Loading drivers/atm/idt77252.c +4 −8 Original line number Diff line number Diff line Loading @@ -3173,14 +3173,10 @@ static void init_sram(struct idt77252_dev *card) (u32) 0xffffffff); } writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); writel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); writel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); writel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); writel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); /* Initialize rate table */ for (i = 0; i < 256; i++) { Loading Loading
drivers/atm/idt77252.c +4 −8 Original line number Diff line number Diff line Loading @@ -3173,14 +3173,10 @@ static void init_sram(struct idt77252_dev *card) (u32) 0xffffffff); } writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); writel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); writel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); writel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); writel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); /* Initialize rate table */ for (i = 0; i < 256; i++) { Loading