Loading Documentation/devicetree/bindings/spi/efm32-spi.txt +4 −4 Original line number Diff line number Diff line Loading @@ -3,24 +3,24 @@ Required properties: - #address-cells: see spi-bus.txt - #size-cells: see spi-bus.txt - compatible: should be "efm32,spi" - compatible: should be "energymicro,efm32-spi" - reg: Offset and length of the register set for the controller - interrupts: pair specifying rx and tx irq - clocks: phandle to the spi clock - cs-gpios: see spi-bus.txt - location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values. - efm32,location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values. Example: spi1: spi@0x4000c400 { /* USART1 */ #address-cells = <1>; #size-cells = <0>; compatible = "efm32,spi"; compatible = "energymicro,efm32-spi"; reg = <0x4000c400 0x400>; interrupts = <15 16>; clocks = <&cmu 20>; cs-gpios = <&gpio 51 1>; // D3 location = <1>; efm32,location = <1>; status = "ok"; ks8851@0 { Loading Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +2 −0 Original line number Diff line number Diff line Loading @@ -10,6 +10,7 @@ Required properties: - pinctrl-names: must contain a "default" entry. - spi-num-chipselects : the number of the chipselect signals. - bus-num : the slave chip chipselect signal number. - big-endian : if DSPI modudle is big endian, the bool will be set in node. Example: dspi0@4002c000 { Loading @@ -24,6 +25,7 @@ dspi0@4002c000 { bus-num = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dspi0_1>; big-endian; status = "okay"; sflash: at26df081a@0 { Loading drivers/spi/Kconfig +2 −1 Original line number Diff line number Diff line Loading @@ -270,6 +270,7 @@ config SPI_FSL_SPI config SPI_FSL_DSPI tristate "Freescale DSPI controller" select SPI_BITBANG select REGMAP_MMIO depends on SOC_VF610 || COMPILE_TEST help This enables support for the Freescale DSPI controller in master Loading Loading @@ -546,7 +547,7 @@ config SPI_DW_MID_DMA config SPI_DW_MMIO tristate "Memory-mapped io interface driver for DW SPI core" depends on SPI_DESIGNWARE && HAVE_CLK depends on SPI_DESIGNWARE # # There are lots of SPI device types, with sensors and memory Loading drivers/spi/spi-dw-mmio.c +1 −1 Original line number Diff line number Diff line Loading @@ -66,7 +66,7 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) if (ret) return ret; dws->bus_num = 0; dws->bus_num = pdev->id; dws->num_cs = 4; dws->max_freq = clk_get_rate(dwsmmio->clk); Loading drivers/spi/spi-dw.c +2 −15 Original line number Diff line number Diff line Loading @@ -276,8 +276,7 @@ static void giveback(struct dw_spi *dws) queue_work(dws->workqueue, &dws->pump_messages); spin_unlock_irqrestore(&dws->lock, flags); last_transfer = list_entry(msg->transfers.prev, struct spi_transfer, last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, transfer_list); if (!last_transfer->cs_change && dws->cs_control) Loading Loading @@ -439,12 +438,6 @@ static void pump_transfers(unsigned long data) if (transfer->speed_hz != speed) { speed = transfer->speed_hz; if (speed > dws->max_freq) { printk(KERN_ERR "MRST SPI0: unsupported" "freq: %dHz\n", speed); message->status = -EIO; goto early_exit; } /* clk_div doesn't support odd number */ clk_div = dws->max_freq / speed; Loading Loading @@ -671,12 +664,6 @@ static int dw_spi_setup(struct spi_device *spi) return 0; } static void dw_spi_cleanup(struct spi_device *spi) { struct chip_data *chip = spi_get_ctldata(spi); kfree(chip); } static int init_queue(struct dw_spi *dws) { INIT_LIST_HEAD(&dws->queue); Loading Loading @@ -806,9 +793,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); master->bus_num = dws->bus_num; master->num_chipselect = dws->num_cs; master->cleanup = dw_spi_cleanup; master->setup = dw_spi_setup; master->transfer = dw_spi_transfer; master->max_speed_hz = dws->max_freq; /* Basic HW init */ spi_hw_init(dws); Loading Loading
Documentation/devicetree/bindings/spi/efm32-spi.txt +4 −4 Original line number Diff line number Diff line Loading @@ -3,24 +3,24 @@ Required properties: - #address-cells: see spi-bus.txt - #size-cells: see spi-bus.txt - compatible: should be "efm32,spi" - compatible: should be "energymicro,efm32-spi" - reg: Offset and length of the register set for the controller - interrupts: pair specifying rx and tx irq - clocks: phandle to the spi clock - cs-gpios: see spi-bus.txt - location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values. - efm32,location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values. Example: spi1: spi@0x4000c400 { /* USART1 */ #address-cells = <1>; #size-cells = <0>; compatible = "efm32,spi"; compatible = "energymicro,efm32-spi"; reg = <0x4000c400 0x400>; interrupts = <15 16>; clocks = <&cmu 20>; cs-gpios = <&gpio 51 1>; // D3 location = <1>; efm32,location = <1>; status = "ok"; ks8851@0 { Loading
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +2 −0 Original line number Diff line number Diff line Loading @@ -10,6 +10,7 @@ Required properties: - pinctrl-names: must contain a "default" entry. - spi-num-chipselects : the number of the chipselect signals. - bus-num : the slave chip chipselect signal number. - big-endian : if DSPI modudle is big endian, the bool will be set in node. Example: dspi0@4002c000 { Loading @@ -24,6 +25,7 @@ dspi0@4002c000 { bus-num = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dspi0_1>; big-endian; status = "okay"; sflash: at26df081a@0 { Loading
drivers/spi/Kconfig +2 −1 Original line number Diff line number Diff line Loading @@ -270,6 +270,7 @@ config SPI_FSL_SPI config SPI_FSL_DSPI tristate "Freescale DSPI controller" select SPI_BITBANG select REGMAP_MMIO depends on SOC_VF610 || COMPILE_TEST help This enables support for the Freescale DSPI controller in master Loading Loading @@ -546,7 +547,7 @@ config SPI_DW_MID_DMA config SPI_DW_MMIO tristate "Memory-mapped io interface driver for DW SPI core" depends on SPI_DESIGNWARE && HAVE_CLK depends on SPI_DESIGNWARE # # There are lots of SPI device types, with sensors and memory Loading
drivers/spi/spi-dw-mmio.c +1 −1 Original line number Diff line number Diff line Loading @@ -66,7 +66,7 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) if (ret) return ret; dws->bus_num = 0; dws->bus_num = pdev->id; dws->num_cs = 4; dws->max_freq = clk_get_rate(dwsmmio->clk); Loading
drivers/spi/spi-dw.c +2 −15 Original line number Diff line number Diff line Loading @@ -276,8 +276,7 @@ static void giveback(struct dw_spi *dws) queue_work(dws->workqueue, &dws->pump_messages); spin_unlock_irqrestore(&dws->lock, flags); last_transfer = list_entry(msg->transfers.prev, struct spi_transfer, last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, transfer_list); if (!last_transfer->cs_change && dws->cs_control) Loading Loading @@ -439,12 +438,6 @@ static void pump_transfers(unsigned long data) if (transfer->speed_hz != speed) { speed = transfer->speed_hz; if (speed > dws->max_freq) { printk(KERN_ERR "MRST SPI0: unsupported" "freq: %dHz\n", speed); message->status = -EIO; goto early_exit; } /* clk_div doesn't support odd number */ clk_div = dws->max_freq / speed; Loading Loading @@ -671,12 +664,6 @@ static int dw_spi_setup(struct spi_device *spi) return 0; } static void dw_spi_cleanup(struct spi_device *spi) { struct chip_data *chip = spi_get_ctldata(spi); kfree(chip); } static int init_queue(struct dw_spi *dws) { INIT_LIST_HEAD(&dws->queue); Loading Loading @@ -806,9 +793,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); master->bus_num = dws->bus_num; master->num_chipselect = dws->num_cs; master->cleanup = dw_spi_cleanup; master->setup = dw_spi_setup; master->transfer = dw_spi_transfer; master->max_speed_hz = dws->max_freq; /* Basic HW init */ spi_hw_init(dws); Loading