Commit 2f05b6b9 authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Stephen Boyd
Browse files

clk: stm32: Add DSI clock for STM32F469 Board 



This patch adds DSI clock for STM32F469 board

Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent fa6f3985

drivers/clk/clk-stm32f4.c

+10 −1
Original line number Diff line number Diff line
@@ -521,7 +521,7 @@ static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = { 
};



static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {

	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },

	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },

	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },

	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },

};
@@ -1047,6 +1047,8 @@ static const char *rtc_parents[4] = { 
	"no-clock", "lse", "lsi", "hse-rtc"

};



static const char *dsi_parent[2] = { NULL, "pll-r" };



static const char *lcd_parent[1] = { "pllsai-r-div" };



static const char *i2s_parents[2] = { "plli2s-r", NULL };
@@ -1156,6 +1158,12 @@ static const struct stm32_aux_clk stm32f469_aux_clk[] = { 
		NO_GATE, 0,

		0

	},

	{

		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),

		STM32F4_RCC_DCKCFGR, 29, 1,

		STM32F4_RCC_APB2ENR, 27,

		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT

	},

};



static const struct stm32_aux_clk stm32f746_aux_clk[] = {
@@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) 
	stm32f4_gate_map = data->gates_map;



	hse_clk = of_clk_get_parent_name(np, 0);

	dsi_parent[0] = hse_clk;



	i2s_in_clk = of_clk_get_parent_name(np, 1);

include/dt-bindings/clock/stm32fx-clock.h

+2 −1
Original line number Diff line number Diff line
@@ -35,8 +35,9 @@ 
#define CLK_SAIQ_PDIV		13

#define CLK_HSI			14

#define CLK_SYSCLK		15

#define CLK_F469_DSI		16



#define END_PRIMARY_CLK		16

#define END_PRIMARY_CLK		17



#define CLK_HDMI_CEC		16

#define CLK_SPDIF		17