Commit 290129c2 authored by Qingqing Zhuo's avatar Qingqing Zhuo Committed by Alex Deucher
Browse files

drm/amd/display: Add CM_BYPASS via debug option 



[Why]
bypass CM block and MPC ogam for debug or triage use.

[How]
create a new flag cm_bypass_mode, which will set both CM_CONTROL
and MPCC_OGAM_MODE to bypass when set to 1.

Signed-off-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a2080098

drivers/gpu/drm/amd/display/dc/dc.h

+3 −0
Original line number Diff line number Diff line
@@ -379,6 +379,9 @@ struct dc_debug_options { 
	 */

	unsigned int force_min_dcfclk_mhz;

	bool disable_timing_sync;

#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	bool cm_in_bypass;

#endif

};



struct dc_debug_data {

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c

+6 −1
Original line number Diff line number Diff line
@@ -52,7 +52,12 @@ static void dpp2_enable_cm_block( 
{

	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);



	REG_UPDATE(CM_CONTROL, CM_BYPASS, 0);

	unsigned int cm_bypass_mode = 0;

	//Temp, put CM in bypass mode

	if (dpp_base->ctx->dc->debug.cm_in_bypass)

		cm_bypass_mode = 1;



	REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);

}

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c

+11 −0
Original line number Diff line number Diff line
@@ -368,6 +368,11 @@ void apply_DEDCN20_305_wa( 
{

	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);



	if (mpc->ctx->dc->debug.cm_in_bypass) {

		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);

		return;

	}



	if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {

		/*hw fixed in new review*/

		return;
@@ -390,10 +395,16 @@ void mpc2_set_output_gamma( 
	enum dc_lut_mode next_mode;

	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);



	if (mpc->ctx->dc->debug.cm_in_bypass) {

		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);

		return;

	}



	if (params == NULL) {

		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);

		return;

	}



	current_mode = mpc20_get_ogam_current(mpc, mpcc_id);

	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

		next_mode = LUT_RAM_B;

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ struct dpp { 


#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	struct pwl_params shaper_params;

	bool cm_bypass_mode;

#endif

};

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

+1 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ struct mpc { 
	struct mpcc mpcc_array[MAX_MPCC];

#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	struct pwl_params blender_params;

	bool cm_bypass_mode;

#endif

};