Commit 23c25876 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-4.15-rc1' of git://git.infradead.org/users/vkoul/slave-dma 

Pull dmaengine updates from Vinod Koul:
 "Updates for this cycle include:

   - new driver for Spreadtrum dma controller, ST MDMA and DMAMUX
     controllers

   - PM support for IMG MDC drivers

   - updates to bcm-sba-raid driver and improvements to sun6i driver

   - subsystem conversion for:
      - timers to use timer_setup()
      - remove usage of PCI pool API
      - usage of %p format specifier

   - minor updates to bunch of drivers"

* tag 'dmaengine-4.15-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (49 commits)
  dmaengine: ti-dma-crossbar: Correct am335x/am43xx mux value type
  dmaengine: dmatest: warn user when dma test times out
  dmaengine: Revert "rcar-dmac: use TCRB instead of TCR for residue"
  dmaengine: stm32_mdma: activate pack/unpack feature
  dmaengine: at_hdmac: Remove unnecessary 0x prefixes before %pad
  dmaengine: coh901318: Remove unnecessary 0x prefixes before %pad
  MAINTAINERS: Step down from a co-maintaner of DW DMAC driver
  dmaengine: pch_dma: Replace PCI pool old API
  dmaengine: Convert timers to use timer_setup()
  dmaengine: sprd: Add Spreadtrum DMA driver
  dt-bindings: dmaengine: Add Spreadtrum SC9860 DMA controller
  dmaengine: sun6i: Retrieve channel count/max request from devicetree
  dmaengine: Build bcm-sba-raid driver as loadable module for iProc SoCs
  dmaengine: bcm-sba-raid: Use common GPL comment header
  dmaengine: bcm-sba-raid: Use only single mailbox channel
  dmaengine: bcm-sba-raid: serialize dma_cookie_complete() using reqs_lock
  dmaengine: pl330: fix descriptor allocation fail
  dmaengine: rcar-dmac: use TCRB instead of TCR for residue
  dmaengine: sun6i: Add support for Allwinner A64 and compatibles
  arm64: allwinner: a64: Add devicetree binding for DMA controller
  ...
parents e0ca3826 cecd5fc5

Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt

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@@ -3,6 +3,8 @@ 
Required Properties:

Required Properties:

-compatible: "renesas,<soctype>-usb-dmac", "renesas,usb-dmac" as fallback.

-compatible: "renesas,<soctype>-usb-dmac", "renesas,usb-dmac" as fallback.

	Examples with soctypes are:

	Examples with soctypes are:

	  - "renesas,r8a7743-usb-dmac" (RZ/G1M)

	  - "renesas,r8a7745-usb-dmac" (RZ/G1E)

	  - "renesas,r8a7790-usb-dmac" (R-Car H2)

	  - "renesas,r8a7790-usb-dmac" (R-Car H2)

	  - "renesas,r8a7791-usb-dmac" (R-Car M2-W)

	  - "renesas,r8a7791-usb-dmac" (R-Car M2-W)

	  - "renesas,r8a7793-usb-dmac" (R-Car M2-N)

	  - "renesas,r8a7793-usb-dmac" (R-Car M2-N)

Documentation/devicetree/bindings/dma/sprd-dma.txt

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* Spreadtrum DMA controller



This binding follows the generic DMA bindings defined in dma.txt.



Required properties:

- compatible: Should be "sprd,sc9860-dma".

- reg: Should contain DMA registers location and length.

- interrupts: Should contain one interrupt shared by all channel.

- #dma-cells: must be <1>. Used to represent the number of integer

	cells in the dmas property of client device.

- #dma-channels : Number of DMA channels supported. Should be 32.

- clock-names: Should contain the clock of the DMA controller.

- clocks: Should contain a clock specifier for each entry in clock-names.



Example:



Controller:

apdma: dma-controller@20100000 {

	compatible = "sprd,sc9860-dma";

	reg = <0x20100000 0x4000>;

	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;

	#dma-cells = <1>;

	#dma-channels = <32>;

	clock-names = "enable";

	clocks = <&clk_ap_ahb_gates 5>;

};





Client:

DMA clients connected to the Spreadtrum DMA controller must use the format

described in the dma.txt file, using a two-cell specifier for each channel.

The two cells in order are:

1. A phandle pointing to the DMA controller.

2. The channel id.



spi0: spi@70a00000{

	...

	dma-names = "rx_chn", "tx_chn";

	dmas = <&apdma 11>, <&apdma 12>;

	...

};

Documentation/devicetree/bindings/dma/stm32-dma.txt

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@@ -13,6 +13,7 @@ Required properties: 
- #dma-cells : Must be <4>. See DMA client paragraph for more details.

- #dma-cells : Must be <4>. See DMA client paragraph for more details.





Optional properties:

Optional properties:

- dma-requests : Number of DMA requests supported.

- resets: Reference to a reset controller asserting the DMA controller

- resets: Reference to a reset controller asserting the DMA controller

- st,mem2mem: boolean; if defined, it indicates that the controller supports

- st,mem2mem: boolean; if defined, it indicates that the controller supports

  memory-to-memory transfer

  memory-to-memory transfer
@@ -34,12 +35,13 @@ Example: 
		#dma-cells = <4>;

		#dma-cells = <4>;

		st,mem2mem;

		st,mem2mem;

		resets = <&rcc 150>;

		resets = <&rcc 150>;

		dma-requests = <8>;

	};

	};





* DMA client

* DMA client





DMA clients connected to the STM32 DMA controller must use the format

DMA clients connected to the STM32 DMA controller must use the format

described in the dma.txt file, using a five-cell specifier for each

described in the dma.txt file, using a four-cell specifier for each

channel: a phandle to the DMA controller plus the following four integer cells:

channel: a phandle to the DMA controller plus the following four integer cells:





1. The channel id

1. The channel id

Documentation/devicetree/bindings/dma/stm32-dmamux.txt

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STM32 DMA MUX (DMA request router)



Required properties:

- compatible:	"st,stm32h7-dmamux"

- reg:		Memory map for accessing module

- #dma-cells:	Should be set to <3>.

		First parameter is request line number.

		Second is DMA channel configuration

		Third is Fifo threshold

		For more details about the three cells, please see

		stm32-dma.txt documentation binding file

- dma-masters:	Phandle pointing to the DMA controllers.

		Several controllers are allowed. Only "st,stm32-dma" DMA

		compatible are supported.



Optional properties:

- dma-channels : Number of DMA requests supported.

- dma-requests : Number of DMAMUX requests supported.

- resets: Reference to a reset controller asserting the DMA controller

- clocks: Input clock of the DMAMUX instance.



Example:



/* DMA controller 1 */

dma1: dma-controller@40020000 {

	compatible = "st,stm32-dma";

	reg = <0x40020000 0x400>;

	interrupts = <11>,

		     <12>,

		     <13>,

		     <14>,

		     <15>,

		     <16>,

		     <17>,

		     <47>;

	clocks = <&timer_clk>;

	#dma-cells = <4>;

	st,mem2mem;

	resets = <&rcc 150>;

	dma-channels = <8>;

	dma-requests = <8>;

};



/* DMA controller 1 */

dma2: dma@40020400 {

	compatible = "st,stm32-dma";

	reg = <0x40020400 0x400>;

	interrupts = <56>,

		     <57>,

		     <58>,

		     <59>,

		     <60>,

		     <68>,

		     <69>,

		     <70>;

	clocks = <&timer_clk>;

	#dma-cells = <4>;

	st,mem2mem;

	resets = <&rcc 150>;

	dma-channels = <8>;

	dma-requests = <8>;

};



/* DMA mux */

dmamux1: dma-router@40020800 {

	compatible = "st,stm32h7-dmamux";

	reg = <0x40020800 0x3c>;

	#dma-cells = <3>;

	dma-requests = <128>;

	dma-channels = <16>;

	dma-masters = <&dma1 &dma2>;

	clocks = <&timer_clk>;

};



/* DMA client */

usart1: serial@40011000 {

	compatible = "st,stm32-usart", "st,stm32-uart";

	reg = <0x40011000 0x400>;

	interrupts = <37>;

	clocks = <&timer_clk>;

	dmas = <&dmamux1 41 0x414 0>,

	       <&dmamux1 42 0x414 0>;

	dma-names = "rx", "tx";

};

Documentation/devicetree/bindings/dma/stm32-mdma.txt

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* STMicroelectronics STM32 MDMA controller



The STM32 MDMA is a general-purpose direct memory access controller capable of

supporting 64 independent DMA channels with 256 HW requests.



Required properties:

- compatible: Should be "st,stm32h7-mdma"

- reg: Should contain MDMA registers location and length. This should include

  all of the per-channel registers.

- interrupts: Should contain the MDMA interrupt.

- clocks: Should contain the input clock of the DMA instance.

- resets: Reference to a reset controller asserting the DMA controller.

- #dma-cells : Must be <5>. See DMA client paragraph for more details.



Optional properties:

- dma-channels: Number of DMA channels supported by the controller.

- dma-requests: Number of DMA request signals supported by the controller.

- st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via

  AHB bus.



Example:



	mdma1: dma@52000000 {

		compatible = "st,stm32h7-mdma";

		reg = <0x52000000 0x1000>;

		interrupts = <122>;

		clocks = <&timer_clk>;

		resets = <&rcc 992>;

		#dma-cells = <5>;

		dma-channels = <16>;

		dma-requests = <32>;

		st,ahb-addr-masks = <0x20000000>, <0x00000000>;

	};



* DMA client



DMA clients connected to the STM32 MDMA controller must use the format

described in the dma.txt file, using a five-cell specifier for each channel:

a phandle to the MDMA controller plus the following five integer cells:



1. The request line number

2. The priority level

	0x00: Low

	0x01: Medium

	0x10: High

	0x11: Very high

3. A 32bit mask specifying the DMA channel configuration

 -bit 0-1: Source increment mode

	0x00: Source address pointer is fixed

	0x10: Source address pointer is incremented after each data transfer

	0x11: Source address pointer is decremented after each data transfer

 -bit 2-3: Destination increment mode

	0x00: Destination address pointer is fixed

	0x10: Destination address pointer is incremented after each data

	transfer

	0x11: Destination address pointer is decremented after each data

	transfer

 -bit 8-9: Source increment offset size

	0x00: byte (8bit)

	0x01: half-word (16bit)

	0x10: word (32bit)

	0x11: double-word (64bit)

 -bit 10-11: Destination increment offset size

	0x00: byte (8bit)

	0x01: half-word (16bit)

	0x10: word (32bit)

	0x11: double-word (64bit)

-bit 25-18: The number of bytes to be transferred in a single transfer

	(min = 1 byte, max = 128 bytes)

-bit 29:28: Trigger Mode

	0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)

	0x01: Each MDMA request triggers a block transfer (max 64K bytes)

	0x10: Each MDMA request triggers a repeated block transfer

	0x11: Each MDMA request triggers a linked list transfer

4. A 32bit value specifying the register to be used to acknowledge the request

   if no HW ack signal is used by the MDMA client

5. A 32bit mask specifying the value to be written to acknowledge the request

   if no HW ack signal is used by the MDMA client



Example:



	i2c4: i2c@5c002000 {

		compatible = "st,stm32f7-i2c";

		reg = <0x5c002000 0x400>;

		interrupts = <95>,

			     <96>;

		clocks = <&timer_clk>;

		#address-cells = <1>;

		#size-cells = <0>;

		dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>,

		       <&mdma1 37 0x0 0x40002 0x0 0x0>;

		dma-names = "rx", "tx";

		status = "disabled";

	};