Commit 0926c07d authored by popcornmix's avatar popcornmix
Browse files

Revert "drm/vc4: Add T-format scanout support." 

This reverts commit 85e9ae25.
parent 22e36d57

drivers/gpu/drm/vc4/vc4_plane.c

+4 −28
Original line number Original line Diff line number Diff line
@@ -22,7 +22,6 @@ 
#include "vc4_regs.h"

#include "vc4_regs.h"

#include "drm_atomic.h"

#include "drm_atomic.h"

#include "drm_atomic_helper.h"

#include "drm_atomic_helper.h"

#include "drm_fourcc.h"

#include "drm_fb_cma_helper.h"

#include "drm_fb_cma_helper.h"

#include "drm_plane_helper.h"

#include "drm_plane_helper.h"
@@ -500,8 +499,8 @@ static int vc4_plane_mode_set(struct drm_plane *plane, 
	u32 ctl0_offset = vc4_state->dlist_count;

	u32 ctl0_offset = vc4_state->dlist_count;

	const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);

	const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);

	int num_planes = drm_format_num_planes(format->drm);

	int num_planes = drm_format_num_planes(format->drm);

	u32 scl0, scl1, pitch0;

	u32 scl0, scl1;

	u32 lbm_size, tiling = SCALER_CTL0_TILING_LINEAR;

	u32 lbm_size;

	unsigned long irqflags;

	unsigned long irqflags;

	int ret, i;

	int ret, i;
@@ -542,31 +541,11 @@ static int vc4_plane_mode_set(struct drm_plane *plane, 
		scl1 = vc4_get_scl_field(state, 0);

		scl1 = vc4_get_scl_field(state, 0);

	}

	}





	switch (fb->modifier[0]) {

	case DRM_FORMAT_MOD_NONE:

		tiling = SCALER_CTL0_TILING_LINEAR;

		pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);

		break;

	case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:

		tiling = SCALER_CTL0_TILING_256B_OR_T;



		pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET),

			  VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L),

			  VC4_SET_FIELD((vc4_state->src_w[0] + 31) >> 5,

					SCALER_PITCH0_TILE_WIDTH_R));

		break;

	default:

		DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",

			      (long long)fb->modifier[0]);

		return -EINVAL;

	}



	/* Control word */

	/* Control word */

	vc4_dlist_write(vc4_state,

	vc4_dlist_write(vc4_state,

			SCALER_CTL0_VALID |

			SCALER_CTL0_VALID |

			(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |

			(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |

			(format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |

			(format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |

			VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |

			(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |

			(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |

			VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |

			VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |

			VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));

			VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
@@ -620,11 +599,8 @@ static int vc4_plane_mode_set(struct drm_plane *plane, 
	for (i = 0; i < num_planes; i++)

	for (i = 0; i < num_planes; i++)

		vc4_dlist_write(vc4_state, 0xc0c0c0c0);

		vc4_dlist_write(vc4_state, 0xc0c0c0c0);





	/* Pitch word 0 */

	/* Pitch word 0/1/2 */

	vc4_dlist_write(vc4_state, pitch0);

	for (i = 0; i < num_planes; i++) {



	/* Pitch word 1/2 */

	for (i = 1; i < num_planes; i++) {

		vc4_dlist_write(vc4_state,

		vc4_dlist_write(vc4_state,

				VC4_SET_FIELD(fb->pitches[i], SCALER_SRC_PITCH));

				VC4_SET_FIELD(fb->pitches[i], SCALER_SRC_PITCH));

	}

	}

drivers/gpu/drm/vc4/vc4_regs.h

+0 −19
Original line number Original line Diff line number Diff line
@@ -709,13 +709,6 @@ enum hvs_pixel_format { 
#define SCALER_CTL0_SIZE_MASK			VC4_MASK(29, 24)

#define SCALER_CTL0_SIZE_MASK			VC4_MASK(29, 24)

#define SCALER_CTL0_SIZE_SHIFT			24

#define SCALER_CTL0_SIZE_SHIFT			24





#define SCALER_CTL0_TILING_MASK			VC4_MASK(21, 20)

#define SCALER_CTL0_TILING_SHIFT		20

#define SCALER_CTL0_TILING_LINEAR		0

#define SCALER_CTL0_TILING_64B			1

#define SCALER_CTL0_TILING_128B			2

#define SCALER_CTL0_TILING_256B_OR_T		3



#define SCALER_CTL0_HFLIP                       BIT(16)

#define SCALER_CTL0_HFLIP                       BIT(16)

#define SCALER_CTL0_VFLIP                       BIT(15)

#define SCALER_CTL0_VFLIP                       BIT(15)
@@ -845,19 +838,7 @@ enum hvs_pixel_format { 
#define SCALER_PPF_KERNEL_OFFSET_SHIFT		0

#define SCALER_PPF_KERNEL_OFFSET_SHIFT		0

#define SCALER_PPF_KERNEL_UNCACHED		BIT(31)

#define SCALER_PPF_KERNEL_UNCACHED		BIT(31)





/* PITCH0/1/2 fields for raster. */

#define SCALER_SRC_PITCH_MASK			VC4_MASK(15, 0)

#define SCALER_SRC_PITCH_MASK			VC4_MASK(15, 0)

#define SCALER_SRC_PITCH_SHIFT			0

#define SCALER_SRC_PITCH_SHIFT			0





/* PITCH0 fields for T-tiled. */

#define SCALER_PITCH0_TILE_WIDTH_L_MASK		VC4_MASK(22, 16)

#define SCALER_PITCH0_TILE_WIDTH_L_SHIFT	16

#define SCALER_PITCH0_TILE_LINE_DIR		BIT(15)

#define SCALER_PITCH0_TILE_INITIAL_LINE_DIR	BIT(14)

/* Y offset within a tile. */

#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 7)

#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	7

#define SCALER_PITCH0_TILE_WIDTH_R_MASK		VC4_MASK(6, 0)

#define SCALER_PITCH0_TILE_WIDTH_R_SHIFT	0



#endif /* VC4_REGS_H */
 
#endif /* VC4_REGS_H */

include/uapi/drm/drm_fourcc.h

+0 −22
Original line number Original line Diff line number Diff line
@@ -159,7 +159,6 @@ extern "C" { 
#define DRM_FORMAT_MOD_VENDOR_NV      0x03

#define DRM_FORMAT_MOD_VENDOR_NV      0x03

#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04

#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04

#define DRM_FORMAT_MOD_VENDOR_QCOM    0x05

#define DRM_FORMAT_MOD_VENDOR_QCOM    0x05

#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07

/* add more to the end as needed */

/* add more to the end as needed */





#define fourcc_mod_code(vendor, val) \

#define fourcc_mod_code(vendor, val) \
@@ -234,27 +233,6 @@ extern "C" { 
 */

 */

#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)

#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)





/*

 * Broadcom VC4 "T" format

 *

 * This is the primary layout that the V3D GPU can texture from (it

 * can't do linear).  The T format has:

 *

 * - 64b utiles of pixels in a raster-order grid according to cpp.  It's 4x4

 *   pixels at 32 bit depth.

 *

 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually

 *   16x16 pixels).

 *

 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On

 *   even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows

 *   they're (TR, BR, BL, TL), where bottom left is start of memory.

 *

 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k

 *   tiles) or right-to-left (odd rows of 4k tiles).

 */

#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)



#if defined(__cplusplus)

#if defined(__cplusplus)

}

}

#endif

#endif