Loading arch/arm/boot/dts/mmp2.dtsi +36 −0 Original line number Diff line number Diff line Loading @@ -117,6 +117,42 @@ reg-names = "mux status", "mux mask"; mrvl,intc-nr-irqs = <2>; }; mmc1: mmc@d4280000 { compatible = "mrvl,pxav3-mmc"; reg = <0xd4280000 0x120>; clocks = <&soc_clocks MMP2_CLK_SDH0>; clock-names = "io"; interrupts = <39>; status = "disabled"; }; mmc2: mmc@d4280800 { compatible = "mrvl,pxav3-mmc"; reg = <0xd4280800 0x120>; clocks = <&soc_clocks MMP2_CLK_SDH1>; clock-names = "io"; interrupts = <52>; status = "disabled"; }; mmc3: mmc@d4281000 { compatible = "mrvl,pxav3-mmc"; reg = <0xd4281000 0x120>; clocks = <&soc_clocks MMP2_CLK_SDH2>; clock-names = "io"; interrupts = <53>; status = "disabled"; }; mmc4: mmc@d4281800 { compatible = "mrvl,pxav3-mmc"; reg = <0xd4281800 0x120>; clocks = <&soc_clocks MMP2_CLK_SDH3>; clock-names = "io"; interrupts = <54>; status = "disabled"; }; }; apb@d4000000 { /* APB */ Loading Loading
arch/arm/boot/dts/mmp2.dtsi +36 −0 Original line number Diff line number Diff line Loading @@ -117,6 +117,42 @@ reg-names = "mux status", "mux mask"; mrvl,intc-nr-irqs = <2>; }; mmc1: mmc@d4280000 { compatible = "mrvl,pxav3-mmc"; reg = <0xd4280000 0x120>; clocks = <&soc_clocks MMP2_CLK_SDH0>; clock-names = "io"; interrupts = <39>; status = "disabled"; }; mmc2: mmc@d4280800 { compatible = "mrvl,pxav3-mmc"; reg = <0xd4280800 0x120>; clocks = <&soc_clocks MMP2_CLK_SDH1>; clock-names = "io"; interrupts = <52>; status = "disabled"; }; mmc3: mmc@d4281000 { compatible = "mrvl,pxav3-mmc"; reg = <0xd4281000 0x120>; clocks = <&soc_clocks MMP2_CLK_SDH2>; clock-names = "io"; interrupts = <53>; status = "disabled"; }; mmc4: mmc@d4281800 { compatible = "mrvl,pxav3-mmc"; reg = <0xd4281800 0x120>; clocks = <&soc_clocks MMP2_CLK_SDH3>; clock-names = "io"; interrupts = <54>; status = "disabled"; }; }; apb@d4000000 { /* APB */ Loading