Commit ff970453 authored by Larry Finger's avatar Larry Finger Committed by Kalle Valo
Browse files

rtlwifi: rtl8192{c,u}: Remove CamelCase variables 



This patch affects modules rtl8192ce, rtl8192cu, and rtl8192com.

The following checkpatch exceptions are also fixed:

CHECK: No space is necessary after a cast
#237: FILE: drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c:90:
+                                                     (u8 *) (&rfstate));

CHECK: No space is necessary after a cast
#744: FILE: drivers/net/wireless/realtek/rtlwifi/rtl8192ce/rf.c:329:
+                       pwr_val[i] = (u8) ((writeval & (0x7f <<

CHECK: No space is necessary after a cast
#784: FILE: drivers/net/wireless/realtek/rtlwifi/rtl8192ce/rf.c:365:
+                                              (u8) writeval);

CHECK: spaces preferred around that '/' (ctx:VxV)
#963: FILE: drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c:513:
+               txqpageunit = txqpagenum/outepnum;
                                        ^

CHECK: Unnecessary parentheses around 'outepnum > 1'
#975: FILE: drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c:521:
+               if ((outepnum > 1) && (txqremaininpage))

CHECK: Alignment should match open parenthesis
#1059: FILE: drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c:617:
+static void _rtl92cu_init_chipn_two_out_ep_priority(struct ieee80211_hw *hw,
                                                                bool wmm_enable,

ERROR: "foo * bar" should be "foo *bar"
#1940: FILE: drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c:591:
+void rtl92cu_fill_fake_txdesc(struct ieee80211_hw *hw, u8 *pdesc,

Note that not all checkpatch exceptions are addressed. Those will be
handled in later patches.

Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent d4201106

drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.h

+2 −2
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ 
#define DM_DIG_FA_TH1				0x100

#define DM_DIG_FA_TH2				0x200



#define RXPATHSELECTION_SS_TH_lOW		30

#define RXPATHSELECTION_SS_TH_LOW		30

#define RXPATHSELECTION_DIFF_TH			18



#define DM_RATR_STA_INIT			0
@@ -38,7 +38,7 @@ 
#define CTS2SELF_THVAL				30

#define REGC38_TH				20



#define WAIOTTHVal				25

#define WAIOTTHVAL				25



#define TXHIGHPWRLEVEL_NORMAL			0

#define TXHIGHPWRLEVEL_LEVEL1			1

drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.c

+7 −7
Original line number Diff line number Diff line
@@ -57,27 +57,27 @@ static void _rtl92c_write_fw(struct ieee80211_hw *hw, 
	RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size);

	is_version_b = IS_NORMAL_CHIP(version);

	if (is_version_b) {

		u32 pageNums, remainsize;

		u32 pagenums, remainsize;

		u32 page, offset;



		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)

			rtl_fill_dummy(bufferptr, &size);



		pageNums = size / FW_8192C_PAGE_SIZE;

		pagenums = size / FW_8192C_PAGE_SIZE;

		remainsize = size % FW_8192C_PAGE_SIZE;



		if (pageNums > 4)

		if (pagenums > 4)

			pr_err("Page numbers should not greater then 4\n");



		for (page = 0; page < pageNums; page++) {

		for (page = 0; page < pagenums; page++) {

			offset = page * FW_8192C_PAGE_SIZE;

			rtl_fw_page_write(hw, page, (bufferptr + offset),

					  FW_8192C_PAGE_SIZE);

		}



		if (remainsize) {

			offset = pageNums * FW_8192C_PAGE_SIZE;

			page = pageNums;

			offset = pagenums * FW_8192C_PAGE_SIZE;

			page = pagenums;

			rtl_fw_page_write(hw, page, (bufferptr + offset),

					  remainsize);

		}
@@ -96,7 +96,7 @@ static int _rtl92c_fw_free_to_go(struct ieee80211_hw *hw) 
	do {

		value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);

	} while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&

		 (!(value32 & FWDL_ChkSum_rpt)));

		 (!(value32 & FWDL_CHKSUM_RPT)));



	if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {

		pr_err("chksum report fail! REG_MCUFWDL:0x%08x .\n",

drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c

+12 −12
Original line number Diff line number Diff line
@@ -217,7 +217,7 @@ bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw) 


EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);



void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,

void _rtl92c_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,

					    u32 regaddr, u32 bitmask,

					    u32 data)

{
@@ -371,7 +371,7 @@ void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw, 
		rtlphy->pwrgroup_cnt++;

	}

}

EXPORT_SYMBOL(_rtl92c_store_pwrIndex_diffrate_offset);

EXPORT_SYMBOL(_rtl92c_store_pwrindex_diffrate_offset);



void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)

{
@@ -430,10 +430,10 @@ void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 
	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =

	    RFPGA0_XB_LSSIPARAMETER;



	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;

	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;

	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;

	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;

	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;

	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;

	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;

	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;



	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;

	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
@@ -1098,19 +1098,19 @@ static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw, 
static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,

				     u32 *addareg, bool is_patha_on, bool is2t)

{

	u32 pathOn;

	u32 pathon;

	u32 i;



	pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;

	pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;

	if (false == is2t) {

		pathOn = 0x0bdb25a0;

		pathon = 0x0bdb25a0;

		rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);

	} else {

		rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);

		rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);

	}



	for (i = 1; i < IQK_ADDA_REG_NUM; i++)

		rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);

		rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);

}



static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
@@ -1339,7 +1339,7 @@ static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, 


	if (is_hal_stop(rtlhal)) {

		rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);

		rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);

		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);

	}

	if (is2t) {

		if (bmain)

drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.h

+3 −3
Original line number Diff line number Diff line
@@ -22,9 +22,9 @@ 


#define LOOP_LIMIT			5

#define MAX_STALL_TIME			50

#define AntennaDiversityValue		0x80

#define ANTENNADIVERSITYVALUE		0x80

#define MAX_TXPWR_IDX_NMODE_92S		63

#define Reset_Cnt_Limit			3

#define RESET_CNT_LIMIT			3



#define IQK_ADDA_REG_NUM		16

#define IQK_MAC_REG_NUM			4
@@ -220,7 +220,7 @@ void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw, 
				 enum radio_path rfpath, u32 offset,

				 u32 data);

bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);

void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,

void _rtl92c_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,

					    u32 regaddr, u32 bitmask,

					    u32 data);

bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/dm.h

+2 −2
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
#define DM_DIG_FA_TH1				0x100

#define DM_DIG_FA_TH2				0x200



#define RXPATHSELECTION_SS_TH_lOW		30

#define RXPATHSELECTION_SS_TH_LOW		30

#define RXPATHSELECTION_DIFF_TH			18



#define DM_RATR_STA_INIT			0
@@ -33,7 +33,7 @@ 
#define CTS2SELF_THVAL				30

#define REGC38_TH				20



#define WAIOTTHVal				25

#define WAIOTTHVAL				25



#define TXHIGHPWRLEVEL_NORMAL			0

#define TXHIGHPWRLEVEL_LEVEL1			1