Commit f817586c authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: re-init modeset hw state after gpu reset 



After a gpu reset we need to re-init some of the hw state we only
initialize when modeset is enabled, like rc6, hw contexts or render/GT
core clock gating and workaround register settings.

Note that this patch has a small change in the resume code:
- rc6 on gen6+ is only restored for the modeset case (for more
  consistency with other callsites). This is no problem because recent
  kernels refuse to load drm/i915 without kms on gen6+
- rc6/emon on ilk is only restored for the modeset case. This is no
  problem because rc6 is disabled by default on ilk, and ums on ilk
  has never really been a supported option outside of horrible rhel
  backports.

v2: Chris Wilson noticed that we not only fail to restore the clock
gating settings after gpu reset.

v3: Move the call to modeset_init_hw in _reset out of the
struct_mutext protected area - other callers don't hold it, too.

Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f8413190

drivers/gpu/drm/i915/i915_drv.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -851,9 +851,14 @@ int i915_reset(struct drm_device *dev, u8 flags) 
		i915_gem_init_ppgtt(dev);

		i915_gem_init_ppgtt(dev);





		mutex_unlock(&dev->struct_mutex);

		mutex_unlock(&dev->struct_mutex);



		if (drm_core_check_feature(dev, DRIVER_MODESET))

			intel_modeset_init_hw(dev);



		drm_irq_uninstall(dev);

		drm_irq_uninstall(dev);

		drm_mode_config_reset(dev);

		drm_mode_config_reset(dev);

		drm_irq_install(dev);

		drm_irq_install(dev);



		mutex_lock(&dev->struct_mutex);

		mutex_lock(&dev->struct_mutex);

	}

	}

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -1433,6 +1433,7 @@ static inline void intel_unregister_dsm_handler(void) { return; } 
#endif /* CONFIG_ACPI */

#endif /* CONFIG_ACPI */





/* modesetting */

/* modesetting */

extern void intel_modeset_init_hw(struct drm_device *dev);

extern void intel_modeset_init(struct drm_device *dev);

extern void intel_modeset_init(struct drm_device *dev);

extern void intel_modeset_gem_init(struct drm_device *dev);

extern void intel_modeset_gem_init(struct drm_device *dev);

extern void intel_modeset_cleanup(struct drm_device *dev);

extern void intel_modeset_cleanup(struct drm_device *dev);

drivers/gpu/drm/i915/i915_suspend.c

+1 −11
Original line number Original line Diff line number Diff line
@@ -879,17 +879,7 @@ int i915_restore_state(struct drm_device *dev) 
	mutex_unlock(&dev->struct_mutex);

	mutex_unlock(&dev->struct_mutex);





	if (drm_core_check_feature(dev, DRIVER_MODESET))

	if (drm_core_check_feature(dev, DRIVER_MODESET))

		intel_init_clock_gating(dev);

		intel_modeset_init_hw(dev);



	if (IS_IRONLAKE_M(dev)) {

		ironlake_enable_drps(dev);

		intel_init_emon(dev);

	}



	if (INTEL_INFO(dev)->gen >= 6) {

		gen6_enable_rps(dev_priv);

		gen6_update_ring_freq(dev_priv);

	}





	mutex_lock(&dev->struct_mutex);

	mutex_lock(&dev->struct_mutex);

drivers/gpu/drm/i915/intel_display.c

+18 −11
Original line number Original line Diff line number Diff line
@@ -9530,6 +9530,23 @@ static void i915_disable_vga(struct drm_device *dev) 
	POSTING_READ(vga_reg);

	POSTING_READ(vga_reg);

}

}





void intel_modeset_init_hw(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	intel_init_clock_gating(dev);



	if (IS_IRONLAKE_M(dev)) {

		ironlake_enable_drps(dev);

		intel_init_emon(dev);

	}



	if (IS_GEN6(dev) || IS_GEN7(dev)) {

		gen6_enable_rps(dev_priv);

		gen6_update_ring_freq(dev_priv);

	}

}



void intel_modeset_init(struct drm_device *dev)

void intel_modeset_init(struct drm_device *dev)

{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -9575,17 +9592,7 @@ void intel_modeset_init(struct drm_device *dev) 
	i915_disable_vga(dev);

	i915_disable_vga(dev);

	intel_setup_outputs(dev);

	intel_setup_outputs(dev);





	intel_init_clock_gating(dev);

	intel_modeset_init_hw(dev);



	if (IS_IRONLAKE_M(dev)) {

		ironlake_enable_drps(dev);

		intel_init_emon(dev);

	}



	if (IS_GEN6(dev) || IS_GEN7(dev)) {

		gen6_enable_rps(dev_priv);

		gen6_update_ring_freq(dev_priv);

	}





	INIT_WORK(&dev_priv->idle_work, intel_idle_update);

	INIT_WORK(&dev_priv->idle_work, intel_idle_update);

	setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,

	setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,