Commit edc6f389 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

radeon: fix PCI bus mastering support enables. 



Someone noticed these registers moved around for later chips,
so we redo the codepaths per-chip. PCIE chips don't appear to
require explicit enables.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent b2ceddfa

drivers/gpu/drm/radeon/radeon_cp.c

+14 −2
Original line number Diff line number Diff line
@@ -363,6 +363,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 
				     R300_cp_microcode[i][0]);

		}

	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {

		DRM_INFO("Loading R400 Microcode\n");

		for (i = 0; i < 256; i++) {
@@ -652,8 +653,18 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev, 
	RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);



	/* Turn on bus mastering */

	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {

		/* rs400, rs690/rs740 */

		tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS;

		RADEON_WRITE(RADEON_BUS_CNTL, tmp);

	} else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||

		    ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) {

		/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */

		tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;

		RADEON_WRITE(RADEON_BUS_CNTL, tmp);

	} /* PCIE cards appears to not need this */



	dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;

	RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
@@ -1719,6 +1730,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags) 
	case CHIP_R300:

	case CHIP_R350:

	case CHIP_R420:

	case CHIP_R423:

	case CHIP_RV410:

	case CHIP_RV515:

	case CHIP_R520:

drivers/gpu/drm/radeon/radeon_drv.h

+25 −0
Original line number Diff line number Diff line
@@ -122,6 +122,7 @@ enum radeon_family { 
	CHIP_RV350,

	CHIP_RV380,

	CHIP_R420,

	CHIP_R423,

	CHIP_RV410,

	CHIP_RS400,

	CHIP_RS480,
@@ -439,8 +440,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, 
#	define RADEON_SCISSOR_1_ENABLE		(1 << 29)

#	define RADEON_SCISSOR_2_ENABLE		(1 << 30)



/*

 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)

 * don't have an explicit bus mastering disable bit.  It's handled

 * by the PCI D-states.  PMI_BM_DIS disables D-state bus master

 * handling, not bus mastering itself.

 */

#define RADEON_BUS_CNTL			0x0030

/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */

#	define RADEON_BUS_MASTER_DIS		(1 << 6)

/* rs400, rs690/rs740 */

#	define RS400_BUS_MASTER_DIS		(1 << 14)

#	define RS400_MSI_REARM		        (1 << 20)

/* see RS480_MSI_REARM in AIC_CNTL for rs480 */



#define RADEON_BUS_CNTL1		0x0034

#	define RADEON_PMI_BM_DIS		(1 << 2)

#	define RADEON_PMI_INT_DIS		(1 << 3)



#define RV370_BUS_CNTL			0x004c

#	define RV370_PMI_BM_DIS		        (1 << 5)

#	define RV370_PMI_INT_DIS		(1 << 6)



#define RADEON_MSI_REARM_EN		0x0160

/* rv370/rv380, rv410, r423/r430/r480, r5xx */

#	define RV370_MSI_REARM_EN		(1 << 0)



#define RADEON_CLOCK_CNTL_DATA		0x000c

#	define RADEON_PLL_WR_EN			(1 << 7)
@@ -913,6 +937,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, 


#define RADEON_AIC_CNTL			0x01d0

#	define RADEON_PCIGART_TRANSLATE_EN	(1 << 0)

#	define RS480_MSI_REARM	                (1 << 3)

#define RADEON_AIC_STAT			0x01d4

#define RADEON_AIC_PT_BASE		0x01d8

#define RADEON_AIC_LO_ADDR		0x01dc

include/drm/drm_pciids.h

+22 −22
Original line number Diff line number Diff line
@@ -84,18 +84,18 @@ 
	{0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \

	{0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \

	{0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
@@ -124,16 +124,16 @@ 
	{0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \

	{0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \

	{0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \