Commit e235f7b8 authored by Peter Chen's avatar Peter Chen Committed by Felipe Balbi
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usb: phy: mxs: add delay before set phyctrl.clkgate 



There is a request from IC engineer that if we doesn't
set phypwd as 0xffffffff, we need to delay about five
32Khz cycles before set phy's pwd register, otherwise,
the wakeup signal may can't wake up controller.

Signed-off-by: default avatarPeter Chen <peter.chen@freescale.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent efdbd3a5

drivers/usb/phy/phy-mxs-usb.c

+9 −3
Original line number Diff line number Diff line
@@ -371,10 +371,16 @@ static int mxs_phy_suspend(struct usb_phy *x, int suspend) 
		 * connect. The low speed connection will have problem at

		 * very rare cases during usb suspend and resume process.

		 */

		if (low_speed_connection & vbus_is_on)

			writel(0xfffbffff, x->io_priv + HW_USBPHY_PWD);

		else

		if (low_speed_connection & vbus_is_on) {

			/*

			 * If value to be set as pwd value is not 0xffffffff,

			 * several 32Khz cycles are needed.

			 */

			mxs_phy_clock_switch_delay();

			writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);

		} else {

			writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);

		}

		writel(BM_USBPHY_CTRL_CLKGATE,

		       x->io_priv + HW_USBPHY_CTRL_SET);

		clk_disable_unprepare(mxs_phy->clk);