Loading arch/powerpc/boot/dts/gef_ppc9a.dts +13 −0 Original line number Diff line number Diff line Loading @@ -167,6 +167,19 @@ soc@fef00000 { reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; mcm-law@0 { compatible = "fsl,mcm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; mcm@1000 { compatible = "fsl,mpc8641-mcm", "fsl,mcm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; Loading arch/powerpc/boot/dts/gef_sbc310.dts +13 −0 Original line number Diff line number Diff line Loading @@ -166,6 +166,19 @@ soc@fef00000 { reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; mcm-law@0 { compatible = "fsl,mcm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; mcm@1000 { compatible = "fsl,mpc8641-mcm", "fsl,mcm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; Loading arch/powerpc/boot/dts/gef_sbc610.dts +13 −0 Original line number Diff line number Diff line Loading @@ -131,6 +131,19 @@ soc@fef00000 { reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; mcm-law@0 { compatible = "fsl,mcm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; mcm@1000 { compatible = "fsl,mpc8641-mcm", "fsl,mcm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; Loading arch/powerpc/boot/dts/mpc8610_hpcd.dts +13 −0 Original line number Diff line number Diff line Loading @@ -115,6 +115,19 @@ soc@e0000000 { reg = <0xe0000000 0x1000>; bus-frequency = <0>; mcm-law@0 { compatible = "fsl,mcm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; mcm@1000 { compatible = "fsl,mpc8610-mcm", "fsl,mcm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; i2c@3000 { #address-cells = <1>; #size-cells = <0>; Loading arch/powerpc/boot/dts/mpc8641_hpcn.dts +13 −0 Original line number Diff line number Diff line Loading @@ -117,6 +117,19 @@ soc8641@ffe00000 { reg = <0xffe00000 0x00001000>; // CCSRBAR bus-frequency = <0>; mcm-law@0 { compatible = "fsl,mcm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; mcm@1000 { compatible = "fsl,mpc8641-mcm", "fsl,mcm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; i2c@3000 { #address-cells = <1>; #size-cells = <0>; Loading Loading
arch/powerpc/boot/dts/gef_ppc9a.dts +13 −0 Original line number Diff line number Diff line Loading @@ -167,6 +167,19 @@ soc@fef00000 { reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; mcm-law@0 { compatible = "fsl,mcm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; mcm@1000 { compatible = "fsl,mpc8641-mcm", "fsl,mcm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; Loading
arch/powerpc/boot/dts/gef_sbc310.dts +13 −0 Original line number Diff line number Diff line Loading @@ -166,6 +166,19 @@ soc@fef00000 { reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; mcm-law@0 { compatible = "fsl,mcm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; mcm@1000 { compatible = "fsl,mpc8641-mcm", "fsl,mcm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; Loading
arch/powerpc/boot/dts/gef_sbc610.dts +13 −0 Original line number Diff line number Diff line Loading @@ -131,6 +131,19 @@ soc@fef00000 { reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; mcm-law@0 { compatible = "fsl,mcm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; mcm@1000 { compatible = "fsl,mpc8641-mcm", "fsl,mcm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; Loading
arch/powerpc/boot/dts/mpc8610_hpcd.dts +13 −0 Original line number Diff line number Diff line Loading @@ -115,6 +115,19 @@ soc@e0000000 { reg = <0xe0000000 0x1000>; bus-frequency = <0>; mcm-law@0 { compatible = "fsl,mcm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; mcm@1000 { compatible = "fsl,mpc8610-mcm", "fsl,mcm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; i2c@3000 { #address-cells = <1>; #size-cells = <0>; Loading
arch/powerpc/boot/dts/mpc8641_hpcn.dts +13 −0 Original line number Diff line number Diff line Loading @@ -117,6 +117,19 @@ soc8641@ffe00000 { reg = <0xffe00000 0x00001000>; // CCSRBAR bus-frequency = <0>; mcm-law@0 { compatible = "fsl,mcm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; mcm@1000 { compatible = "fsl,mpc8641-mcm", "fsl,mcm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; i2c@3000 { #address-cells = <1>; #size-cells = <0>; Loading