Commit d8d6b902 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: mach-sdk7786: Add support for the FPGA SRAM. 



This ties in the 2KiB of FPGA SRAM in to the generic SRAM pool.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent c993487e

arch/sh/boards/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ config SH_SDK7786 
	select SYS_SUPPORTS_PCI

	select NO_IOPORT if !PCI

	select ARCH_WANT_OPTIONAL_GPIOLIB

	select HAVE_SRAM_POOL

	help

	  Select SDK7786 if configuring for a Renesas Technology Europe

	  SH7786-65nm board.

arch/sh/boards/mach-sdk7786/Makefile

+2 −1
Original line number Diff line number Diff line 
obj-y	:= setup.o fpga.o irq.o

obj-y	:= fpga.o irq.o setup.o



obj-$(CONFIG_GENERIC_GPIO)	+= gpio.o

obj-$(CONFIG_HAVE_SRAM_POOL)	+= sram.o

arch/sh/boards/mach-sdk7786/sram.c

0 → 100644
+72 −0
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/*

 * SDK7786 FPGA SRAM Support.

 *

 * Copyright (C) 2010  Paul Mundt

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt



#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/io.h>

#include <linux/string.h>

#include <mach/fpga.h>

#include <asm/sram.h>

#include <asm/sizes.h>



static int __init fpga_sram_init(void)

{

	unsigned long phys;

	unsigned int area;

	void __iomem *vaddr;

	int ret;

	u16 data;



	/* Enable FPGA SRAM */

	data = fpga_read_reg(LCLASR);

	data |= LCLASR_FRAMEN;

	fpga_write_reg(data, LCLASR);



	/*

	 * FPGA_SEL determines the area mapping

	 */

	area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT;

	if (unlikely(area == LCLASR_AREA_MASK)) {

		pr_err("FPGA memory unmapped.\n");

		return -ENXIO;

	}



	/*

	 * The memory itself occupies a 2KiB range at the top of the area

	 * immediately below the system registers.

	 */

	phys = (area << 26) + SZ_64M - SZ_4K;



	/*

	 * The FPGA SRAM resides in translatable physical space, so set

	 * up a mapping prior to inserting it in to the pool.

	 */

	vaddr = ioremap(phys, SZ_2K);

	if (unlikely(!vaddr)) {

		pr_err("Failed remapping FPGA memory.\n");

		return -ENXIO;

	}



	pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx "

		"(area %d) to pool.\n",

		SZ_2K >> 10, phys, phys + SZ_2K - 1, area);



	ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1);

	if (unlikely(ret < 0)) {

		pr_err("Failed adding memory\n");

		iounmap(vaddr);

		return ret;

	}



	return 0;

}

postcore_initcall(fpga_sram_init);

arch/sh/include/asm/sizes.h

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#define SZ_512				0x00000200



#define SZ_1K                           0x00000400

#define SZ_2K                           0x00000800

#define SZ_4K                           0x00001000

#define SZ_8K                           0x00002000

#define SZ_16K                          0x00004000

arch/sh/include/mach-sdk7786/mach/fpga.h

+16 −1
Original line number Diff line number Diff line
@@ -43,8 +43,23 @@ 


#define FAER		0x150

#define USRGPIR		0x160



/* 0x170 reserved */



#define LCLASR			0x180

#define  LCLASR_FRAMEN		BIT(15)



#define  LCLASR_FPGA_SEL_SHIFT	12

#define  LCLASR_NAND_SEL_SHIFT	8

#define  LCLASR_NORB_SEL_SHIFT	4

#define  LCLASR_NORA_SEL_SHIFT	0



#define  LCLASR_AREA_MASK	0x7



#define  LCLASR_FPGA_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT)

#define  LCLASR_NAND_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT)

#define  LCLASR_NORB_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT)

#define  LCLASR_NORA_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT)



#define SBCR		0x190

#define  SCBR_I2CMEN	BIT(0)	/* FPGA I2C master enable */