Loading arch/mips/mm/c-r4k.c +3 −4 Original line number Diff line number Diff line Loading @@ -464,8 +464,8 @@ static void r4k_flush_data_cache_page(unsigned long addr) } struct flush_icache_range_args { unsigned long __user start; unsigned long __user end; unsigned long start; unsigned long end; }; static inline void local_r4k_flush_icache_range(void *args) Loading Loading @@ -528,8 +528,7 @@ static inline void local_r4k_flush_icache_range(void *args) } } static void r4k_flush_icache_range(unsigned long __user start, unsigned long __user end) static void r4k_flush_icache_range(unsigned long start, unsigned long end) { struct flush_icache_range_args args; Loading arch/mips/mm/cache.c +2 −3 Original line number Diff line number Diff line Loading @@ -25,8 +25,7 @@ void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end); void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); void (*flush_icache_range)(unsigned long __user start, unsigned long __user end); void (*flush_icache_range)(unsigned long start, unsigned long end); void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); /* MIPS specific cache operations */ Loading @@ -53,7 +52,7 @@ EXPORT_SYMBOL(_dma_cache_inv); * We could optimize the case where the cache argument is not BCACHE but * that seems very atypical use ... */ asmlinkage int sys_cacheflush(unsigned long __user addr, asmlinkage int sys_cacheflush(unsigned long addr, unsigned long bytes, unsigned int cache) { if (bytes == 0) Loading include/asm-mips/cacheflush.h +1 −2 Original line number Diff line number Diff line Loading @@ -49,8 +49,7 @@ static inline void flush_dcache_page(struct page *page) extern void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); extern void (*flush_icache_range)(unsigned long __user start, unsigned long __user end); extern void (*flush_icache_range)(unsigned long start, unsigned long end); #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() Loading Loading
arch/mips/mm/c-r4k.c +3 −4 Original line number Diff line number Diff line Loading @@ -464,8 +464,8 @@ static void r4k_flush_data_cache_page(unsigned long addr) } struct flush_icache_range_args { unsigned long __user start; unsigned long __user end; unsigned long start; unsigned long end; }; static inline void local_r4k_flush_icache_range(void *args) Loading Loading @@ -528,8 +528,7 @@ static inline void local_r4k_flush_icache_range(void *args) } } static void r4k_flush_icache_range(unsigned long __user start, unsigned long __user end) static void r4k_flush_icache_range(unsigned long start, unsigned long end) { struct flush_icache_range_args args; Loading
arch/mips/mm/cache.c +2 −3 Original line number Diff line number Diff line Loading @@ -25,8 +25,7 @@ void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end); void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); void (*flush_icache_range)(unsigned long __user start, unsigned long __user end); void (*flush_icache_range)(unsigned long start, unsigned long end); void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); /* MIPS specific cache operations */ Loading @@ -53,7 +52,7 @@ EXPORT_SYMBOL(_dma_cache_inv); * We could optimize the case where the cache argument is not BCACHE but * that seems very atypical use ... */ asmlinkage int sys_cacheflush(unsigned long __user addr, asmlinkage int sys_cacheflush(unsigned long addr, unsigned long bytes, unsigned int cache) { if (bytes == 0) Loading
include/asm-mips/cacheflush.h +1 −2 Original line number Diff line number Diff line Loading @@ -49,8 +49,7 @@ static inline void flush_dcache_page(struct page *page) extern void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); extern void (*flush_icache_range)(unsigned long __user start, unsigned long __user end); extern void (*flush_icache_range)(unsigned long start, unsigned long end); #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() Loading