Commit d33e6fe3 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: FRE: Use set/clear_c0_config5 instead of open coded sequences. 



Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b0c34f61

arch/mips/include/asm/fpu.h

+3 −5
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ static inline int __enable_fpu(enum fpu_mode mode) 
			return SIGFPE;



		/* set FRE */

		write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE);

		set_c0_config5(MIPS_CONF5_FRE);

		goto fr_common;



	case FPU_64BIT:
@@ -76,7 +76,7 @@ static inline int __enable_fpu(enum fpu_mode mode) 
	case FPU_32BIT:

		if (cpu_has_fre) {

			/* clear FRE */

			write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);

			clear_c0_config5(MIPS_CONF5_FRE);

		}

fr_common:

		/* set CU1 & change FR appropriately */
@@ -196,15 +196,13 @@ static inline int init_fpu(void) 
			return 0;

		}



		config5 = read_c0_config5();



		/*

		 * Ensure FRE is clear whilst running _init_fpu, since

		 * single precision FP instructions are used. If FRE

		 * was set then we'll just end up initialising all 32

		 * 64b registers.

		 */

		write_c0_config5(config5 & ~MIPS_CONF5_FRE);

		config5 = clear_c0_config5(MIPS_CONF5_FRE);

		enable_fpu_hazard();



		_init_fpu();