Loading Documentation/cgroup-v2.txt +5 −1 Original line number Diff line number Diff line Loading @@ -7,7 +7,7 @@ This is the authoritative documentation on the design, interface and conventions of cgroup v2. It describes all userland-visible aspects of cgroup including core and specific controller behaviors. All future changes must be reflected in this document. Documentation for v1 is available under Documentation/cgroup-legacy/. v1 is available under Documentation/cgroup-v1/. CONTENTS Loading Loading @@ -843,6 +843,10 @@ PAGE_SIZE multiple when read back. Amount of memory used to cache filesystem data, including tmpfs and shared memory. sock Amount of memory used in network transmission buffers file_mapped Amount of cached filesystem data mapped with mmap() Loading Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt +1 −1 Original line number Diff line number Diff line Loading @@ -30,7 +30,7 @@ that they are defined using standard clock bindings with following clock-output-names: - "xin24m" - crystal input - required, - "ext_i2s" - external I2S clock - optional, - "ext_gmac" - external GMAC clock - optional - "rmii_clkin" - external EMAC clock - optional Example: Clock controller node: Loading Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +2 −3 Original line number Diff line number Diff line Loading @@ -24,9 +24,8 @@ Main node required properties: 1 = edge triggered 4 = level triggered Cells 4 and beyond are reserved for future use. When the 1st cell has a value of 0 or 1, cells 4 and beyond act as padding, and may be ignored. It is recommended that padding cells have a value of 0. Cells 4 and beyond are reserved for future use and must have a value of 0 if present. - reg : Specifies base physical address(s) and size of the GIC registers, in the following order: Loading Documentation/devicetree/bindings/net/brcm,bcmgenet.txt +2 −2 Original line number Diff line number Diff line Loading @@ -68,7 +68,7 @@ ethernet@f0b60000 { phy1: ethernet-phy@1 { max-speed = <1000>; reg = <0x1>; compatible = "brcm,28nm-gphy", "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22"; }; }; }; Loading Loading @@ -115,7 +115,7 @@ ethernet@f0ba0000 { phy0: ethernet-phy@0 { max-speed = <1000>; reg = <0x0>; compatible = "brcm,bcm53125", "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22"; }; }; }; Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt +1 −4 Original line number Diff line number Diff line Loading @@ -4,8 +4,6 @@ Required properties: - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2". "hisilicon,hns-dsaf-v1" is for hip05. "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612. - dsa-name: dsa fabric name who provide this interface. should be "dsafX", X is the dsaf id. - mode: dsa fabric mode string. only support one of dsaf modes like these: "2port-64vf", "6port-16rss", Loading @@ -26,9 +24,8 @@ Required properties: Example: dsa: dsa@c7000000 { dsaf0: dsa@c7000000 { compatible = "hisilicon,hns-dsaf-v1"; dsa_name = "dsaf0"; mode = "6port-16rss"; interrupt-parent = <&mbigen_dsa>; reg = <0x0 0xC0000000 0x0 0x420000 Loading Loading
Documentation/cgroup-v2.txt +5 −1 Original line number Diff line number Diff line Loading @@ -7,7 +7,7 @@ This is the authoritative documentation on the design, interface and conventions of cgroup v2. It describes all userland-visible aspects of cgroup including core and specific controller behaviors. All future changes must be reflected in this document. Documentation for v1 is available under Documentation/cgroup-legacy/. v1 is available under Documentation/cgroup-v1/. CONTENTS Loading Loading @@ -843,6 +843,10 @@ PAGE_SIZE multiple when read back. Amount of memory used to cache filesystem data, including tmpfs and shared memory. sock Amount of memory used in network transmission buffers file_mapped Amount of cached filesystem data mapped with mmap() Loading
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt +1 −1 Original line number Diff line number Diff line Loading @@ -30,7 +30,7 @@ that they are defined using standard clock bindings with following clock-output-names: - "xin24m" - crystal input - required, - "ext_i2s" - external I2S clock - optional, - "ext_gmac" - external GMAC clock - optional - "rmii_clkin" - external EMAC clock - optional Example: Clock controller node: Loading
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +2 −3 Original line number Diff line number Diff line Loading @@ -24,9 +24,8 @@ Main node required properties: 1 = edge triggered 4 = level triggered Cells 4 and beyond are reserved for future use. When the 1st cell has a value of 0 or 1, cells 4 and beyond act as padding, and may be ignored. It is recommended that padding cells have a value of 0. Cells 4 and beyond are reserved for future use and must have a value of 0 if present. - reg : Specifies base physical address(s) and size of the GIC registers, in the following order: Loading
Documentation/devicetree/bindings/net/brcm,bcmgenet.txt +2 −2 Original line number Diff line number Diff line Loading @@ -68,7 +68,7 @@ ethernet@f0b60000 { phy1: ethernet-phy@1 { max-speed = <1000>; reg = <0x1>; compatible = "brcm,28nm-gphy", "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22"; }; }; }; Loading Loading @@ -115,7 +115,7 @@ ethernet@f0ba0000 { phy0: ethernet-phy@0 { max-speed = <1000>; reg = <0x0>; compatible = "brcm,bcm53125", "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22"; }; }; };
Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt +1 −4 Original line number Diff line number Diff line Loading @@ -4,8 +4,6 @@ Required properties: - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2". "hisilicon,hns-dsaf-v1" is for hip05. "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612. - dsa-name: dsa fabric name who provide this interface. should be "dsafX", X is the dsaf id. - mode: dsa fabric mode string. only support one of dsaf modes like these: "2port-64vf", "6port-16rss", Loading @@ -26,9 +24,8 @@ Required properties: Example: dsa: dsa@c7000000 { dsaf0: dsa@c7000000 { compatible = "hisilicon,hns-dsaf-v1"; dsa_name = "dsaf0"; mode = "6port-16rss"; interrupt-parent = <&mbigen_dsa>; reg = <0x0 0xC0000000 0x0 0x420000 Loading