Commit b6080e12 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

tg3: Add coalesce parameters for msix vectors 



This patch adds code to tune the coalescing parameters for the other
msix vectors.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Reviewed-by: default avatarBenjamin Li <benli@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent fed97810

drivers/net/tg3.c

+48 −9
Original line number Original line Diff line number Diff line
@@ -6876,24 +6876,63 @@ static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, 
static void __tg3_set_rx_mode(struct net_device *);

static void __tg3_set_rx_mode(struct net_device *);

static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)

static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)

{

{

	tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);

	int i;



	if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {

		tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);

		tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);

	tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);

		tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);

		tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);

	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {

		tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);

		tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);

	}

	tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);

		tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);

		tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);



		tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);

		tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);

		tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);

	} else {

		tw32(HOSTCC_TXCOL_TICKS, 0);

		tw32(HOSTCC_TXMAX_FRAMES, 0);

		tw32(HOSTCC_TXCOAL_MAXF_INT, 0);



		tw32(HOSTCC_RXCOL_TICKS, 0);

		tw32(HOSTCC_RXMAX_FRAMES, 0);

		tw32(HOSTCC_RXCOAL_MAXF_INT, 0);

	}



	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {

	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {

		u32 val = ec->stats_block_coalesce_usecs;

		u32 val = ec->stats_block_coalesce_usecs;





		tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);

		tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);



		if (!netif_carrier_ok(tp->dev))

		if (!netif_carrier_ok(tp->dev))

			val = 0;

			val = 0;





		tw32(HOSTCC_STAT_COAL_TICKS, val);

		tw32(HOSTCC_STAT_COAL_TICKS, val);

	}

	}



	for (i = 0; i < tp->irq_cnt - 1; i++) {

		u32 reg;



		reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;

		tw32(reg, ec->rx_coalesce_usecs);

		reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;

		tw32(reg, ec->tx_coalesce_usecs);

		reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;

		tw32(reg, ec->rx_max_coalesced_frames);

		reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;

		tw32(reg, ec->tx_max_coalesced_frames);

		reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;

		tw32(reg, ec->rx_max_coalesced_frames_irq);

		reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;

		tw32(reg, ec->tx_max_coalesced_frames_irq);

	}



	for (; i < tp->irq_max - 1; i++) {

		tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);

		tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);

		tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);

		tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);

		tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);

		tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);

	}

}

}





/* tp->lock is held. */

/* tp->lock is held. */

drivers/net/tg3.h

+9 −1
Original line number Original line Diff line number Diff line
@@ -1119,7 +1119,15 @@ 
#define HOSTCC_SND_CON_IDX_14		0x00003cf8

#define HOSTCC_SND_CON_IDX_14		0x00003cf8

#define HOSTCC_SND_CON_IDX_15		0x00003cfc

#define HOSTCC_SND_CON_IDX_15		0x00003cfc

#define HOSTCC_STATBLCK_RING1		0x00003d00

#define HOSTCC_STATBLCK_RING1		0x00003d00

/* 0x3d04 --> 0x4000 unused */

/* 0x3d00 --> 0x3d80 unused */



#define HOSTCC_RXCOL_TICKS_VEC1		0x00003d80

#define HOSTCC_TXCOL_TICKS_VEC1		0x00003d84

#define HOSTCC_RXMAX_FRAMES_VEC1	0x00003d88

#define HOSTCC_TXMAX_FRAMES_VEC1	0x00003d8c

#define HOSTCC_RXCOAL_MAXF_INT_VEC1	0x00003d90

#define HOSTCC_TXCOAL_MAXF_INT_VEC1	0x00003d94

/* 0x3d98 --> 0x4000 unused */





/* Memory arbiter control registers */

/* Memory arbiter control registers */

#define MEMARB_MODE			0x00004000

#define MEMARB_MODE			0x00004000