Loading drivers/gpu/drm/nouveau/core/engine/device/nve0.c +0 −2 Original line number Diff line number Diff line Loading @@ -164,10 +164,8 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; #if 0 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; #endif device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; Loading drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c +48 −2 Original line number Diff line number Diff line Loading @@ -24,6 +24,15 @@ #include "nvc0.h" /******************************************************************************* * Graphics object classes ******************************************************************************/ static struct nouveau_oclass nvf0_graph_sclass[] = { {} }; /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ Loading Loading @@ -142,6 +151,43 @@ nvf0_graph_init_tpc[] = { {} }; static int nvf0_graph_fini(struct nouveau_object *object, bool suspend) { struct nvc0_graph_priv *priv = (void *)object; static const struct { u32 addr; u32 data; } magic[] = { { 0x020520, 0xfffffffc }, { 0x020524, 0xfffffffe }, { 0x020524, 0xfffffffc }, { 0x020524, 0xfffffff8 }, { 0x020524, 0xffffffe0 }, { 0x020530, 0xfffffffe }, { 0x02052c, 0xfffffffa }, { 0x02052c, 0xfffffff0 }, { 0x02052c, 0xffffffc0 }, { 0x02052c, 0xffffff00 }, { 0x02052c, 0xfffffc00 }, { 0x02052c, 0xfffcfc00 }, { 0x02052c, 0xfff0fc00 }, { 0x02052c, 0xff80fc00 }, { 0x020528, 0xfffffffe }, { 0x020528, 0xfffffffc }, }; int i; nv_mask(priv, 0x000200, 0x08001000, 0x00000000); nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000); for (i = 0; i < ARRAY_SIZE(magic); i++) { nv_wr32(priv, magic[i].addr, magic[i].data); nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); } return nouveau_graph_fini(&priv->base, suspend); } static struct nvc0_graph_init * nvf0_graph_init_mmio[] = { nve4_graph_init_regs, Loading @@ -168,9 +214,9 @@ nvf0_graph_oclass = &(struct nvc0_graph_oclass) { .ctor = nvc0_graph_ctor, .dtor = nvc0_graph_dtor, .init = nve4_graph_init, .fini = _nouveau_graph_fini, .fini = nvf0_graph_fini, }, .cclass = &nvf0_grctx_oclass, .sclass = NULL, .sclass = nvf0_graph_sclass, .mmio = nvf0_graph_init_mmio, }.base; Loading
drivers/gpu/drm/nouveau/core/engine/device/nve0.c +0 −2 Original line number Diff line number Diff line Loading @@ -164,10 +164,8 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; #if 0 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; #endif device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; Loading
drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c +48 −2 Original line number Diff line number Diff line Loading @@ -24,6 +24,15 @@ #include "nvc0.h" /******************************************************************************* * Graphics object classes ******************************************************************************/ static struct nouveau_oclass nvf0_graph_sclass[] = { {} }; /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ Loading Loading @@ -142,6 +151,43 @@ nvf0_graph_init_tpc[] = { {} }; static int nvf0_graph_fini(struct nouveau_object *object, bool suspend) { struct nvc0_graph_priv *priv = (void *)object; static const struct { u32 addr; u32 data; } magic[] = { { 0x020520, 0xfffffffc }, { 0x020524, 0xfffffffe }, { 0x020524, 0xfffffffc }, { 0x020524, 0xfffffff8 }, { 0x020524, 0xffffffe0 }, { 0x020530, 0xfffffffe }, { 0x02052c, 0xfffffffa }, { 0x02052c, 0xfffffff0 }, { 0x02052c, 0xffffffc0 }, { 0x02052c, 0xffffff00 }, { 0x02052c, 0xfffffc00 }, { 0x02052c, 0xfffcfc00 }, { 0x02052c, 0xfff0fc00 }, { 0x02052c, 0xff80fc00 }, { 0x020528, 0xfffffffe }, { 0x020528, 0xfffffffc }, }; int i; nv_mask(priv, 0x000200, 0x08001000, 0x00000000); nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000); for (i = 0; i < ARRAY_SIZE(magic); i++) { nv_wr32(priv, magic[i].addr, magic[i].data); nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); } return nouveau_graph_fini(&priv->base, suspend); } static struct nvc0_graph_init * nvf0_graph_init_mmio[] = { nve4_graph_init_regs, Loading @@ -168,9 +214,9 @@ nvf0_graph_oclass = &(struct nvc0_graph_oclass) { .ctor = nvc0_graph_ctor, .dtor = nvc0_graph_dtor, .init = nve4_graph_init, .fini = _nouveau_graph_fini, .fini = nvf0_graph_fini, }, .cclass = &nvf0_grctx_oclass, .sclass = NULL, .sclass = nvf0_graph_sclass, .mmio = nvf0_graph_init_mmio, }.base;