Loading drivers/gpu/drm/i915/i915_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -1915,6 +1915,7 @@ #define DISPPLANE_16BPP (0x5<<26) #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) #define DISPPLANE_32BPP (0x7<<26) #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) #define DISPPLANE_STEREO_ENABLE (1<<25) #define DISPPLANE_STEREO_DISABLE 0 #define DISPPLANE_SEL_PIPE_MASK (1<<24) Loading drivers/gpu/drm/i915/intel_display.c +4 −1 Original line number Diff line number Diff line Loading @@ -1289,6 +1289,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, break; case 24: case 32: if (crtc->fb->depth == 30) dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; else dspcntr |= DISPPLANE_32BPP_NO_ALPHA; break; default: Loading Loading
drivers/gpu/drm/i915/i915_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -1915,6 +1915,7 @@ #define DISPPLANE_16BPP (0x5<<26) #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) #define DISPPLANE_32BPP (0x7<<26) #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) #define DISPPLANE_STEREO_ENABLE (1<<25) #define DISPPLANE_STEREO_DISABLE 0 #define DISPPLANE_SEL_PIPE_MASK (1<<24) Loading
drivers/gpu/drm/i915/intel_display.c +4 −1 Original line number Diff line number Diff line Loading @@ -1289,6 +1289,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, break; case 24: case 32: if (crtc->fb->depth == 30) dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; else dspcntr |= DISPPLANE_32BPP_NO_ALPHA; break; default: Loading