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Commit a168b8f1 authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Markos Chandras
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MIPS: mm: Add MIPS R6 instruction encodings 



MIPS R6 defines new opcodes for ll, sc, cache and pref instructions
so we need to take these into consideration in the micro-assembler.

Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent 51eec48e
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