Loading arch/mips/include/asm/spram.h 0 → 100644 +10 −0 Original line number Diff line number Diff line #ifndef _MIPS_SPRAM_H #define _MIPS_SPRAM_H #ifdef CONFIG_CPU_MIPSR2 extern __init void spram_config(void); #else static inline void spram_config(void) { }; #endif /* CONFIG_CPU_MIPSR2 */ #endif /* _MIPS_SPRAM_H */ arch/mips/kernel/cpu-probe.c +1 −7 Original line number Diff line number Diff line Loading @@ -23,7 +23,7 @@ #include <asm/mipsregs.h> #include <asm/system.h> #include <asm/watch.h> #include <asm/spram.h> /* * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, * the implementation of the "wait" feature differs between CPU families. This Loading Loading @@ -711,12 +711,6 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); } #ifdef CONFIG_CPU_MIPSR2 extern void spram_config(void); #else static inline void spram_config(void) {} #endif static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); Loading arch/mips/kernel/spram.c +1 −3 Original line number Diff line number Diff line Loading @@ -13,7 +13,6 @@ #include <linux/ptrace.h> #include <linux/stddef.h> #include <asm/cpu.h> #include <asm/fpu.h> #include <asm/mipsregs.h> #include <asm/system.h> Loading Loading @@ -198,8 +197,7 @@ static __cpuinit void probe_spram(char *type, offset += 2 * SPRAM_TAG_STRIDE; } } __cpuinit void spram_config(void) void __cpuinit spram_config(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config0; Loading Loading
arch/mips/include/asm/spram.h 0 → 100644 +10 −0 Original line number Diff line number Diff line #ifndef _MIPS_SPRAM_H #define _MIPS_SPRAM_H #ifdef CONFIG_CPU_MIPSR2 extern __init void spram_config(void); #else static inline void spram_config(void) { }; #endif /* CONFIG_CPU_MIPSR2 */ #endif /* _MIPS_SPRAM_H */
arch/mips/kernel/cpu-probe.c +1 −7 Original line number Diff line number Diff line Loading @@ -23,7 +23,7 @@ #include <asm/mipsregs.h> #include <asm/system.h> #include <asm/watch.h> #include <asm/spram.h> /* * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, * the implementation of the "wait" feature differs between CPU families. This Loading Loading @@ -711,12 +711,6 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); } #ifdef CONFIG_CPU_MIPSR2 extern void spram_config(void); #else static inline void spram_config(void) {} #endif static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); Loading
arch/mips/kernel/spram.c +1 −3 Original line number Diff line number Diff line Loading @@ -13,7 +13,6 @@ #include <linux/ptrace.h> #include <linux/stddef.h> #include <asm/cpu.h> #include <asm/fpu.h> #include <asm/mipsregs.h> #include <asm/system.h> Loading Loading @@ -198,8 +197,7 @@ static __cpuinit void probe_spram(char *type, offset += 2 * SPRAM_TAG_STRIDE; } } __cpuinit void spram_config(void) void __cpuinit spram_config(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config0; Loading