Commit 9cd9669b authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Use board_cache_error_setup for r4k cache error handler setup. 



Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3821/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 586016eb

arch/mips/mm/c-r4k.c

+10 −4
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
#include <asm/mmu_context.h>

#include <asm/war.h>

#include <asm/cacheflush.h> /* for run_uncached() */



#include <asm/traps.h>



/*

 * Special Variant of smp_call_function for use by cache functions:
@@ -1385,10 +1385,8 @@ static int __init setcoherentio(char *str) 
__setup("coherentio", setcoherentio);

#endif



void __cpuinit r4k_cache_init(void)

static void __cpuinit r4k_cache_error_setup(void)

{

	extern void build_clear_page(void);

	extern void build_copy_page(void);

	extern char __weak except_vec2_generic;

	extern char __weak except_vec2_sb1;

	struct cpuinfo_mips *c = &current_cpu_data;
@@ -1403,6 +1401,13 @@ void __cpuinit r4k_cache_init(void) 
		set_uncached_handler(0x100, &except_vec2_generic, 0x80);

		break;

	}

}



void __cpuinit r4k_cache_init(void)

{

	extern void build_clear_page(void);

	extern void build_copy_page(void);

	struct cpuinfo_mips *c = &current_cpu_data;



	probe_pcache();

	setup_scache();
@@ -1465,4 +1470,5 @@ void __cpuinit r4k_cache_init(void) 
	local_r4k___flush_cache_all(NULL);

#endif

	coherency_setup();

	board_cache_error_setup = r4k_cache_error_setup;

}