Loading drivers/gpu/drm/i915/i915_irq.c +14 −15 Original line number Diff line number Diff line Loading @@ -1787,11 +1787,12 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) u32 master_ctl, iir; irqreturn_t ret = IRQ_NONE; master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL; for (;;) { master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; iir = I915_READ(VLV_IIR); if (master_ctl == 0 && iir == 0) return IRQ_NONE; break; I915_WRITE(GEN8_MASTER_IRQ, 0); Loading @@ -1800,10 +1801,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) valleyview_pipestat_irq_handler(dev, iir); /* Consume port. Then clear IIR or we'll miss events */ if (iir & I915_DISPLAY_PORT_INTERRUPT) { i9xx_hpd_irq_handler(dev); ret = IRQ_HANDLED; } I915_WRITE(VLV_IIR, iir); Loading @@ -1811,6 +1809,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) POSTING_READ(GEN8_MASTER_IRQ); ret = IRQ_HANDLED; } return ret; } Loading Loading
drivers/gpu/drm/i915/i915_irq.c +14 −15 Original line number Diff line number Diff line Loading @@ -1787,11 +1787,12 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) u32 master_ctl, iir; irqreturn_t ret = IRQ_NONE; master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL; for (;;) { master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; iir = I915_READ(VLV_IIR); if (master_ctl == 0 && iir == 0) return IRQ_NONE; break; I915_WRITE(GEN8_MASTER_IRQ, 0); Loading @@ -1800,10 +1801,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) valleyview_pipestat_irq_handler(dev, iir); /* Consume port. Then clear IIR or we'll miss events */ if (iir & I915_DISPLAY_PORT_INTERRUPT) { i9xx_hpd_irq_handler(dev); ret = IRQ_HANDLED; } I915_WRITE(VLV_IIR, iir); Loading @@ -1811,6 +1809,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) POSTING_READ(GEN8_MASTER_IRQ); ret = IRQ_HANDLED; } return ret; } Loading