Loading drivers/clk/hisilicon/clk.c +28 −0 Original line number Diff line number Diff line Loading @@ -177,6 +177,34 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, } } void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { struct clk *clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { clk = clk_register_gate(NULL, clks[i].name, clks[i].parent_name, clks[i].flags, base + clks[i].offset, clks[i].bit_idx, clks[i].gate_flags, &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } if (clks[i].alias) clk_register_clkdev(clk, clks[i].alias, NULL); data->clk_data.clks[clks[i].id] = clk; } } void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { Loading drivers/clk/hisilicon/clk.h +2 −0 Original line number Diff line number Diff line Loading @@ -104,6 +104,8 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *, int, struct hisi_clock_data *); void __init hisi_clk_register_divider(struct hisi_divider_clock *, int, struct hisi_clock_data *); void __init hisi_clk_register_gate(struct hisi_gate_clock *, int, struct hisi_clock_data *); void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, int, struct hisi_clock_data *); #endif /* __HISI_CLK_H */ Loading
drivers/clk/hisilicon/clk.c +28 −0 Original line number Diff line number Diff line Loading @@ -177,6 +177,34 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, } } void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { struct clk *clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { clk = clk_register_gate(NULL, clks[i].name, clks[i].parent_name, clks[i].flags, base + clks[i].offset, clks[i].bit_idx, clks[i].gate_flags, &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } if (clks[i].alias) clk_register_clkdev(clk, clks[i].alias, NULL); data->clk_data.clks[clks[i].id] = clk; } } void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { Loading
drivers/clk/hisilicon/clk.h +2 −0 Original line number Diff line number Diff line Loading @@ -104,6 +104,8 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *, int, struct hisi_clock_data *); void __init hisi_clk_register_divider(struct hisi_divider_clock *, int, struct hisi_clock_data *); void __init hisi_clk_register_gate(struct hisi_gate_clock *, int, struct hisi_clock_data *); void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, int, struct hisi_clock_data *); #endif /* __HISI_CLK_H */