Loading Documentation/devicetree/bindings/arm/calxeda.txt 0 → 100644 +8 −0 Original line number Diff line number Diff line Calxeda Highbank Platforms Device Tree Bindings ----------------------------------------------- Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following properties. Required root node properties: - compatible = "calxeda,highbank"; Documentation/devicetree/bindings/arm/l2cc.txt 0 → 100644 +44 −0 Original line number Diff line number Diff line * ARM L2 Cache Controller ARM cores often have a separate level 2 cache controller. There are various implementations of the L2 cache controller with compatible programming models. The ARM L2 cache representation in the device tree should be done as follows: Required properties: - compatible : should be one of: "arm,pl310-cache" "arm,l220-cache" "arm,l210-cache" - cache-unified : Specifies the cache is a unified cache. - cache-level : Should be set to 2 for a level 2 cache. - reg : Physical base address and size of cache controller's memory mapped registers. Optional properties: - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of read, write and setup latencies. Minimum valid values are 1. Controllers without setup latency control should use a value of 0. - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of read, write and setup latencies. Controllers without setup latency control should use 0. Controllers without separate read and write Tag RAM latency values should only use the first cell. - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. - arm,filter-ranges : <start length> Starting address and length of window to filter. Addresses in the filter window are directed to the M1 port. Other addresses will go to the M0 port. - interrupts : 1 combined interrupt. Example: L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xfff12000 0x1000>; arm,data-latency = <1 1 1>; arm,tag-latency = <2 2 2>; arm,filter-latency = <0x80000000 0x8000000>; cache-unified; cache-level = <2>; interrupts = <45>; }; MAINTAINERS +6 −0 Original line number Diff line number Diff line Loading @@ -688,6 +688,12 @@ F: drivers/mtd/nand/bcm_umi_nand.c F: drivers/mtd/nand/bcm_umi_bch.c F: drivers/mtd/nand/nand_bcm_umi.h ARM/CALXEDA HIGHBANK ARCHITECTURE M: Rob Herring <rob.herring@calxeda.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-highbank/ ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT M: Anton Vorontsov <avorontsov@mvista.com> S: Maintained Loading arch/arm/Kconfig +16 −1 Original line number Diff line number Diff line Loading @@ -330,6 +330,20 @@ config ARCH_BCMRING help Support for Broadcom's BCMRing platform. config ARCH_HIGHBANK bool "Calxeda Highbank-based" select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 select CLKDEV_LOOKUP select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU select USE_OF help Support for the Calxeda Highbank SoC based boards. config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x-based" select CPU_ARM720T Loading Loading @@ -862,6 +876,7 @@ config ARCH_U300 select CLKDEV_LOOKUP select HAVE_MACH_CLKDEV select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB select NEED_MACH_MEMORY_H help Support for ST-Ericsson U300 series mobile platforms. Loading Loading @@ -1402,7 +1417,7 @@ config SMP depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK select USE_GENERIC_SMP_HELPERS select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP help Loading arch/arm/Kconfig.debug +66 −30 Original line number Diff line number Diff line Loading @@ -65,57 +65,93 @@ config DEBUG_USER # These options are only for real kernel hackers who want to get their hands dirty. config DEBUG_LL bool "Kernel low-level debugging functions" bool "Kernel low-level debugging functions (read help!)" depends on DEBUG_KERNEL help Say Y here to include definitions of printascii, printch, printhex in the kernel. This is helpful if you are debugging code that executes before the console is initialized. config EARLY_PRINTK bool "Early printk" Note that selecting this option will limit the kernel to a single UART definition, as specified below. Attempting to boot the kernel image on a different platform *will not work*, so this option should not be enabled for kernels that are intended to be portable. choice prompt "Kernel low-level debugging port" depends on DEBUG_LL config DEBUG_LL_UART_NONE bool "No low-level debugging UART" help Say Y here if you want to have an early console using the kernel low-level debugging functions. Add earlyprintk to your kernel parameters to enable this console. Say Y here if your platform doesn't provide a UART option below. This relies on your platform choosing the right UART definition internally in order for low-level debugging to work. config DEBUG_ICEDCC bool "Kernel low-level debugging via EmbeddedICE DCC channel" depends on DEBUG_LL help Say Y here if you want the debug print routines to direct their output to the EmbeddedICE macrocell's DCC channel using Say Y here if you want the debug print routines to direct their output to the EmbeddedICE macrocell's DCC channel using co-processor 14. This is known to work on the ARM9 style ICE channel and on the XScale with the PEEDI. It does include a timeout to ensure that the system does not totally freeze when there is nothing connected to read. Note that the system will appear to hang during boot if there is nothing connected to read from the DCC. config OC_ETM bool "On-chip ETM and ETB" select ARM_AMBA config DEBUG_FOOTBRIDGE_COM1 bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1" depends on FOOTBRIDGE help Enables the on-chip embedded trace macrocell and embedded trace buffer driver that will allow you to collect traces of the kernel code. Say Y here if you want the debug print routines to direct their output to the 8250 at PCI COM1. config DEBUG_DC21285_PORT bool "Kernel low-level debugging messages via footbridge serial port" depends on DEBUG_LL && FOOTBRIDGE depends on FOOTBRIDGE help Say Y here if you want the debug print routines to direct their output to the serial port in the DC21285 (Footbridge). Saying N will cause the debug messages to appear on the first 16550 serial port. Say Y here if you want the debug print routines to direct their output to the serial port in the DC21285 (Footbridge). config DEBUG_CLPS711X_UART1 bool "Kernel low-level debugging messages via UART1" depends on ARCH_CLPS711X help Say Y here if you want the debug print routines to direct their output to the first serial port on these devices. config DEBUG_CLPS711X_UART2 bool "Kernel low-level debugging messages via UART2" depends on DEBUG_LL && ARCH_CLPS711X depends on ARCH_CLPS711X help Say Y here if you want the debug print routines to direct their output to the second serial port on these devices. config DEBUG_HIGHBANK_UART bool "Kernel low-level debugging messages via Highbank UART" depends on ARCH_HIGHBANK help Say Y here if you want the debug print routines to direct their output to the second serial port on these devices. Saying N will cause the debug messages to appear on the first serial port. Say Y here if you want the debug print routines to direct their output to the UART on Highbank based devices. endchoice config EARLY_PRINTK bool "Early printk" depends on DEBUG_LL help Say Y here if you want to have an early console using the kernel low-level debugging functions. Add earlyprintk to your kernel parameters to enable this console. config OC_ETM bool "On-chip ETM and ETB" select ARM_AMBA help Enables the on-chip embedded trace macrocell and embedded trace buffer driver that will allow you to collect traces of the kernel code. config DEBUG_S3C_UART depends on PLAT_SAMSUNG Loading Loading
Documentation/devicetree/bindings/arm/calxeda.txt 0 → 100644 +8 −0 Original line number Diff line number Diff line Calxeda Highbank Platforms Device Tree Bindings ----------------------------------------------- Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following properties. Required root node properties: - compatible = "calxeda,highbank";
Documentation/devicetree/bindings/arm/l2cc.txt 0 → 100644 +44 −0 Original line number Diff line number Diff line * ARM L2 Cache Controller ARM cores often have a separate level 2 cache controller. There are various implementations of the L2 cache controller with compatible programming models. The ARM L2 cache representation in the device tree should be done as follows: Required properties: - compatible : should be one of: "arm,pl310-cache" "arm,l220-cache" "arm,l210-cache" - cache-unified : Specifies the cache is a unified cache. - cache-level : Should be set to 2 for a level 2 cache. - reg : Physical base address and size of cache controller's memory mapped registers. Optional properties: - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of read, write and setup latencies. Minimum valid values are 1. Controllers without setup latency control should use a value of 0. - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of read, write and setup latencies. Controllers without setup latency control should use 0. Controllers without separate read and write Tag RAM latency values should only use the first cell. - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. - arm,filter-ranges : <start length> Starting address and length of window to filter. Addresses in the filter window are directed to the M1 port. Other addresses will go to the M0 port. - interrupts : 1 combined interrupt. Example: L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xfff12000 0x1000>; arm,data-latency = <1 1 1>; arm,tag-latency = <2 2 2>; arm,filter-latency = <0x80000000 0x8000000>; cache-unified; cache-level = <2>; interrupts = <45>; };
MAINTAINERS +6 −0 Original line number Diff line number Diff line Loading @@ -688,6 +688,12 @@ F: drivers/mtd/nand/bcm_umi_nand.c F: drivers/mtd/nand/bcm_umi_bch.c F: drivers/mtd/nand/nand_bcm_umi.h ARM/CALXEDA HIGHBANK ARCHITECTURE M: Rob Herring <rob.herring@calxeda.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-highbank/ ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT M: Anton Vorontsov <avorontsov@mvista.com> S: Maintained Loading
arch/arm/Kconfig +16 −1 Original line number Diff line number Diff line Loading @@ -330,6 +330,20 @@ config ARCH_BCMRING help Support for Broadcom's BCMRing platform. config ARCH_HIGHBANK bool "Calxeda Highbank-based" select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 select CLKDEV_LOOKUP select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU select USE_OF help Support for the Calxeda Highbank SoC based boards. config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x-based" select CPU_ARM720T Loading Loading @@ -862,6 +876,7 @@ config ARCH_U300 select CLKDEV_LOOKUP select HAVE_MACH_CLKDEV select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB select NEED_MACH_MEMORY_H help Support for ST-Ericsson U300 series mobile platforms. Loading Loading @@ -1402,7 +1417,7 @@ config SMP depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK select USE_GENERIC_SMP_HELPERS select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP help Loading
arch/arm/Kconfig.debug +66 −30 Original line number Diff line number Diff line Loading @@ -65,57 +65,93 @@ config DEBUG_USER # These options are only for real kernel hackers who want to get their hands dirty. config DEBUG_LL bool "Kernel low-level debugging functions" bool "Kernel low-level debugging functions (read help!)" depends on DEBUG_KERNEL help Say Y here to include definitions of printascii, printch, printhex in the kernel. This is helpful if you are debugging code that executes before the console is initialized. config EARLY_PRINTK bool "Early printk" Note that selecting this option will limit the kernel to a single UART definition, as specified below. Attempting to boot the kernel image on a different platform *will not work*, so this option should not be enabled for kernels that are intended to be portable. choice prompt "Kernel low-level debugging port" depends on DEBUG_LL config DEBUG_LL_UART_NONE bool "No low-level debugging UART" help Say Y here if you want to have an early console using the kernel low-level debugging functions. Add earlyprintk to your kernel parameters to enable this console. Say Y here if your platform doesn't provide a UART option below. This relies on your platform choosing the right UART definition internally in order for low-level debugging to work. config DEBUG_ICEDCC bool "Kernel low-level debugging via EmbeddedICE DCC channel" depends on DEBUG_LL help Say Y here if you want the debug print routines to direct their output to the EmbeddedICE macrocell's DCC channel using Say Y here if you want the debug print routines to direct their output to the EmbeddedICE macrocell's DCC channel using co-processor 14. This is known to work on the ARM9 style ICE channel and on the XScale with the PEEDI. It does include a timeout to ensure that the system does not totally freeze when there is nothing connected to read. Note that the system will appear to hang during boot if there is nothing connected to read from the DCC. config OC_ETM bool "On-chip ETM and ETB" select ARM_AMBA config DEBUG_FOOTBRIDGE_COM1 bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1" depends on FOOTBRIDGE help Enables the on-chip embedded trace macrocell and embedded trace buffer driver that will allow you to collect traces of the kernel code. Say Y here if you want the debug print routines to direct their output to the 8250 at PCI COM1. config DEBUG_DC21285_PORT bool "Kernel low-level debugging messages via footbridge serial port" depends on DEBUG_LL && FOOTBRIDGE depends on FOOTBRIDGE help Say Y here if you want the debug print routines to direct their output to the serial port in the DC21285 (Footbridge). Saying N will cause the debug messages to appear on the first 16550 serial port. Say Y here if you want the debug print routines to direct their output to the serial port in the DC21285 (Footbridge). config DEBUG_CLPS711X_UART1 bool "Kernel low-level debugging messages via UART1" depends on ARCH_CLPS711X help Say Y here if you want the debug print routines to direct their output to the first serial port on these devices. config DEBUG_CLPS711X_UART2 bool "Kernel low-level debugging messages via UART2" depends on DEBUG_LL && ARCH_CLPS711X depends on ARCH_CLPS711X help Say Y here if you want the debug print routines to direct their output to the second serial port on these devices. config DEBUG_HIGHBANK_UART bool "Kernel low-level debugging messages via Highbank UART" depends on ARCH_HIGHBANK help Say Y here if you want the debug print routines to direct their output to the second serial port on these devices. Saying N will cause the debug messages to appear on the first serial port. Say Y here if you want the debug print routines to direct their output to the UART on Highbank based devices. endchoice config EARLY_PRINTK bool "Early printk" depends on DEBUG_LL help Say Y here if you want to have an early console using the kernel low-level debugging functions. Add earlyprintk to your kernel parameters to enable this console. config OC_ETM bool "On-chip ETM and ETB" select ARM_AMBA help Enables the on-chip embedded trace macrocell and embedded trace buffer driver that will allow you to collect traces of the kernel code. config DEBUG_S3C_UART depends on PLAT_SAMSUNG Loading