Commit 85a4d2d4 authored by Len Brown's avatar Len Brown
Browse files

intel_idle: support Haswell 



This patch enables intel_idle to run on the
next-generation Intel(R) Microarchitecture code named "Haswell".

Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent b1beab48

drivers/idle/intel_idle.c

+39 −0
Original line number Diff line number Diff line
@@ -212,6 +212,38 @@ static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = { 
		.enter = &intel_idle },

};



static struct cpuidle_state hsw_cstates[MWAIT_MAX_NUM_CSTATES] = {

	{ /* MWAIT C0 */ },

	{ /* MWAIT C1 */

		.name = "C1-HSW",

		.desc = "MWAIT 0x00",

		.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,

		.exit_latency = 2,

		.target_residency = 2,

		.enter = &intel_idle },

	{ /* MWAIT C2 */

		.name = "C3-HSW",

		.desc = "MWAIT 0x10",

		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 33,

		.target_residency = 100,

		.enter = &intel_idle },

	{ /* MWAIT C3 */

		.name = "C6-HSW",

		.desc = "MWAIT 0x20",

		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 133,

		.target_residency = 400,

		.enter = &intel_idle },

	{ /* MWAIT C4 */

		.name = "C7s-HSW",

		.desc = "MWAIT 0x32",

		.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 166,

		.target_residency = 500,

		.enter = &intel_idle },

};



static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {

	{ /* MWAIT C0 */ },

	{ /* MWAIT C1 */
@@ -365,6 +397,10 @@ static const struct idle_cpu idle_cpu_ivb = { 
	.state_table = ivb_cstates,

};



static const struct idle_cpu idle_cpu_hsw = {

	.state_table = hsw_cstates,

};



#define ICPU(model, cpu) \

	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
@@ -382,6 +418,9 @@ static const struct x86_cpu_id intel_idle_ids[] = { 
	ICPU(0x2d, idle_cpu_snb),

	ICPU(0x3a, idle_cpu_ivb),

	ICPU(0x3e, idle_cpu_ivb),

	ICPU(0x3c, idle_cpu_hsw),

	ICPU(0x3f, idle_cpu_hsw),

	ICPU(0x45, idle_cpu_hsw),

	{}

};

MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);