Commit 84058eb8 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau: flatten nv{Read,Write}{MC,VIDEO,FB,EXTDEV} 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent fce875d6

drivers/gpu/drm/nouveau/nouveau_bios.c

+1 −1
Original line number Diff line number Diff line
@@ -246,7 +246,7 @@ int call_lvds_script(struct drm_device *dev, struct dcb_output *dcbent, int head 
	sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;

	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);

	/* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */

	nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);

	nv_wr32(dev, NV_PBUS_POWERCTRL_2, 0);



	return ret;

}

drivers/gpu/drm/nouveau/nouveau_calc.c

+3 −3
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp, 
	struct nv_sim_state sim_data;

	int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);

	int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);

	uint32_t cfg1 = nvReadFB(dev, NV04_PFB_CFG1);

	uint32_t cfg1 = nv_rd32(dev, NV04_PFB_CFG1);



	sim_data.pclk_khz = VClk;

	sim_data.mclk_khz = MClk;
@@ -218,8 +218,8 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp, 
		sim_data.mem_latency = 3;

		sim_data.mem_page_miss = 10;

	} else {

		sim_data.memory_type = nvReadFB(dev, NV04_PFB_CFG0) & 0x1;

		sim_data.memory_width = (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;

		sim_data.memory_type = nv_rd32(dev, NV04_PFB_CFG0) & 0x1;

		sim_data.memory_width = (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;

		sim_data.mem_latency = cfg1 & 0xf;

		sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);

	}

drivers/gpu/drm/nouveau/nouveau_hw.c

+12 −12
Original line number Diff line number Diff line
@@ -172,14 +172,14 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, 
	if (reg1 == 0)

		return -ENOENT;



	pll1 = nvReadMC(dev, reg1);

	pll1 = nv_rd32(dev, reg1);



	if (reg1 <= 0x405c)

		pll2 = nvReadMC(dev, reg1 + 4);

		pll2 = nv_rd32(dev, reg1 + 4);

	else if (nv_two_reg_pll(dev)) {

		uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);



		pll2 = nvReadMC(dev, reg2);

		pll2 = nv_rd32(dev, reg2);

	}



	if (dev_priv->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
@@ -670,15 +670,15 @@ nv_load_state_ext(struct drm_device *dev, int head, 
			 */

			NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);



		nvWriteVIDEO(dev, NV_PVIDEO_STOP, 1);

		nvWriteVIDEO(dev, NV_PVIDEO_INTR_EN, 0);

		nvWriteVIDEO(dev, NV_PVIDEO_OFFSET_BUFF(0), 0);

		nvWriteVIDEO(dev, NV_PVIDEO_OFFSET_BUFF(1), 0);

		nvWriteVIDEO(dev, NV_PVIDEO_LIMIT(0), 0); //dev_priv->fb_available_size - 1);

		nvWriteVIDEO(dev, NV_PVIDEO_LIMIT(1), 0); //dev_priv->fb_available_size - 1);

		nvWriteVIDEO(dev, NV_PVIDEO_UVPLANE_LIMIT(0), 0); //dev_priv->fb_available_size - 1);

		nvWriteVIDEO(dev, NV_PVIDEO_UVPLANE_LIMIT(1), 0); //dev_priv->fb_available_size - 1);

		nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);

		nv_wr32(dev, NV_PVIDEO_STOP, 1);

		nv_wr32(dev, NV_PVIDEO_INTR_EN, 0);

		nv_wr32(dev, NV_PVIDEO_OFFSET_BUFF(0), 0);

		nv_wr32(dev, NV_PVIDEO_OFFSET_BUFF(1), 0);

		nv_wr32(dev, NV_PVIDEO_LIMIT(0), 0); //dev_priv->fb_available_size - 1);

		nv_wr32(dev, NV_PVIDEO_LIMIT(1), 0); //dev_priv->fb_available_size - 1);

		nv_wr32(dev, NV_PVIDEO_UVPLANE_LIMIT(0), 0); //dev_priv->fb_available_size - 1);

		nv_wr32(dev, NV_PVIDEO_UVPLANE_LIMIT(1), 0); //dev_priv->fb_available_size - 1);

		nv_wr32(dev, NV_PBUS_POWERCTRL_2, 0);



		NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);

		NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);

drivers/gpu/drm/nouveau/nouveau_hw.h

+1 −53
Original line number Diff line number Diff line
@@ -57,58 +57,6 @@ void nouveau_hw_load_state_palette(struct drm_device *, int head, 
extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,

			     int *burst, int *lwm);



static inline uint32_t

nvReadMC(struct drm_device *dev, uint32_t reg)

{

	uint32_t val = nv_rd32(dev, reg);

	return val;

}



static inline void

nvWriteMC(struct drm_device *dev, uint32_t reg, uint32_t val)

{

	nv_wr32(dev, reg, val);

}



static inline uint32_t

nvReadVIDEO(struct drm_device *dev, uint32_t reg)

{

	uint32_t val = nv_rd32(dev, reg);

	return val;

}



static inline void

nvWriteVIDEO(struct drm_device *dev, uint32_t reg, uint32_t val)

{

	nv_wr32(dev, reg, val);

}



static inline uint32_t

nvReadFB(struct drm_device *dev, uint32_t reg)

{

	uint32_t val = nv_rd32(dev, reg);

	return val;

}



static inline void

nvWriteFB(struct drm_device *dev, uint32_t reg, uint32_t val)

{

	nv_wr32(dev, reg, val);

}



static inline uint32_t

nvReadEXTDEV(struct drm_device *dev, uint32_t reg)

{

	uint32_t val = nv_rd32(dev, reg);

	return val;

}



static inline void

nvWriteEXTDEV(struct drm_device *dev, uint32_t reg, uint32_t val)

{

	nv_wr32(dev, reg, val);

}



static inline uint32_t NVReadCRTC(struct drm_device *dev,

					int head, uint32_t reg)

{
@@ -302,7 +250,7 @@ nv_heads_tied(struct drm_device *dev) 
	struct drm_nouveau_private *dev_priv = dev->dev_private;



	if (dev_priv->chipset == 0x11)

		return !!(nvReadMC(dev, NV_PBUS_DEBUG_1) & (1 << 28));

		return !!(nv_rd32(dev, NV_PBUS_DEBUG_1) & (1 << 28));



	return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4;

}

drivers/gpu/drm/nouveau/nv04_dac.c

+6 −6
Original line number Diff line number Diff line
@@ -245,12 +245,12 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) 
	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset,

		      saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);



	saved_powerctrl_2 = nvReadMC(dev, NV_PBUS_POWERCTRL_2);

	saved_powerctrl_2 = nv_rd32(dev, NV_PBUS_POWERCTRL_2);



	nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);

	nv_wr32(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);

	if (regoffset == 0x68) {

		saved_powerctrl_4 = nvReadMC(dev, NV_PBUS_POWERCTRL_4);

		nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);

		saved_powerctrl_4 = nv_rd32(dev, NV_PBUS_POWERCTRL_4);

		nv_wr32(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);

	}



	saved_gpio1 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC1);
@@ -304,8 +304,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) 
	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput);

	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);

	if (regoffset == 0x68)

		nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);

	nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);

		nv_wr32(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);

	nv_wr32(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);



	nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, saved_gpio1);

	nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, saved_gpio0);