Loading drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c +1 −1 Original line number Diff line number Diff line Loading @@ -297,7 +297,7 @@ nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, int clk, struct nouveau_pll_vals *pv) { int N1, M1, N2, M2, P; int ret = nv04_pll_calc(clock, info, clk, &N1, &M1, &N2, &M2, &P); int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P); if (ret) { pv->refclk = info->refclk; pv->N1 = N1; Loading drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c +1 −1 Original line number Diff line number Diff line Loading @@ -47,7 +47,7 @@ nv50_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) return ret; } ret = nv04_pll_calc(clk, &info, freq, &N1, &M1, &N2, &M2, &P); ret = nv04_pll_calc(nv_subdev(clk), &info, freq, &N1, &M1, &N2, &M2, &P); if (!ret) { nv_error(clk, "failed pll calculation\n"); return ret; Loading drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c +2 −2 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) if (ret) return ret; ret = nva3_pll_calc(clk, &info, freq, &N, &fN, &M, &P); ret = nva3_pll_calc(nv_subdev(clk), &info, freq, &N, &fN, &M, &P); if (ret < 0) return ret; Loading @@ -72,7 +72,7 @@ nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, { int ret, N, M, P; ret = nva3_pll_calc(clock, info, clk, &N, NULL, &M, &P); ret = nva3_pll_calc(nv_subdev(clock), info, clk, &N, NULL, &M, &P); if (ret > 0) { pv->refclk = info->refclk; Loading drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c +1 −1 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ nvc0_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) if (ret) return ret; ret = nva3_pll_calc(clk, &info, freq, &N, &fN, &M, &P); ret = nva3_pll_calc(nv_subdev(clk), &info, freq, &N, &fN, &M, &P); if (ret < 0) return ret; Loading drivers/gpu/drm/nouveau/core/subdev/clock/pll.h +2 −2 Original line number Diff line number Diff line #ifndef __NOUVEAU_PLL_H__ #define __NOUVEAU_PLL_H__ int nv04_pll_calc(struct nouveau_clock *, struct nvbios_pll *, u32 freq, int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, int *N1, int *M1, int *N2, int *M2, int *P); int nva3_pll_calc(struct nouveau_clock *, struct nvbios_pll *, u32 freq, int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, int *N, int *fN, int *M, int *P); #endif Loading
drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c +1 −1 Original line number Diff line number Diff line Loading @@ -297,7 +297,7 @@ nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, int clk, struct nouveau_pll_vals *pv) { int N1, M1, N2, M2, P; int ret = nv04_pll_calc(clock, info, clk, &N1, &M1, &N2, &M2, &P); int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P); if (ret) { pv->refclk = info->refclk; pv->N1 = N1; Loading
drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c +1 −1 Original line number Diff line number Diff line Loading @@ -47,7 +47,7 @@ nv50_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) return ret; } ret = nv04_pll_calc(clk, &info, freq, &N1, &M1, &N2, &M2, &P); ret = nv04_pll_calc(nv_subdev(clk), &info, freq, &N1, &M1, &N2, &M2, &P); if (!ret) { nv_error(clk, "failed pll calculation\n"); return ret; Loading
drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c +2 −2 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) if (ret) return ret; ret = nva3_pll_calc(clk, &info, freq, &N, &fN, &M, &P); ret = nva3_pll_calc(nv_subdev(clk), &info, freq, &N, &fN, &M, &P); if (ret < 0) return ret; Loading @@ -72,7 +72,7 @@ nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, { int ret, N, M, P; ret = nva3_pll_calc(clock, info, clk, &N, NULL, &M, &P); ret = nva3_pll_calc(nv_subdev(clock), info, clk, &N, NULL, &M, &P); if (ret > 0) { pv->refclk = info->refclk; Loading
drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c +1 −1 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ nvc0_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) if (ret) return ret; ret = nva3_pll_calc(clk, &info, freq, &N, &fN, &M, &P); ret = nva3_pll_calc(nv_subdev(clk), &info, freq, &N, &fN, &M, &P); if (ret < 0) return ret; Loading
drivers/gpu/drm/nouveau/core/subdev/clock/pll.h +2 −2 Original line number Diff line number Diff line #ifndef __NOUVEAU_PLL_H__ #define __NOUVEAU_PLL_H__ int nv04_pll_calc(struct nouveau_clock *, struct nvbios_pll *, u32 freq, int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, int *N1, int *M1, int *N2, int *M2, int *P); int nva3_pll_calc(struct nouveau_clock *, struct nvbios_pll *, u32 freq, int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, int *N, int *fN, int *M, int *P); #endif