Loading arch/mips/alchemy/common/time.c +1 −2 Original line number Diff line number Diff line Loading @@ -141,8 +141,7 @@ static int __init alchemy_time_init(unsigned int m2int) goto cntr_err; /* register counter1 clocksource and event device */ clocksource_set_clock(&au1x_counter1_clocksource, 32768); clocksource_register(&au1x_counter1_clocksource); clocksource_register_hz(&au1x_counter1_clocksource, 32768); cd->shift = 32; cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift); Loading arch/mips/cavium-octeon/csrc-octeon.c +1 −2 Original line number Diff line number Diff line Loading @@ -105,8 +105,7 @@ unsigned long long notrace sched_clock(void) void __init plat_time_init(void) { clocksource_mips.rating = 300; clocksource_set_clock(&clocksource_mips, octeon_get_clock_rate()); clocksource_register(&clocksource_mips); clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate()); } static u64 octeon_udelay_factor; Loading arch/mips/include/asm/time.h +0 −6 Original line number Diff line number Diff line Loading @@ -84,12 +84,6 @@ static inline int init_mips_clocksource(void) #endif } static inline void clocksource_set_clock(struct clocksource *cs, unsigned int clock) { clocksource_calc_mult_shift(cs, clock, 4); } static inline void clockevent_set_clock(struct clock_event_device *cd, unsigned int clock) { Loading arch/mips/jz4740/time.c +1 −2 Original line number Diff line number Diff line Loading @@ -121,8 +121,7 @@ void __init plat_time_init(void) clockevents_register_device(&jz4740_clockevent); clocksource_set_clock(&jz4740_clocksource, clk_rate); ret = clocksource_register(&jz4740_clocksource); ret = clocksource_register_hz(&jz4740_clocksource, clk_rate); if (ret) printk(KERN_ERR "Failed to register clocksource: %d\n", ret); Loading arch/mips/kernel/cevt-txx9.c +1 −2 Original line number Diff line number Diff line Loading @@ -51,8 +51,7 @@ void __init txx9_clocksource_init(unsigned long baseaddr, { struct txx9_tmr_reg __iomem *tmrptr; clocksource_set_clock(&txx9_clocksource.cs, TIMER_CLK(imbusclk)); clocksource_register(&txx9_clocksource.cs); clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk)); tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); __raw_writel(TCR_BASE, &tmrptr->tcr); Loading Loading
arch/mips/alchemy/common/time.c +1 −2 Original line number Diff line number Diff line Loading @@ -141,8 +141,7 @@ static int __init alchemy_time_init(unsigned int m2int) goto cntr_err; /* register counter1 clocksource and event device */ clocksource_set_clock(&au1x_counter1_clocksource, 32768); clocksource_register(&au1x_counter1_clocksource); clocksource_register_hz(&au1x_counter1_clocksource, 32768); cd->shift = 32; cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift); Loading
arch/mips/cavium-octeon/csrc-octeon.c +1 −2 Original line number Diff line number Diff line Loading @@ -105,8 +105,7 @@ unsigned long long notrace sched_clock(void) void __init plat_time_init(void) { clocksource_mips.rating = 300; clocksource_set_clock(&clocksource_mips, octeon_get_clock_rate()); clocksource_register(&clocksource_mips); clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate()); } static u64 octeon_udelay_factor; Loading
arch/mips/include/asm/time.h +0 −6 Original line number Diff line number Diff line Loading @@ -84,12 +84,6 @@ static inline int init_mips_clocksource(void) #endif } static inline void clocksource_set_clock(struct clocksource *cs, unsigned int clock) { clocksource_calc_mult_shift(cs, clock, 4); } static inline void clockevent_set_clock(struct clock_event_device *cd, unsigned int clock) { Loading
arch/mips/jz4740/time.c +1 −2 Original line number Diff line number Diff line Loading @@ -121,8 +121,7 @@ void __init plat_time_init(void) clockevents_register_device(&jz4740_clockevent); clocksource_set_clock(&jz4740_clocksource, clk_rate); ret = clocksource_register(&jz4740_clocksource); ret = clocksource_register_hz(&jz4740_clocksource, clk_rate); if (ret) printk(KERN_ERR "Failed to register clocksource: %d\n", ret); Loading
arch/mips/kernel/cevt-txx9.c +1 −2 Original line number Diff line number Diff line Loading @@ -51,8 +51,7 @@ void __init txx9_clocksource_init(unsigned long baseaddr, { struct txx9_tmr_reg __iomem *tmrptr; clocksource_set_clock(&txx9_clocksource.cs, TIMER_CLK(imbusclk)); clocksource_register(&txx9_clocksource.cs); clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk)); tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); __raw_writel(TCR_BASE, &tmrptr->tcr); Loading