Commit 746078b3 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/selftests: Exercise adjusting rpcs over all render-class engines



Iterate over all user-accessible render engines when checking whether
they can be adjusted for sseu.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191027225808.19437-2-chris@chris-wilson.co.uk
parent 6804da20
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+61 −66
Original line number Diff line number Diff line
@@ -1186,57 +1186,52 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
	       const char *name,
	       unsigned int flags)
{
	struct intel_engine_cs *engine = i915->engine[RCS0];
	struct drm_i915_gem_object *obj;
	struct i915_gem_context *ctx;
	struct intel_context *ce;
	struct intel_sseu pg_sseu;
	struct drm_file *file;
	int inst = 0;
	int ret;

	if (INTEL_GEN(i915) < 9 || !engine)
	if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg)
		return 0;

	if (!RUNTIME_INFO(i915)->sseu.has_slice_pg)
		return 0;
	if (flags & TEST_RESET)
		igt_global_reset_lock(&i915->gt);

	obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
	if (IS_ERR(obj)) {
		ret = PTR_ERR(obj);
		goto out_unlock;
	}

	do {
		struct intel_engine_cs *engine;
		struct intel_context *ce;
		struct intel_sseu pg_sseu;

		engine = intel_engine_lookup_user(i915,
						  I915_ENGINE_CLASS_RENDER,
						  inst++);
		if (!engine)
			break;

		if (hweight32(engine->sseu.slice_mask) < 2)
		return 0;
			continue;

		/*
	 * Gen11 VME friendly power-gated configuration with half enabled
	 * sub-slices.
		 * Gen11 VME friendly power-gated configuration with
		 * half enabled sub-slices.
		 */
		pg_sseu = engine->sseu;
		pg_sseu.slice_mask = 1;
		pg_sseu.subslice_mask =
			~(~0 << (hweight32(engine->sseu.subslice_mask) / 2));

	pr_info("SSEU subtest '%s', flags=%x, def_slices=%u, pg_slices=%u\n",
		name, flags, hweight32(engine->sseu.slice_mask),
		pr_info("%s: SSEU subtest '%s', flags=%x, def_slices=%u, pg_slices=%u\n",
			engine->name, name, flags,
			hweight32(engine->sseu.slice_mask),
			hweight32(pg_sseu.slice_mask));

	file = mock_file(i915);
	if (IS_ERR(file))
		return PTR_ERR(file);

	if (flags & TEST_RESET)
		igt_global_reset_lock(&i915->gt);

	ctx = live_context(i915, file);
	if (IS_ERR(ctx)) {
		ret = PTR_ERR(ctx);
		goto out_unlock;
	}
	i915_gem_context_clear_bannable(ctx); /* to reset and beyond! */

	obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
	if (IS_ERR(obj)) {
		ret = PTR_ERR(obj);
		goto out_unlock;
	}

	ce = i915_gem_context_get_engine(ctx, RCS0);
		ce = intel_context_create(engine->kernel_context->gem_context,
					  engine);
		if (IS_ERR(ce)) {
			ret = PTR_ERR(ce);
			goto out_put;
@@ -1244,35 +1239,37 @@ __igt_ctx_sseu(struct drm_i915_private *i915,

		ret = intel_context_pin(ce);
		if (ret)
		goto out_context;
			goto out_ce;

		/* First set the default mask. */
		ret = __sseu_test(name, flags, ce, obj, engine->sseu);
		if (ret)
		goto out_fail;
			goto out_unpin;

		/* Then set a power-gated configuration. */
		ret = __sseu_test(name, flags, ce, obj, pg_sseu);
		if (ret)
		goto out_fail;
			goto out_unpin;

		/* Back to defaults. */
		ret = __sseu_test(name, flags, ce, obj, engine->sseu);
		if (ret)
		goto out_fail;
			goto out_unpin;

		/* One last power-gated configuration for the road. */
		ret = __sseu_test(name, flags, ce, obj, pg_sseu);
		if (ret)
		goto out_fail;
			goto out_unpin;

out_unpin:
		intel_context_unpin(ce);
out_ce:
		intel_context_put(ce);
	} while (!ret);

out_fail:
	if (igt_flush_test(i915))
		ret = -EIO;

	intel_context_unpin(ce);
out_context:
	intel_context_put(ce);
out_put:
	i915_gem_object_put(obj);

@@ -1280,8 +1277,6 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
	if (flags & TEST_RESET)
		igt_global_reset_unlock(&i915->gt);

	mock_file_free(i915, file);

	if (ret)
		pr_err("%s: Failed with %d!\n", name, ret);