Loading drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +6 −7 Original line number Diff line number Diff line Loading @@ -1047,11 +1047,10 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nv_mask(priv, 0x000260, 0x00000001, 0x00000000); for (i = 0; oclass->mmio[i]; i++) nvc0_graph_mmio(priv, oclass->mmio[i]); for (i = 0; oclass->hub[i]; i++) nvc0_graph_mmio(priv, oclass->hub[i]); for (i = 0; oclass->gpc[i]; i++) nvc0_graph_mmio(priv, oclass->gpc[i]); nvc0_graph_mmio(priv, oclass->tpc); nv_wr32(priv, 0x404154, 0x00000000); Loading Loading @@ -1179,7 +1178,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) } struct nvc0_graph_init * nvc0_grctx_init_mmio[] = { nvc0_grctx_init_hub[] = { nvc0_grctx_init_base, nvc0_grctx_init_unk40xx, nvc0_grctx_init_unk44xx, Loading @@ -1194,10 +1193,11 @@ nvc0_grctx_init_mmio[] = { NULL }; struct nvc0_graph_init * static struct nvc0_graph_init * nvc0_grctx_init_gpc[] = { nvc0_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, nvc0_grctx_init_tpc, NULL }; Loading Loading @@ -1230,9 +1230,8 @@ nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc0_grctx_generate_mods, .mmio = nvc0_grctx_init_mmio, .hub = nvc0_grctx_init_hub, .gpc = nvc0_grctx_init_gpc, .tpc = nvc0_grctx_init_tpc, .icmd = nvc0_grctx_init_icmd, .mthd = nvc0_grctx_init_mthd, }.base; drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c +3 −3 Original line number Diff line number Diff line Loading @@ -757,7 +757,7 @@ nvc1_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) } static struct nvc0_graph_init * nvc1_grctx_init_mmio[] = { nvc1_grctx_init_hub[] = { nvc0_grctx_init_base, nvc0_grctx_init_unk40xx, nvc0_grctx_init_unk44xx, Loading @@ -776,6 +776,7 @@ struct nvc0_graph_init * nvc1_grctx_init_gpc[] = { nvc1_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, nvc1_grctx_init_tpc, NULL }; Loading Loading @@ -803,9 +804,8 @@ nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc1_grctx_generate_mods, .mmio = nvc1_grctx_init_mmio, .hub = nvc1_grctx_init_hub, .gpc = nvc1_grctx_init_gpc, .tpc = nvc1_grctx_init_tpc, .icmd = nvc1_grctx_init_icmd, .mthd = nvc1_grctx_init_mthd, }.base; drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c +10 −3 Original line number Diff line number Diff line Loading @@ -70,6 +70,14 @@ nvc3_grctx_init_tpc[] = { {} }; struct nvc0_graph_init * nvc3_grctx_init_gpc[] = { nvc0_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, nvc3_grctx_init_tpc, NULL }; struct nouveau_oclass * nvc3_grctx_oclass = &(struct nvc0_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xc3), Loading @@ -83,9 +91,8 @@ nvc3_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc0_grctx_generate_mods, .mmio = nvc0_grctx_init_mmio, .gpc = nvc0_grctx_init_gpc, .tpc = nvc3_grctx_init_tpc, .hub = nvc0_grctx_init_hub, .gpc = nvc3_grctx_init_gpc, .icmd = nvc0_grctx_init_icmd, .mthd = nvc0_grctx_init_mthd, }.base; drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c +10 −3 Original line number Diff line number Diff line Loading @@ -341,6 +341,14 @@ nvc8_grctx_init_mthd[] = { {} }; static struct nvc0_graph_init * nvc8_grctx_init_gpc[] = { nvc0_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, nvc8_grctx_init_tpc, NULL }; struct nouveau_oclass * nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xc8), Loading @@ -354,9 +362,8 @@ nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc0_grctx_generate_mods, .mmio = nvc0_grctx_init_mmio, .gpc = nvc0_grctx_init_gpc, .tpc = nvc8_grctx_init_tpc, .hub = nvc0_grctx_init_hub, .gpc = nvc8_grctx_init_gpc, .icmd = nvc8_grctx_init_icmd, .mthd = nvc8_grctx_init_mthd, }.base; drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c +3 −3 Original line number Diff line number Diff line Loading @@ -454,7 +454,7 @@ nvd9_grctx_init_tpc[] = { }; static struct nvc0_graph_init * nvd9_grctx_init_mmio[] = { nvd9_grctx_init_hub[] = { nvc0_grctx_init_base, nvd9_grctx_init_unk40xx, nvc0_grctx_init_unk44xx, Loading @@ -472,6 +472,7 @@ struct nvc0_graph_init * nvd9_grctx_init_gpc[] = { nvd9_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, nvd9_grctx_init_tpc, NULL }; Loading Loading @@ -506,9 +507,8 @@ nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc1_grctx_generate_mods, .mmio = nvd9_grctx_init_mmio, .hub = nvd9_grctx_init_hub, .gpc = nvd9_grctx_init_gpc, .tpc = nvd9_grctx_init_tpc, .icmd = nvd9_grctx_init_icmd, .mthd = nvd9_grctx_init_mthd, }.base; Loading
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +6 −7 Original line number Diff line number Diff line Loading @@ -1047,11 +1047,10 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nv_mask(priv, 0x000260, 0x00000001, 0x00000000); for (i = 0; oclass->mmio[i]; i++) nvc0_graph_mmio(priv, oclass->mmio[i]); for (i = 0; oclass->hub[i]; i++) nvc0_graph_mmio(priv, oclass->hub[i]); for (i = 0; oclass->gpc[i]; i++) nvc0_graph_mmio(priv, oclass->gpc[i]); nvc0_graph_mmio(priv, oclass->tpc); nv_wr32(priv, 0x404154, 0x00000000); Loading Loading @@ -1179,7 +1178,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) } struct nvc0_graph_init * nvc0_grctx_init_mmio[] = { nvc0_grctx_init_hub[] = { nvc0_grctx_init_base, nvc0_grctx_init_unk40xx, nvc0_grctx_init_unk44xx, Loading @@ -1194,10 +1193,11 @@ nvc0_grctx_init_mmio[] = { NULL }; struct nvc0_graph_init * static struct nvc0_graph_init * nvc0_grctx_init_gpc[] = { nvc0_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, nvc0_grctx_init_tpc, NULL }; Loading Loading @@ -1230,9 +1230,8 @@ nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc0_grctx_generate_mods, .mmio = nvc0_grctx_init_mmio, .hub = nvc0_grctx_init_hub, .gpc = nvc0_grctx_init_gpc, .tpc = nvc0_grctx_init_tpc, .icmd = nvc0_grctx_init_icmd, .mthd = nvc0_grctx_init_mthd, }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c +3 −3 Original line number Diff line number Diff line Loading @@ -757,7 +757,7 @@ nvc1_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) } static struct nvc0_graph_init * nvc1_grctx_init_mmio[] = { nvc1_grctx_init_hub[] = { nvc0_grctx_init_base, nvc0_grctx_init_unk40xx, nvc0_grctx_init_unk44xx, Loading @@ -776,6 +776,7 @@ struct nvc0_graph_init * nvc1_grctx_init_gpc[] = { nvc1_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, nvc1_grctx_init_tpc, NULL }; Loading Loading @@ -803,9 +804,8 @@ nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc1_grctx_generate_mods, .mmio = nvc1_grctx_init_mmio, .hub = nvc1_grctx_init_hub, .gpc = nvc1_grctx_init_gpc, .tpc = nvc1_grctx_init_tpc, .icmd = nvc1_grctx_init_icmd, .mthd = nvc1_grctx_init_mthd, }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c +10 −3 Original line number Diff line number Diff line Loading @@ -70,6 +70,14 @@ nvc3_grctx_init_tpc[] = { {} }; struct nvc0_graph_init * nvc3_grctx_init_gpc[] = { nvc0_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, nvc3_grctx_init_tpc, NULL }; struct nouveau_oclass * nvc3_grctx_oclass = &(struct nvc0_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xc3), Loading @@ -83,9 +91,8 @@ nvc3_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc0_grctx_generate_mods, .mmio = nvc0_grctx_init_mmio, .gpc = nvc0_grctx_init_gpc, .tpc = nvc3_grctx_init_tpc, .hub = nvc0_grctx_init_hub, .gpc = nvc3_grctx_init_gpc, .icmd = nvc0_grctx_init_icmd, .mthd = nvc0_grctx_init_mthd, }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c +10 −3 Original line number Diff line number Diff line Loading @@ -341,6 +341,14 @@ nvc8_grctx_init_mthd[] = { {} }; static struct nvc0_graph_init * nvc8_grctx_init_gpc[] = { nvc0_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, nvc8_grctx_init_tpc, NULL }; struct nouveau_oclass * nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xc8), Loading @@ -354,9 +362,8 @@ nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc0_grctx_generate_mods, .mmio = nvc0_grctx_init_mmio, .gpc = nvc0_grctx_init_gpc, .tpc = nvc8_grctx_init_tpc, .hub = nvc0_grctx_init_hub, .gpc = nvc8_grctx_init_gpc, .icmd = nvc8_grctx_init_icmd, .mthd = nvc8_grctx_init_mthd, }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c +3 −3 Original line number Diff line number Diff line Loading @@ -454,7 +454,7 @@ nvd9_grctx_init_tpc[] = { }; static struct nvc0_graph_init * nvd9_grctx_init_mmio[] = { nvd9_grctx_init_hub[] = { nvc0_grctx_init_base, nvd9_grctx_init_unk40xx, nvc0_grctx_init_unk44xx, Loading @@ -472,6 +472,7 @@ struct nvc0_graph_init * nvd9_grctx_init_gpc[] = { nvd9_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, nvd9_grctx_init_tpc, NULL }; Loading Loading @@ -506,9 +507,8 @@ nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc1_grctx_generate_mods, .mmio = nvd9_grctx_init_mmio, .hub = nvd9_grctx_init_hub, .gpc = nvd9_grctx_init_gpc, .tpc = nvd9_grctx_init_tpc, .icmd = nvd9_grctx_init_icmd, .mthd = nvd9_grctx_init_mthd, }.base;