Commit 64d598a1 authored by Neil Armstrong's avatar Neil Armstrong
Browse files

drm/meson: Add G12A support for CVBS Encoder 



The Meson G12A SoCs uses the exact same CVBS encoder except a simple
CVBS DAC register offset and settings delta.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
[narmstrong: fixed subject typo]
Tested-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-9-narmstrong@baylibre.com
parent 68679d41

drivers/gpu/drm/meson/meson_venc.c

+9 −2
Original line number Original line Diff line number Diff line
@@ -73,7 +73,9 @@ 
/* HHI Registers */

/* HHI Registers */

#define HHI_GCLK_MPEG2		0x148 /* 0x52 offset in data sheet */

#define HHI_GCLK_MPEG2		0x148 /* 0x52 offset in data sheet */

#define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */

#define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */

#define HHI_VDAC_CNTL0_G12A	0x2EC /* 0xbd offset in data sheet */

#define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */

#define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */

#define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbe offset in data sheet */

#define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 offset in data sheet */

#define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 offset in data sheet */





struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {

struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
@@ -1675,8 +1677,13 @@ void meson_venc_disable_vsync(struct meson_drm *priv) 
void meson_venc_init(struct meson_drm *priv)

void meson_venc_init(struct meson_drm *priv)

{

{

	/* Disable CVBS VDAC */

	/* Disable CVBS VDAC */

	if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {

		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);

		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8);

	} else {

		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);

		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);

		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);

		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);

	}





	/* Power Down Dacs */

	/* Power Down Dacs */

	writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));

	writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));

drivers/gpu/drm/meson/meson_venc_cvbs.c

+18 −7
Original line number Original line Diff line number Diff line
@@ -37,7 +37,9 @@ 




/* HHI VDAC Registers */

/* HHI VDAC Registers */

#define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */

#define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */

#define HHI_VDAC_CNTL0_G12A	0x2EC /* 0xbd offset in data sheet */

#define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */

#define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */

#define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbe offset in data sheet */





struct meson_venc_cvbs {

struct meson_venc_cvbs {

	struct drm_encoder	encoder;

	struct drm_encoder	encoder;
@@ -166,9 +168,14 @@ static void meson_venc_cvbs_encoder_disable(struct drm_encoder *encoder) 
	struct meson_drm *priv = meson_venc_cvbs->priv;

	struct meson_drm *priv = meson_venc_cvbs->priv;





	/* Disable CVBS VDAC */

	/* Disable CVBS VDAC */

	if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {

		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);

		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);

	} else {

		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);

		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);

		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);

		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);

	}

	}

}





static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder)

static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder)

{

{
@@ -179,13 +186,17 @@ static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder) 
	/* VDAC0 source is not from ATV */

	/* VDAC0 source is not from ATV */

	writel_bits_relaxed(BIT(5), 0, priv->io_base + _REG(VENC_VDAC_DACSEL0));

	writel_bits_relaxed(BIT(5), 0, priv->io_base + _REG(VENC_VDAC_DACSEL0));





	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))

	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {

		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);

		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);

	else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||

		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);

		 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))

	} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||

		 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {

		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001);

		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001);



		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);

		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);

	} else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {

		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001);

		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);

	}

}

}





static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder,

static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder,