Loading arch/arm/boot/dts/imx51.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -221,6 +221,14 @@ gpio4: gpio@73f90000 { #interrupt-cells = <2>; }; kpp: kpp@73f94000 { compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; reg = <0x73f94000 0x4000>; interrupts = <60>; clocks = <&clks 0>; status = "disabled"; }; wdog1: wdog@73f98000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; Loading Loading @@ -410,6 +418,21 @@ pinctrl_uart3_1: uart3grp-1 { >; }; }; kpp { pinctrl_kpp_1: kppgrp-1 { fsl,pins = < 438 0xe0 /* MX51_PAD_KEY_ROW0__KEY_ROW0 */ 439 0xe0 /* MX51_PAD_KEY_ROW1__KEY_ROW1 */ 440 0xe0 /* MX51_PAD_KEY_ROW2__KEY_ROW2 */ 441 0xe0 /* MX51_PAD_KEY_ROW3__KEY_ROW3 */ 442 0xe8 /* MX51_PAD_KEY_COL0__KEY_COL0 */ 444 0xe8 /* MX51_PAD_KEY_COL1__KEY_COL1 */ 446 0xe8 /* MX51_PAD_KEY_COL2__KEY_COL2 */ 448 0xe8 /* MX51_PAD_KEY_COL3__KEY_COL3 */ >; }; }; }; pwm1: pwm@73fb4000 { Loading Loading
arch/arm/boot/dts/imx51.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -221,6 +221,14 @@ gpio4: gpio@73f90000 { #interrupt-cells = <2>; }; kpp: kpp@73f94000 { compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; reg = <0x73f94000 0x4000>; interrupts = <60>; clocks = <&clks 0>; status = "disabled"; }; wdog1: wdog@73f98000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; Loading Loading @@ -410,6 +418,21 @@ pinctrl_uart3_1: uart3grp-1 { >; }; }; kpp { pinctrl_kpp_1: kppgrp-1 { fsl,pins = < 438 0xe0 /* MX51_PAD_KEY_ROW0__KEY_ROW0 */ 439 0xe0 /* MX51_PAD_KEY_ROW1__KEY_ROW1 */ 440 0xe0 /* MX51_PAD_KEY_ROW2__KEY_ROW2 */ 441 0xe0 /* MX51_PAD_KEY_ROW3__KEY_ROW3 */ 442 0xe8 /* MX51_PAD_KEY_COL0__KEY_COL0 */ 444 0xe8 /* MX51_PAD_KEY_COL1__KEY_COL1 */ 446 0xe8 /* MX51_PAD_KEY_COL2__KEY_COL2 */ 448 0xe8 /* MX51_PAD_KEY_COL3__KEY_COL3 */ >; }; }; }; pwm1: pwm@73fb4000 { Loading