Loading drivers/gpu/drm/i915/intel_pm.c +22 −34 Original line number Diff line number Diff line Loading @@ -5061,7 +5061,6 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) struct drm_device *dev = dev_priv->dev; u32 val, rp0; if (dev->pdev->revision >= 0x20) { val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); switch (INTEL_INFO(dev)->eu_total) { Loading @@ -5080,13 +5079,9 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); break; } rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); } else { /* For pre-production hardware */ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; } return rp0; } Loading @@ -5102,18 +5097,11 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; u32 val, rp1; if (dev->pdev->revision >= 0x20) { val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); rp1 = (val & FB_GFX_FREQ_FUSE_MASK); } else { /* For pre-production hardware */ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK); } return rp1; } Loading Loading
drivers/gpu/drm/i915/intel_pm.c +22 −34 Original line number Diff line number Diff line Loading @@ -5061,7 +5061,6 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) struct drm_device *dev = dev_priv->dev; u32 val, rp0; if (dev->pdev->revision >= 0x20) { val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); switch (INTEL_INFO(dev)->eu_total) { Loading @@ -5080,13 +5079,9 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); break; } rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); } else { /* For pre-production hardware */ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; } return rp0; } Loading @@ -5102,18 +5097,11 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; u32 val, rp1; if (dev->pdev->revision >= 0x20) { val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); rp1 = (val & FB_GFX_FREQ_FUSE_MASK); } else { /* For pre-production hardware */ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK); } return rp1; } Loading