Commit 599a7e9f authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: implement smu7 hwmgr to manager asics with smu ip version 7. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarKen Wang <Qingqing.Wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ee1a51f8

drivers/gpu/drm/amd/powerplay/hwmgr/Makefile

+13 −10
Original line number Diff line number Diff line
@@ -10,10 +10,13 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ 
		fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \

		fiji_clockpowergating.o fiji_thermal.o \

		polaris10_hwmgr.o polaris10_powertune.o polaris10_thermal.o \

	       polaris10_clockpowergating.o iceland_hwmgr.o \

		polaris10_clockpowergating.o \

		smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \

		smu7_clockpowergating.o iceland_hwmgr.o \

		iceland_clockpowergating.o iceland_thermal.o \

		iceland_powertune.o





AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))



AMD_POWERPLAY_FILES += $(AMD_PP_HWMGR)

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c

0 → 100644
+488 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#include "smu7_hwmgr.h"

#include "smu7_clockpowergating.h"

#include "smu7_common.h"



static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)

{

	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?

			PPSMC_MSG_UVDDPM_Enable :

			PPSMC_MSG_UVDDPM_Disable);

}



static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)

{

	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?

			PPSMC_MSG_VCEDPM_Enable :

			PPSMC_MSG_VCEDPM_Disable);

}



static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)

{

	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?

			PPSMC_MSG_SAMUDPM_Enable :

			PPSMC_MSG_SAMUDPM_Disable);

}



static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)

{

	if (!bgate)

		smum_update_smc_table(hwmgr, SMU_UVD_TABLE);

	return smu7_enable_disable_uvd_dpm(hwmgr, !bgate);

}



static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)

{

	if (!bgate)

		smum_update_smc_table(hwmgr, SMU_VCE_TABLE);

	return smu7_enable_disable_vce_dpm(hwmgr, !bgate);

}



static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)

{

	if (!bgate)

		smum_update_smc_table(hwmgr, SMU_SAMU_TABLE);

	return smu7_enable_disable_samu_dpm(hwmgr, !bgate);

}



int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)

{

	if (phm_cf_want_uvd_power_gating(hwmgr))

		return smum_send_msg_to_smc(hwmgr->smumgr,

				PPSMC_MSG_UVDPowerOFF);

	return 0;

}



int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)

{

	if (phm_cf_want_uvd_power_gating(hwmgr)) {

		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,

				  PHM_PlatformCaps_UVDDynamicPowerGating)) {

			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,

					PPSMC_MSG_UVDPowerON, 1);

		} else {

			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,

					PPSMC_MSG_UVDPowerON, 0);

		}

	}



	return 0;

}



int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)

{

	if (phm_cf_want_vce_power_gating(hwmgr))

		return smum_send_msg_to_smc(hwmgr->smumgr,

				PPSMC_MSG_VCEPowerOFF);

	return 0;

}



int smu7_powerup_vce(struct pp_hwmgr *hwmgr)

{

	if (phm_cf_want_vce_power_gating(hwmgr))

		return smum_send_msg_to_smc(hwmgr->smumgr,

				PPSMC_MSG_VCEPowerON);

	return 0;

}



int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)

{

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,

			PHM_PlatformCaps_SamuPowerGating))

		return smum_send_msg_to_smc(hwmgr->smumgr,

				PPSMC_MSG_SAMPowerOFF);

	return 0;

}



int smu7_powerup_samu(struct pp_hwmgr *hwmgr)

{

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,

			PHM_PlatformCaps_SamuPowerGating))

		return smum_send_msg_to_smc(hwmgr->smumgr,

				PPSMC_MSG_SAMPowerON);

	return 0;

}



int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr)

{

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);



	data->uvd_power_gated = false;

	data->vce_power_gated = false;

	data->samu_power_gated = false;



	smu7_powerup_uvd(hwmgr);

	smu7_powerup_vce(hwmgr);

	smu7_powerup_samu(hwmgr);



	return 0;

}



int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)

{

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);



	data->uvd_power_gated = bgate;



	if (bgate) {

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_UVD,

				AMD_CG_STATE_GATE);

		smu7_update_uvd_dpm(hwmgr, true);

		smu7_powerdown_uvd(hwmgr);

	} else {

		smu7_powerup_uvd(hwmgr);

		smu7_update_uvd_dpm(hwmgr, false);

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_UVD,

				AMD_CG_STATE_UNGATE);

	}



	return 0;

}



int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)

{

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);



	if (data->vce_power_gated == bgate)

		return 0;



	data->vce_power_gated = bgate;



	if (bgate) {

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_VCE,

				AMD_CG_STATE_GATE);

		smu7_update_vce_dpm(hwmgr, true);

		smu7_powerdown_vce(hwmgr);

	} else {

		smu7_powerup_vce(hwmgr);

		smu7_update_vce_dpm(hwmgr, false);

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_VCE,

				AMD_CG_STATE_UNGATE);

	}

	return 0;

}



int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)

{

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);



	if (data->samu_power_gated == bgate)

		return 0;



	data->samu_power_gated = bgate;



	if (bgate) {

		smu7_update_samu_dpm(hwmgr, true);

		smu7_powerdown_samu(hwmgr);

	} else {

		smu7_powerup_samu(hwmgr);

		smu7_update_samu_dpm(hwmgr, false);

	}



	return 0;

}



int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,

					const uint32_t *msg_id)

{

	PPSMC_Msg msg;

	uint32_t value;



	if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU))

		return 0;



	switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) {

	case PP_GROUP_GFX:

		switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {

		case PP_BLOCK_GFX_CG:

			if (PP_STATE_SUPPORT_CG & *msg_id) {

				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_GFX_CGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			if (PP_STATE_SUPPORT_LS & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS

					? PPSMC_MSG_EnableClockGatingFeature

					: PPSMC_MSG_DisableClockGatingFeature;

				value = CG_GFX_CGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		case PP_BLOCK_GFX_3D:

			if (PP_STATE_SUPPORT_CG & *msg_id) {

				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_GFX_3DCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}



			if  (PP_STATE_SUPPORT_LS & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_GFX_3DLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		case PP_BLOCK_GFX_RLC:

			if (PP_STATE_SUPPORT_LS & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_GFX_RLC_LS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		case PP_BLOCK_GFX_CP:

			if (PP_STATE_SUPPORT_LS & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_GFX_CP_LS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		case PP_BLOCK_GFX_MG:

			if (PP_STATE_SUPPORT_CG & *msg_id) {

				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = (CG_CPF_MGCG_MASK | CG_RLC_MGCG_MASK |

						CG_GFX_OTHERS_MGCG_MASK);



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		default:

			return -EINVAL;

		}

		break;



	case PP_GROUP_SYS:

		switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {

		case PP_BLOCK_SYS_BIF:

			if (PP_STATE_SUPPORT_CG & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_BIF_MGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			if  (PP_STATE_SUPPORT_LS & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_BIF_MGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		case PP_BLOCK_SYS_MC:

			if (PP_STATE_SUPPORT_CG & *msg_id) {

				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_MC_MGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}



			if (PP_STATE_SUPPORT_LS & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_MC_MGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		case PP_BLOCK_SYS_DRM:

			if (PP_STATE_SUPPORT_CG & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_DRM_MGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			if (PP_STATE_SUPPORT_LS & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_DRM_MGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		case PP_BLOCK_SYS_HDP:

			if (PP_STATE_SUPPORT_CG & *msg_id) {

				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_HDP_MGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}



			if (PP_STATE_SUPPORT_LS & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_HDP_MGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		case PP_BLOCK_SYS_SDMA:

			if (PP_STATE_SUPPORT_CG & *msg_id) {

				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_SDMA_MGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}



			if (PP_STATE_SUPPORT_LS & *msg_id) {

				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_SDMA_MGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		case PP_BLOCK_SYS_ROM:

			if (PP_STATE_SUPPORT_CG & *msg_id) {

				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?

						PPSMC_MSG_EnableClockGatingFeature :

						PPSMC_MSG_DisableClockGatingFeature;

				value = CG_SYS_ROM_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr->smumgr, msg, value))

					return -EINVAL;

			}

			break;



		default:

			return -EINVAL;



		}

		break;



	default:

		return -EINVAL;



	}



	return 0;

}



/* This function is for Polaris11 only for now,

 * Powerplay will only control the static per CU Power Gating.

 * Dynamic per CU Power Gating will be done in gfx.

 */

int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)

{

	struct cgs_system_info sys_info = {0};

	uint32_t active_cus;

	int result;



	sys_info.size = sizeof(struct cgs_system_info);

	sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;



	result = cgs_query_system_info(hwmgr->device, &sys_info);



	if (result)

		return -EINVAL;



	active_cus = sys_info.value;



	if (enable)

		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,

				PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);

	else

		return smum_send_msg_to_smc(hwmgr->smumgr,

				PPSMC_MSG_GFX_CU_PG_DISABLE);

}

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h

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+40 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef _SMU7_CLOCK_POWER_GATING_H_

#define _SMU7_CLOCK__POWER_GATING_H_



#include "smu7_hwmgr.h"

#include "pp_asicblocks.h"



int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);

int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);

int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr);

int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);

int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);

int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr);

int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,

					const uint32_t *msg_id);

int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);



#endif

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h

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Original line number Diff line number Diff line 
/*

 * Copyright 2015 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef _SMU7_DYN_DEFAULTS_H

#define _SMU7_DYN_DEFAULTS_H





/*  We need to fill in the default values */





#define SMU7_VOTINGRIGHTSCLIENTS_DFLT0              0x3FFFC102

#define SMU7_VOTINGRIGHTSCLIENTS_DFLT1              0x000400

#define SMU7_VOTINGRIGHTSCLIENTS_DFLT2              0xC00080

#define SMU7_VOTINGRIGHTSCLIENTS_DFLT3              0xC00200

#define SMU7_VOTINGRIGHTSCLIENTS_DFLT4              0xC01680

#define SMU7_VOTINGRIGHTSCLIENTS_DFLT5              0xC00033

#define SMU7_VOTINGRIGHTSCLIENTS_DFLT6              0xC00033

#define SMU7_VOTINGRIGHTSCLIENTS_DFLT7              0x3FFFC000





#define SMU7_THERMALPROTECTCOUNTER_DFLT            0x200

#define SMU7_STATICSCREENTHRESHOLDUNIT_DFLT        0

#define SMU7_STATICSCREENTHRESHOLD_DFLT            0x00C8

#define SMU7_GFXIDLECLOCKSTOPTHRESHOLD_DFLT        0x200

#define SMU7_REFERENCEDIVIDER_DFLT                  4



#define SMU7_ULVVOLTAGECHANGEDELAY_DFLT             1687



#define SMU7_CGULVPARAMETER_DFLT                    0x00040035

#define SMU7_CGULVCONTROL_DFLT                      0x00007450

#define SMU7_TARGETACTIVITY_DFLT                     50

#define SMU7_MCLK_TARGETACTIVITY_DFLT                10



#endif

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

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File added.

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