Loading drivers/net/forcedeth.c +14 −0 Original line number Diff line number Diff line Loading @@ -1435,16 +1435,30 @@ static void nv_mac_reset(struct net_device *dev) { struct fe_priv *np = netdev_priv(dev); u8 __iomem *base = get_hwbase(dev); u32 temp1, temp2, temp3; dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); pci_push(base); /* save registers since they will be cleared on reset */ temp1 = readl(base + NvRegMacAddrA); temp2 = readl(base + NvRegMacAddrB); temp3 = readl(base + NvRegTransmitPoll); writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); pci_push(base); udelay(NV_MAC_RESET_DELAY); writel(0, base + NvRegMacReset); pci_push(base); udelay(NV_MAC_RESET_DELAY); /* restore saved registers */ writel(temp1, base + NvRegMacAddrA); writel(temp2, base + NvRegMacAddrB); writel(temp3, base + NvRegTransmitPoll); writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); pci_push(base); } Loading Loading
drivers/net/forcedeth.c +14 −0 Original line number Diff line number Diff line Loading @@ -1435,16 +1435,30 @@ static void nv_mac_reset(struct net_device *dev) { struct fe_priv *np = netdev_priv(dev); u8 __iomem *base = get_hwbase(dev); u32 temp1, temp2, temp3; dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); pci_push(base); /* save registers since they will be cleared on reset */ temp1 = readl(base + NvRegMacAddrA); temp2 = readl(base + NvRegMacAddrB); temp3 = readl(base + NvRegTransmitPoll); writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); pci_push(base); udelay(NV_MAC_RESET_DELAY); writel(0, base + NvRegMacReset); pci_push(base); udelay(NV_MAC_RESET_DELAY); /* restore saved registers */ writel(temp1, base + NvRegMacAddrA); writel(temp2, base + NvRegMacAddrB); writel(temp3, base + NvRegTransmitPoll); writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); pci_push(base); } Loading