Loading drivers/gpu/drm/nouveau/nv50_display.c +12 −6 Original line number Diff line number Diff line Loading @@ -3940,6 +3940,8 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, asyh->clr.mask, asyh->set.mask); if (crtc_state->active && !asyh->state.active) drm_crtc_vblank_off(crtc); if (asyh->clr.mask) { nv50_head_flush_clr(head, asyh, atom->flush_disable); Loading Loading @@ -4025,12 +4027,14 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) nv50_head_flush_set(head, asyh); interlock_core = 1; } } for_each_crtc_in_state(state, crtc, crtc_state, i) { if (crtc->state->event) if (asyh->state.active) { if (!crtc_state->active) drm_crtc_vblank_on(crtc); if (asyh->state.event) drm_crtc_vblank_get(crtc); } } /* Update plane(s). */ for_each_plane_in_state(state, plane, plane_state, i) { Loading Loading @@ -4076,11 +4080,13 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) if (crtc->state->event) { unsigned long flags; /* Get correct count/ts if racing with vblank irq */ if (crtc->state->active) drm_accurate_vblank_count(crtc); spin_lock_irqsave(&crtc->dev->event_lock, flags); drm_crtc_send_vblank_event(crtc, crtc->state->event); spin_unlock_irqrestore(&crtc->dev->event_lock, flags); crtc->state->event = NULL; if (crtc->state->active) drm_crtc_vblank_put(crtc); } } Loading Loading
drivers/gpu/drm/nouveau/nv50_display.c +12 −6 Original line number Diff line number Diff line Loading @@ -3940,6 +3940,8 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, asyh->clr.mask, asyh->set.mask); if (crtc_state->active && !asyh->state.active) drm_crtc_vblank_off(crtc); if (asyh->clr.mask) { nv50_head_flush_clr(head, asyh, atom->flush_disable); Loading Loading @@ -4025,12 +4027,14 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) nv50_head_flush_set(head, asyh); interlock_core = 1; } } for_each_crtc_in_state(state, crtc, crtc_state, i) { if (crtc->state->event) if (asyh->state.active) { if (!crtc_state->active) drm_crtc_vblank_on(crtc); if (asyh->state.event) drm_crtc_vblank_get(crtc); } } /* Update plane(s). */ for_each_plane_in_state(state, plane, plane_state, i) { Loading Loading @@ -4076,11 +4080,13 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) if (crtc->state->event) { unsigned long flags; /* Get correct count/ts if racing with vblank irq */ if (crtc->state->active) drm_accurate_vblank_count(crtc); spin_lock_irqsave(&crtc->dev->event_lock, flags); drm_crtc_send_vblank_event(crtc, crtc->state->event); spin_unlock_irqrestore(&crtc->dev->event_lock, flags); crtc->state->event = NULL; if (crtc->state->active) drm_crtc_vblank_put(crtc); } } Loading