Commit 43f7071e authored by Rabin Vincent's avatar Rabin Vincent Committed by Jesper Nilsson
Browse files

CRISv32: add irq domains support 



Add support for IRQ domains to the CRISv32 interrupt controller.

Signed-off-by: default avatarRabin Vincent <rabin@rab.in>
Signed-off-by: default avatarJesper Nilsson <jesper.nilsson@axis.com>
parent 8fda64c2

arch/cris/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ config CRIS 
	select OLD_SIGSUSPEND

	select OLD_SIGACTION

	select ARCH_REQUIRE_GPIOLIB

	select IRQ_DOMAIN if ETRAX_ARCH_V32



config HZ

	int

arch/cris/arch-v32/kernel/irq.c

+25 −3
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@ 
#include <linux/errno.h>

#include <linux/init.h>

#include <linux/profile.h>

#include <linux/of.h>

#include <linux/of_irq.h>

#include <linux/proc_fs.h>

#include <linux/seq_file.h>

#include <linux/threads.h>
@@ -431,6 +433,19 @@ crisv32_do_multiple(struct pt_regs* regs) 
	irq_exit();

}



static int crisv32_irq_map(struct irq_domain *h, unsigned int virq,

			   irq_hw_number_t hw_irq_num)

{

	irq_set_chip_and_handler(virq, &crisv32_irq_type, handle_simple_irq);



	return 0;

}



static struct irq_domain_ops crisv32_irq_ops = {

	.map	= crisv32_irq_map,

	.xlate	= irq_domain_xlate_onecell,

};



/*

 * This is called by start_kernel. It fixes the IRQ masks and setup the

 * interrupt vector table to point to bad_interrupt pointers.
@@ -441,6 +456,8 @@ init_IRQ(void) 
	int i;

	int j;

	reg_intr_vect_rw_mask vect_mask = {0};

	struct device_node *np;

	struct irq_domain *domain;



	/* Clear all interrupts masks. */

	for (i = 0; i < NBR_REGS; i++)
@@ -449,10 +466,15 @@ init_IRQ(void) 
	for (i = 0; i < 256; i++)

		etrax_irv->v[i] = weird_irq;



	/* Point all IRQ's to bad handlers. */

	np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc");

	domain = irq_domain_add_legacy(np, NR_IRQS - FIRST_IRQ,

				       FIRST_IRQ, FIRST_IRQ,

				       &crisv32_irq_ops, NULL);

	BUG_ON(!domain);

	irq_set_default_host(domain);

	of_node_put(np);



	for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {

		irq_set_chip_and_handler(j, &crisv32_irq_type,

					 handle_simple_irq);

		set_exception_vector(i, interrupt[j]);

	}