Commit 27b3b22d authored by Gilad Ben-Yossef's avatar Gilad Ben-Yossef Committed by Herbert Xu
Browse files

crypto: ccree - add support for older HW revs 



Add support for the legacy CryptoCell 630 and 710 revs.

Signed-off-by: default avatarGilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 9d3a45ea

drivers/crypto/Kconfig

+3 −3
Original line number Diff line number Diff line
@@ -750,9 +750,9 @@ config CRYPTO_DEV_CCREE 
	select CRYPTO_CTR

	select CRYPTO_XTS

	help

	  Say 'Y' to enable a driver for the Arm TrustZone CryptoCell

	  family of processors. Currently only the CryptoCell 712 REE

	  is supported.

	  Say 'Y' to enable a driver for the REE interface of the Arm

	  TrustZone CryptoCell family of processors. Currently the

	  CryptoCell 712, 710 and 630 are supported.

	  Choose this if you wish to use hardware acceleration of

	  cryptographic operations on the system REE.

	  If unsure say Y.

drivers/crypto/ccree/cc_aead.c

+25 −9
Original line number Diff line number Diff line
@@ -327,7 +327,7 @@ static int hmac_setkey(struct cc_hw_desc *desc, struct cc_aead_ctx *ctx) 
		/* Load the hash current length*/

		hw_desc_init(&desc[idx]);

		set_cipher_mode(&desc[idx], hash_mode);

		set_din_const(&desc[idx], 0, HASH_LEN_SIZE);

		set_din_const(&desc[idx], 0, ctx->drvdata->hash_len_sz);

		set_flow_mode(&desc[idx], S_DIN_to_HASH);

		set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);

		idx++;
@@ -465,7 +465,7 @@ static int cc_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, 
			/* Load the hash current length*/

			hw_desc_init(&desc[idx]);

			set_cipher_mode(&desc[idx], hashmode);

			set_din_const(&desc[idx], 0, HASH_LEN_SIZE);

			set_din_const(&desc[idx], 0, ctx->drvdata->hash_len_sz);

			set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);

			set_flow_mode(&desc[idx], S_DIN_to_HASH);

			set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
@@ -877,7 +877,7 @@ static void cc_proc_digest_desc(struct aead_request *req, 
		set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);

		set_dout_dlli(&desc[idx], req_ctx->icv_dma_addr, ctx->authsize,

			      NS_BIT, 1);

		set_queue_last_ind(&desc[idx]);

		set_queue_last_ind(ctx->drvdata, &desc[idx]);

		if (ctx->auth_mode == DRV_HASH_XCBC_MAC) {

			set_aes_not_hash_mode(&desc[idx]);

			set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
@@ -893,7 +893,7 @@ static void cc_proc_digest_desc(struct aead_request *req, 
		set_flow_mode(&desc[idx], S_HASH_to_DOUT);

		set_dout_dlli(&desc[idx], req_ctx->mac_buf_dma_addr,

			      ctx->authsize, NS_BIT, 1);

		set_queue_last_ind(&desc[idx]);

		set_queue_last_ind(ctx->drvdata, &desc[idx]);

		set_cipher_config0(&desc[idx],

				   HASH_DIGEST_RESULT_LITTLE_ENDIAN);

		set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
@@ -1001,7 +1001,7 @@ static void cc_set_hmac_desc(struct aead_request *req, struct cc_hw_desc desc[], 
	hw_desc_init(&desc[idx]);

	set_cipher_mode(&desc[idx], hash_mode);

	set_din_sram(&desc[idx], cc_digest_len_addr(ctx->drvdata, hash_mode),

		     HASH_LEN_SIZE);

		     ctx->drvdata->hash_len_sz);

	set_flow_mode(&desc[idx], S_DIN_to_HASH);

	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);

	idx++;
@@ -1098,7 +1098,7 @@ static void cc_proc_scheme_desc(struct aead_request *req, 
	hw_desc_init(&desc[idx]);

	set_cipher_mode(&desc[idx], hash_mode);

	set_dout_sram(&desc[idx], aead_handle->sram_workspace_addr,

		      HASH_LEN_SIZE);

		      ctx->drvdata->hash_len_sz);

	set_flow_mode(&desc[idx], S_HASH_to_DOUT);

	set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);

	set_cipher_do(&desc[idx], DO_PAD);
@@ -1128,7 +1128,7 @@ static void cc_proc_scheme_desc(struct aead_request *req, 
	hw_desc_init(&desc[idx]);

	set_cipher_mode(&desc[idx], hash_mode);

	set_din_sram(&desc[idx], cc_digest_len_addr(ctx->drvdata, hash_mode),

		     HASH_LEN_SIZE);

		     ctx->drvdata->hash_len_sz);

	set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);

	set_flow_mode(&desc[idx], S_DIN_to_HASH);

	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
@@ -1509,7 +1509,7 @@ static int cc_ccm(struct aead_request *req, struct cc_hw_desc desc[], 
	set_din_type(&desc[idx], DMA_DLLI, req_ctx->mac_buf_dma_addr,

		     ctx->authsize, NS_BIT);

	set_dout_dlli(&desc[idx], mac_result, ctx->authsize, NS_BIT, 1);

	set_queue_last_ind(&desc[idx]);

	set_queue_last_ind(ctx->drvdata, &desc[idx]);

	set_flow_mode(&desc[idx], DIN_AES_DOUT);

	idx++;
@@ -1772,7 +1772,7 @@ static void cc_proc_gcm_result(struct aead_request *req, 
	set_din_type(&desc[idx], DMA_DLLI, req_ctx->mac_buf_dma_addr,

		     AES_BLOCK_SIZE, NS_BIT);

	set_dout_dlli(&desc[idx], mac_result, ctx->authsize, NS_BIT, 1);

	set_queue_last_ind(&desc[idx]);

	set_queue_last_ind(ctx->drvdata, &desc[idx]);

	set_flow_mode(&desc[idx], DIN_AES_DOUT);

	idx++;
@@ -2358,6 +2358,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_CBC,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_SHA1,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "authenc(hmac(sha1),cbc(des3_ede))",
@@ -2377,6 +2378,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_CBC,

		.flow_mode = S_DIN_to_DES,

		.auth_mode = DRV_HASH_SHA1,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "authenc(hmac(sha256),cbc(aes))",
@@ -2396,6 +2398,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_CBC,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_SHA256,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "authenc(hmac(sha256),cbc(des3_ede))",
@@ -2415,6 +2418,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_CBC,

		.flow_mode = S_DIN_to_DES,

		.auth_mode = DRV_HASH_SHA256,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "authenc(xcbc(aes),cbc(aes))",
@@ -2434,6 +2438,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_CBC,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_XCBC_MAC,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "authenc(hmac(sha1),rfc3686(ctr(aes)))",
@@ -2453,6 +2458,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_CTR,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_SHA1,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "authenc(hmac(sha256),rfc3686(ctr(aes)))",
@@ -2472,6 +2478,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_CTR,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_SHA256,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "authenc(xcbc(aes),rfc3686(ctr(aes)))",
@@ -2491,6 +2498,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_CTR,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_XCBC_MAC,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "ccm(aes)",
@@ -2510,6 +2518,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_CCM,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_NULL,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "rfc4309(ccm(aes))",
@@ -2529,6 +2538,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_CCM,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_NULL,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "gcm(aes)",
@@ -2548,6 +2558,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_GCTR,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_NULL,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "rfc4106(gcm(aes))",
@@ -2567,6 +2578,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_GCTR,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_NULL,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "rfc4543(gcm(aes))",
@@ -2586,6 +2598,7 @@ static struct cc_alg_template aead_algs[] = { 
		.cipher_mode = DRV_CIPHER_GCTR,

		.flow_mode = S_DIN_to_AES,

		.auth_mode = DRV_HASH_NULL,

		.min_hw_rev = CC_HW_REV_630,

	},

};
@@ -2671,6 +2684,9 @@ int cc_aead_alloc(struct cc_drvdata *drvdata) 


	/* Linux crypto */

	for (alg = 0; alg < ARRAY_SIZE(aead_algs); alg++) {

		if (aead_algs[alg].min_hw_rev > drvdata->hw_rev)

			continue;



		t_alg = cc_create_aead_alg(&aead_algs[alg], dev);

		if (IS_ERR(t_alg)) {

			rc = PTR_ERR(t_alg);

drivers/crypto/ccree/cc_cipher.c

+23 −2
Original line number Diff line number Diff line
@@ -502,7 +502,7 @@ static void cc_setup_cipher_data(struct crypto_tfm *tfm, 
		set_dout_dlli(&desc[*seq_size], sg_dma_address(dst),

			      nbytes, NS_BIT, (!areq ? 0 : 1));

		if (areq)

			set_queue_last_ind(&desc[*seq_size]);

			set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);



		set_flow_mode(&desc[*seq_size], flow_mode);

		(*seq_size)++;
@@ -547,7 +547,7 @@ static void cc_setup_cipher_data(struct crypto_tfm *tfm, 
				      (!areq ? 0 : 1));

		}

		if (areq)

			set_queue_last_ind(&desc[*seq_size]);

			set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);



		set_flow_mode(&desc[*seq_size], flow_mode);

		(*seq_size)++;
@@ -748,6 +748,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_XTS,

		.flow_mode = S_DIN_to_AES,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "xts512(aes)",
@@ -764,6 +765,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
		.cipher_mode = DRV_CIPHER_XTS,

		.flow_mode = S_DIN_to_AES,

		.data_unit = 512,

		.min_hw_rev = CC_HW_REV_712,

	},

	{

		.name = "xts4096(aes)",
@@ -780,6 +782,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
		.cipher_mode = DRV_CIPHER_XTS,

		.flow_mode = S_DIN_to_AES,

		.data_unit = 4096,

		.min_hw_rev = CC_HW_REV_712,

	},

	{

		.name = "essiv(aes)",
@@ -795,6 +798,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_ESSIV,

		.flow_mode = S_DIN_to_AES,

		.min_hw_rev = CC_HW_REV_712,

	},

	{

		.name = "essiv512(aes)",
@@ -811,6 +815,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
		.cipher_mode = DRV_CIPHER_ESSIV,

		.flow_mode = S_DIN_to_AES,

		.data_unit = 512,

		.min_hw_rev = CC_HW_REV_712,

	},

	{

		.name = "essiv4096(aes)",
@@ -827,6 +832,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
		.cipher_mode = DRV_CIPHER_ESSIV,

		.flow_mode = S_DIN_to_AES,

		.data_unit = 4096,

		.min_hw_rev = CC_HW_REV_712,

	},

	{

		.name = "bitlocker(aes)",
@@ -842,6 +848,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_BITLOCKER,

		.flow_mode = S_DIN_to_AES,

		.min_hw_rev = CC_HW_REV_712,

	},

	{

		.name = "bitlocker512(aes)",
@@ -858,6 +865,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
		.cipher_mode = DRV_CIPHER_BITLOCKER,

		.flow_mode = S_DIN_to_AES,

		.data_unit = 512,

		.min_hw_rev = CC_HW_REV_712,

	},

	{

		.name = "bitlocker4096(aes)",
@@ -874,6 +882,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
		.cipher_mode = DRV_CIPHER_BITLOCKER,

		.flow_mode = S_DIN_to_AES,

		.data_unit = 4096,

		.min_hw_rev = CC_HW_REV_712,

	},

	{

		.name = "ecb(aes)",
@@ -890,6 +899,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_ECB,

		.flow_mode = S_DIN_to_AES,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "cbc(aes)",
@@ -906,6 +916,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
		},

		.cipher_mode = DRV_CIPHER_CBC,

		.flow_mode = S_DIN_to_AES,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "ofb(aes)",
@@ -922,6 +933,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_OFB,

		.flow_mode = S_DIN_to_AES,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "cts1(cbc(aes))",
@@ -938,6 +950,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_CBC_CTS,

		.flow_mode = S_DIN_to_AES,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "ctr(aes)",
@@ -954,6 +967,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_CTR,

		.flow_mode = S_DIN_to_AES,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "cbc(des3_ede)",
@@ -970,6 +984,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_CBC,

		.flow_mode = S_DIN_to_DES,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "ecb(des3_ede)",
@@ -986,6 +1001,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_ECB,

		.flow_mode = S_DIN_to_DES,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "cbc(des)",
@@ -1002,6 +1018,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_CBC,

		.flow_mode = S_DIN_to_DES,

		.min_hw_rev = CC_HW_REV_630,

	},

	{

		.name = "ecb(des)",
@@ -1018,6 +1035,7 @@ static const struct cc_alg_template skcipher_algs[] = { 
			},

		.cipher_mode = DRV_CIPHER_ECB,

		.flow_mode = S_DIN_to_DES,

		.min_hw_rev = CC_HW_REV_630,

	},

};
@@ -1094,6 +1112,9 @@ int cc_cipher_alloc(struct cc_drvdata *drvdata) 
	dev_dbg(dev, "Number of algorithms = %zu\n",

		ARRAY_SIZE(skcipher_algs));

	for (alg = 0; alg < ARRAY_SIZE(skcipher_algs); alg++) {

		if (skcipher_algs[alg].min_hw_rev > drvdata->hw_rev)

			continue;



		dev_dbg(dev, "creating %s\n", skcipher_algs[alg].driver_name);

		t_alg = cc_create_alg(&skcipher_algs[alg], dev);

		if (IS_ERR(t_alg)) {

drivers/crypto/ccree/cc_crypto_ctx.h

+0 −16
Original line number Diff line number Diff line
@@ -6,17 +6,6 @@ 


#include <linux/types.h>



/* context size */

#ifndef CC_CTX_SIZE_LOG2

#if (CC_DEV_SHA_MAX > 256)

#define CC_CTX_SIZE_LOG2 8

#else

#define CC_CTX_SIZE_LOG2 7

#endif

#endif

#define CC_CTX_SIZE BIT(CC_CTX_SIZE_LOG2)

#define CC_DRV_CTX_SIZE_WORDS (CC_CTX_SIZE >> 2)



#define CC_DRV_DES_IV_SIZE 8

#define CC_DRV_DES_BLOCK_SIZE 8
@@ -59,13 +48,8 @@ 
#define CC_SHA384_BLOCK_SIZE 128

#define CC_SHA512_BLOCK_SIZE 128



#if (CC_DEV_SHA_MAX > 256)

#define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE

#define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/

#else /* Only up to SHA256 */

#define CC_DIGEST_SIZE_MAX CC_SHA256_DIGEST_SIZE

#define CC_HASH_BLOCK_SIZE_MAX CC_SHA256_BLOCK_SIZE /*512b*/

#endif



#define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX

drivers/crypto/ccree/cc_driver.c

+55 −13
Original line number Diff line number Diff line
@@ -35,6 +35,34 @@ bool cc_dump_bytes; 
module_param_named(dump_bytes, cc_dump_bytes, bool, 0600);

MODULE_PARM_DESC(cc_dump_bytes, "Dump buffers to kernel log as debugging aid");



struct cc_hw_data {

	char *name;

	enum cc_hw_rev rev;

	u32 sig;

};



/* Hardware revisions defs. */



static const struct cc_hw_data cc712_hw = {

	.name = "712", .rev = CC_HW_REV_712, .sig =  0xDCC71200U

};



static const struct cc_hw_data cc710_hw = {

	.name = "710", .rev = CC_HW_REV_710, .sig =  0xDCC63200U

};



static const struct cc_hw_data cc630p_hw = {

	.name = "630P", .rev = CC_HW_REV_630, .sig = 0xDCC63000U

};



static const struct of_device_id arm_ccree_dev_of_match[] = {

	{ .compatible = "arm,cryptocell-712-ree", .data = &cc712_hw },

	{ .compatible = "arm,cryptocell-710-ree", .data = &cc710_hw },

	{ .compatible = "arm,cryptocell-630p-ree", .data = &cc630p_hw },

	{}

};

MODULE_DEVICE_TABLE(of, arm_ccree_dev_of_match);



void __dump_byte_array(const char *name, const u8 *buf, size_t len)

{

	char prefix[64];
@@ -128,9 +156,12 @@ int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe) 
	cc_iowrite(drvdata, CC_REG(HOST_ICR), val);



	/* Unmask relevant interrupt cause */

	val = (unsigned int)(~(CC_COMP_IRQ_MASK | CC_AXI_ERR_IRQ_MASK |

			       CC_GPR0_IRQ_MASK));

	cc_iowrite(drvdata, CC_REG(HOST_IMR), val);

	val = CC_COMP_IRQ_MASK | CC_AXI_ERR_IRQ_MASK;



	if (drvdata->hw_rev >= CC_HW_REV_712)

		val |= CC_GPR0_IRQ_MASK;



	cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val);



	cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0);
@@ -157,12 +188,30 @@ static int init_cc_resources(struct platform_device *plat_dev) 
	struct device_node *np = dev->of_node;

	u32 signature_val;

	u64 dma_mask;

	const struct cc_hw_data *hw_rev;

	const struct of_device_id *dev_id;

	int rc = 0;



	new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);

	if (!new_drvdata)

		return -ENOMEM;



	dev_id = of_match_node(arm_ccree_dev_of_match, np);

	if (!dev_id)

		return -ENODEV;



	hw_rev = (struct cc_hw_data *)dev_id->data;

	new_drvdata->hw_rev_name = hw_rev->name;

	new_drvdata->hw_rev = hw_rev->rev;



	if (hw_rev->rev >= CC_HW_REV_712) {

		new_drvdata->hash_len_sz = HASH_LEN_SIZE_712;

		new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);

	} else {

		new_drvdata->hash_len_sz = HASH_LEN_SIZE_630;

		new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);

	}



	platform_set_drvdata(plat_dev, new_drvdata);

	new_drvdata->plat_dev = plat_dev;
@@ -228,9 +277,9 @@ static int init_cc_resources(struct platform_device *plat_dev) 


	/* Verify correct mapping */

	signature_val = cc_ioread(new_drvdata, CC_REG(HOST_SIGNATURE));

	if (signature_val != CC_DEV_SIGNATURE) {

	if (signature_val != hw_rev->sig) {

		dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",

			signature_val, (u32)CC_DEV_SIGNATURE);

			signature_val, hw_rev->sig);

		rc = -EINVAL;

		goto post_clk_err;

	}
@@ -238,8 +287,7 @@ static int init_cc_resources(struct platform_device *plat_dev) 


	/* Display HW versions */

	dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n",

		 CC_DEV_NAME_STR,

		 cc_ioread(new_drvdata, CC_REG(HOST_VERSION)),

		 hw_rev->name, cc_ioread(new_drvdata, CC_REG(HOST_VERSION)),

		 DRV_MODULE_VERSION);



	rc = init_cc_regs(new_drvdata, true);
@@ -430,12 +478,6 @@ static int ccree_remove(struct platform_device *plat_dev) 
	return 0;

}



static const struct of_device_id arm_ccree_dev_of_match[] = {

	{.compatible = "arm,cryptocell-712-ree"},

	{}

};

MODULE_DEVICE_TABLE(of, arm_ccree_dev_of_match);



static struct platform_driver ccree_driver = {

	.driver = {

		   .name = "ccree",