Loading drivers/dma/mmp_tdma.c +29 −1 Original line number Diff line number Diff line Loading @@ -62,6 +62,11 @@ #define TDCR_BURSTSZ_16B (0x3 << 6) #define TDCR_BURSTSZ_32B (0x6 << 6) #define TDCR_BURSTSZ_64B (0x7 << 6) #define TDCR_BURSTSZ_SQU_1B (0x5 << 6) #define TDCR_BURSTSZ_SQU_2B (0x6 << 6) #define TDCR_BURSTSZ_SQU_4B (0x0 << 6) #define TDCR_BURSTSZ_SQU_8B (0x1 << 6) #define TDCR_BURSTSZ_SQU_16B (0x3 << 6) #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) #define TDCR_BURSTSZ_128B (0x5 << 6) #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ Loading Loading @@ -228,8 +233,31 @@ static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac) return -EINVAL; } } else if (tdmac->type == PXA910_SQU) { tdcr |= TDCR_BURSTSZ_SQU_32B; tdcr |= TDCR_SSPMOD; switch (tdmac->burst_sz) { case 1: tdcr |= TDCR_BURSTSZ_SQU_1B; break; case 2: tdcr |= TDCR_BURSTSZ_SQU_2B; break; case 4: tdcr |= TDCR_BURSTSZ_SQU_4B; break; case 8: tdcr |= TDCR_BURSTSZ_SQU_8B; break; case 16: tdcr |= TDCR_BURSTSZ_SQU_16B; break; case 32: tdcr |= TDCR_BURSTSZ_SQU_32B; break; default: dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); return -EINVAL; } } writel(tdcr, tdmac->reg_base + TDCR); Loading Loading
drivers/dma/mmp_tdma.c +29 −1 Original line number Diff line number Diff line Loading @@ -62,6 +62,11 @@ #define TDCR_BURSTSZ_16B (0x3 << 6) #define TDCR_BURSTSZ_32B (0x6 << 6) #define TDCR_BURSTSZ_64B (0x7 << 6) #define TDCR_BURSTSZ_SQU_1B (0x5 << 6) #define TDCR_BURSTSZ_SQU_2B (0x6 << 6) #define TDCR_BURSTSZ_SQU_4B (0x0 << 6) #define TDCR_BURSTSZ_SQU_8B (0x1 << 6) #define TDCR_BURSTSZ_SQU_16B (0x3 << 6) #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) #define TDCR_BURSTSZ_128B (0x5 << 6) #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ Loading Loading @@ -228,8 +233,31 @@ static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac) return -EINVAL; } } else if (tdmac->type == PXA910_SQU) { tdcr |= TDCR_BURSTSZ_SQU_32B; tdcr |= TDCR_SSPMOD; switch (tdmac->burst_sz) { case 1: tdcr |= TDCR_BURSTSZ_SQU_1B; break; case 2: tdcr |= TDCR_BURSTSZ_SQU_2B; break; case 4: tdcr |= TDCR_BURSTSZ_SQU_4B; break; case 8: tdcr |= TDCR_BURSTSZ_SQU_8B; break; case 16: tdcr |= TDCR_BURSTSZ_SQU_16B; break; case 32: tdcr |= TDCR_BURSTSZ_SQU_32B; break; default: dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); return -EINVAL; } } writel(tdcr, tdmac->reg_base + TDCR); Loading