diff --git a/CREDITS b/CREDITS index 2ef5dceef32455ae6afac5d74db1000912fd0b9f..ec7e6c7fdd1b9c93342d808d1c65d8807e63312f 100644 --- a/CREDITS +++ b/CREDITS @@ -2049,6 +2049,10 @@ D: pirq addr, CS5535 alsa audio driver S: Gurgaon, India S: Kuala Lumpur, Malaysia +N: Mohit Kumar +D: ST Microelectronics SPEAr13xx PCI host bridge driver +D: Synopsys Designware PCI host bridge driver + N: Gabor Kuti M: seasons@falcon.sch.bme.hu M: seasons@makosteszta.sote.hu @@ -3705,6 +3709,13 @@ N: Dirk Verworner D: Co-author of German book ``Linux-Kernel-Programmierung'' D: Co-founder of Berlin Linux User Group +N: Andrew Victor +E: linux@maxim.org.za +W: http://maxim.org.za/at91_26.html +D: First maintainer of Atmel ARM-based SoC, aka AT91 +D: Introduced support for at91rm9200, the first chip of AT91 family +S: South Africa + N: Riku Voipio E: riku.voipio@iki.fi D: Author of PCA9532 LED and Fintek f75375s hwmon driver diff --git a/Documentation/ABI/testing/sysfs-block-dm b/Documentation/ABI/testing/sysfs-block-dm index 87ca5691e29b1d92726e01bbe5296cde6932d08d..f9f2339b9a0a88e485d91bae022b1e6a3d213f07 100644 --- a/Documentation/ABI/testing/sysfs-block-dm +++ b/Documentation/ABI/testing/sysfs-block-dm @@ -23,3 +23,25 @@ Description: Device-mapper device suspend state. Contains the value 1 while the device is suspended. Otherwise it contains 0. Read-only attribute. Users: util-linux, device-mapper udev rules + +What: /sys/block/dm-/dm/rq_based_seq_io_merge_deadline +Date: March 2015 +KernelVersion: 4.1 +Contact: dm-devel@redhat.com +Description: Allow control over how long a request that is a + reasonable merge candidate can be queued on the request + queue. The resolution of this deadline is in + microseconds (ranging from 1 to 100000 usecs). + Setting this attribute to 0 (the default) will disable + request-based DM's merge heuristic and associated extra + accounting. This attribute is not applicable to + bio-based DM devices so it will only ever report 0 for + them. + +What: /sys/block/dm-/dm/use_blk_mq +Date: March 2015 +KernelVersion: 4.1 +Contact: dm-devel@redhat.com +Description: Request-based Device-mapper blk-mq I/O path mode. + Contains the value 1 if the device is using blk-mq. + Otherwise it contains 0. Read-only attribute. diff --git a/Documentation/ABI/testing/sysfs-bus-pci-drivers-janz-cmodio b/Documentation/ABI/testing/sysfs-bus-pci-drivers-janz-cmodio new file mode 100644 index 0000000000000000000000000000000000000000..4d08f28dc871d0dea7a50feae167269cd5b70112 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-pci-drivers-janz-cmodio @@ -0,0 +1,8 @@ +What: /sys/bus/pci/drivers/janz-cmodio/.../modulbus_number +Date: May 2010 +KernelVersion: 2.6.35 +Contact: Ira W. Snyder +Description: + Value representing the HEX switch S2 of the janz carrier board CMOD-IO or CAN-PCI2 + + Read-only: value of the configuration switch (0..15) diff --git a/Documentation/ABI/testing/sysfs-class-mtd b/Documentation/ABI/testing/sysfs-class-mtd index 76ee192f80a080b12f319d2e6624f38606f4efa7..3b5c3bca9186d13e8cf5f1911b2fc88424c6970f 100644 --- a/Documentation/ABI/testing/sysfs-class-mtd +++ b/Documentation/ABI/testing/sysfs-class-mtd @@ -222,3 +222,13 @@ Description: The number of blocks that are marked as reserved, if any, in this partition. These are typically used to store the in-flash bad block table (BBT). + +What: /sys/class/mtd/mtdX/offset +Date: March 2015 +KernelVersion: 4.1 +Contact: linux-mtd@lists.infradead.org +Description: + For a partition, the offset of that partition from the start + of the master device in bytes. This attribute is absent on + main devices, so it can be used to distinguish between + partitions and devices that aren't partitions. diff --git a/Documentation/ABI/testing/sysfs-class-net b/Documentation/ABI/testing/sysfs-class-net index 5ecfd72ba684c35acce51273d4370258b147ffb8..668604fc8e062bc7d7d4fc363aec6db48b00d6e8 100644 --- a/Documentation/ABI/testing/sysfs-class-net +++ b/Documentation/ABI/testing/sysfs-class-net @@ -39,6 +39,25 @@ Description: Format is a string, e.g: 00:11:22:33:44:55 for an Ethernet MAC address. +What: /sys/class/net//bridge/group_fwd_mask +Date: January 2012 +KernelVersion: 3.2 +Contact: netdev@vger.kernel.org +Description: + Bitmask to allow forwarding of link local frames with address + 01-80-C2-00-00-0X on a bridge device. Only values that set bits + not matching BR_GROUPFWD_RESTRICTED in net/bridge/br_private.h + allowed. + Default value 0 does not forward any link local frames. + + Restricted bits: + 0: 01-80-C2-00-00-00 Bridge Group Address used for STP + 1: 01-80-C2-00-00-01 (MAC Control) 802.3 used for MAC PAUSE + 2: 01-80-C2-00-00-02 (Link Aggregation) 802.3ad + + Any values not setting these bits can be used. Take special + care when forwarding control frames e.g. 802.1X-PAE or LLDP. + What: /sys/class/net//broadcast Date: April 2005 KernelVersion: 2.6.12 diff --git a/Documentation/ABI/testing/sysfs-class-net-janz-ican3 b/Documentation/ABI/testing/sysfs-class-net-janz-ican3 new file mode 100644 index 0000000000000000000000000000000000000000..fdbc03a2b8f873e6bd476ac5aa6b132c65bb8aef --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-net-janz-ican3 @@ -0,0 +1,19 @@ +What: /sys/class/net//termination +Date: May 2010 +KernelVersion: 2.6.35 +Contact: Ira W. Snyder +Description: + Value representing the can bus termination + + Default: 1 (termination active) + Reading: get actual termination state + Writing: set actual termination state (0=no termination, 1=termination active) + +What: /sys/class/net//fwinfo +Date: May 2015 +KernelVersion: 3.19 +Contact: Andreas Gröger +Description: + Firmware stamp of ican3 module + Read-only: 32 byte string identification of the ICAN3 module + (known values: "JANZ-ICAN3 ICANOS 1.xx", "JANZ-ICAN3 CAL/CANopen 1.xx") diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index 99983e67c13c9f6aadff74c1969a4d27cede7d26..da95513571ea3e3e53263f6c91588fb58d50f3fb 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -162,7 +162,7 @@ Description: Discover CPUs in the same CPU frequency coordination domain What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1} Date: August 2008 KernelVersion: 2.6.27 -Contact: discuss@x86-64.org +Contact: Linux kernel mailing list Description: Disable L3 cache indices These files exist in every CPU's cache/index3 directory. Each diff --git a/Documentation/ABI/testing/sysfs-driver-toshiba_acpi b/Documentation/ABI/testing/sysfs-driver-toshiba_acpi index ca9c71a531c5f86c1ca281f6e9ca5d2129da0c8a..eed922ef42e533ae9bf16da6d224a50d2b46e16b 100644 --- a/Documentation/ABI/testing/sysfs-driver-toshiba_acpi +++ b/Documentation/ABI/testing/sysfs-driver-toshiba_acpi @@ -8,9 +8,11 @@ Description: This file controls the keyboard backlight operation mode, valid * 0x2 -> AUTO (also called TIMER) * 0x8 -> ON * 0x10 -> OFF - Note that the kernel 3.16 onwards this file accepts all listed + Note that from kernel 3.16 onwards this file accepts all listed parameters, kernel 3.15 only accepts the first two (FN-Z and AUTO). + Also note that toggling this value on type 1 devices, requires + a reboot for changes to take effect. Users: KToshiba What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/kbd_backlight_timeout @@ -67,15 +69,72 @@ Description: This file shows the current keyboard backlight type, * 2 -> Type 2, supporting modes TIMER, ON and OFF Users: KToshiba +What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/usb_sleep_charge +Date: January 23, 2015 +KernelVersion: 4.0 +Contact: Azael Avalos +Description: This file controls the USB Sleep & Charge charging mode, which + can be: + * 0 -> Disabled (0x00) + * 1 -> Alternate (0x09) + * 2 -> Auto (0x21) + * 3 -> Typical (0x11) + Note that from kernel 4.1 onwards this file accepts all listed + values, kernel 4.0 only supports the first three. + Note that this feature only works when connected to power, if + you want to use it under battery, see the entry named + "sleep_functions_on_battery" +Users: KToshiba + +What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/sleep_functions_on_battery +Date: January 23, 2015 +KernelVersion: 4.0 +Contact: Azael Avalos +Description: This file controls the USB Sleep Functions under battery, and + set the level at which point they will be disabled, accepted + values can be: + * 0 -> Disabled + * 1-100 -> Battery level to disable sleep functions + Currently it prints two values, the first one indicates if the + feature is enabled or disabled, while the second one shows the + current battery level set. + Note that when the value is set to disabled, the sleep function + will only work when connected to power. +Users: KToshiba + +What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/usb_rapid_charge +Date: January 23, 2015 +KernelVersion: 4.0 +Contact: Azael Avalos +Description: This file controls the USB Rapid Charge state, which can be: + * 0 -> Disabled + * 1 -> Enabled + Note that toggling this value requires a reboot for changes to + take effect. +Users: KToshiba + +What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/usb_sleep_music +Date: January 23, 2015 +KernelVersion: 4.0 +Contact: Azael Avalos +Description: This file controls the Sleep & Music state, which values can be: + * 0 -> Disabled + * 1 -> Enabled + Note that this feature only works when connected to power, if + you want to use it under battery, see the entry named + "sleep_functions_on_battery" +Users: KToshiba + What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/version -Date: February, 2015 -KernelVersion: 3.20 +Date: February 12, 2015 +KernelVersion: 4.0 Contact: Azael Avalos Description: This file shows the current version of the driver +Users: KToshiba What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/fan -Date: February, 2015 -KernelVersion: 3.20 +Date: February 12, 2015 +KernelVersion: 4.0 Contact: Azael Avalos Description: This file controls the state of the internal fan, valid values are: @@ -83,8 +142,8 @@ Description: This file controls the state of the internal fan, valid * 1 -> ON What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/kbd_function_keys -Date: February, 2015 -KernelVersion: 3.20 +Date: February 12, 2015 +KernelVersion: 4.0 Contact: Azael Avalos Description: This file controls the Special Functions (hotkeys) operation mode, valid values are: @@ -94,21 +153,29 @@ Description: This file controls the Special Functions (hotkeys) operation and the hotkeys are accessed via FN-F{1-12}. In the "Special Functions" mode, the F{1-12} keys trigger the hotkey and the F{1-12} keys are accessed via FN-F{1-12}. + Note that toggling this value requires a reboot for changes to + take effect. +Users: KToshiba What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/panel_power_on -Date: February, 2015 -KernelVersion: 3.20 +Date: February 12, 2015 +KernelVersion: 4.0 Contact: Azael Avalos Description: This file controls whether the laptop should turn ON whenever the LID is opened, valid values are: * 0 -> Disabled * 1 -> Enabled + Note that toggling this value requires a reboot for changes to + take effect. +Users: KToshiba What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/usb_three -Date: February, 2015 -KernelVersion: 3.20 +Date: February 12, 2015 +KernelVersion: 4.0 Contact: Azael Avalos -Description: This file controls whether the USB 3 functionality, valid - values are: +Description: This file controls the USB 3 functionality, valid values are: * 0 -> Disabled (Acts as a regular USB 2) * 1 -> Enabled (Full USB 3 functionality) + Note that toggling this value requires a reboot for changes to + take effect. +Users: KToshiba diff --git a/Documentation/ABI/testing/sysfs-platform-dell-laptop b/Documentation/ABI/testing/sysfs-platform-dell-laptop new file mode 100644 index 0000000000000000000000000000000000000000..8c6a0b8e113133c127b1505c61e09ff1d347d551 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-dell-laptop @@ -0,0 +1,69 @@ +What: /sys/class/leds/dell::kbd_backlight/als_enabled +Date: December 2014 +KernelVersion: 3.19 +Contact: Gabriele Mazzotta , + Pali Rohár +Description: + This file allows to control the automatic keyboard + illumination mode on some systems that have an ambient + light sensor. Write 1 to this file to enable the auto + mode, 0 to disable it. + +What: /sys/class/leds/dell::kbd_backlight/als_setting +Date: December 2014 +KernelVersion: 3.19 +Contact: Gabriele Mazzotta , + Pali Rohár +Description: + This file allows to specifiy the on/off threshold value, + as reported by the ambient light sensor. + +What: /sys/class/leds/dell::kbd_backlight/start_triggers +Date: December 2014 +KernelVersion: 3.19 +Contact: Gabriele Mazzotta , + Pali Rohár +Description: + This file allows to control the input triggers that + turn on the keyboard backlight illumination that is + disabled because of inactivity. + Read the file to see the triggers available. The ones + enabled are preceded by '+', those disabled by '-'. + + To enable a trigger, write its name preceded by '+' to + this file. To disable a trigger, write its name preceded + by '-' instead. + + For example, to enable the keyboard as trigger run: + echo +keyboard > /sys/class/leds/dell::kbd_backlight/start_triggers + To disable it: + echo -keyboard > /sys/class/leds/dell::kbd_backlight/start_triggers + + Note that not all the available triggers can be configured. + +What: /sys/class/leds/dell::kbd_backlight/stop_timeout +Date: December 2014 +KernelVersion: 3.19 +Contact: Gabriele Mazzotta , + Pali Rohár +Description: + This file allows to specify the interval after which the + keyboard illumination is disabled because of inactivity. + The timeouts are expressed in seconds, minutes, hours and + days, for which the symbols are 's', 'm', 'h' and 'd' + respectively. + + To configure the timeout, write to this file a value along + with any the above units. If no unit is specified, the value + is assumed to be expressed in seconds. + + For example, to set the timeout to 10 minutes run: + echo 10m > /sys/class/leds/dell::kbd_backlight/stop_timeout + + Note that when this file is read, the returned value might be + expressed in a different unit than the one used when the timeout + was set. + + Also note that only some timeouts are supported and that + some systems might fall back to a specific timeout in case + an invalid timeout is written to this file. diff --git a/Documentation/CodingStyle b/Documentation/CodingStyle index 4d4f06d47e0620325016bbda0af537995a8bfead..f4b78eafd92a2e76e439f168fff97e1d41374b59 100644 --- a/Documentation/CodingStyle +++ b/Documentation/CodingStyle @@ -13,7 +13,7 @@ and NOT read it. Burn them, it's a great symbolic gesture. Anyway, here goes: - Chapter 1: Indentation + Chapter 1: Indentation Tabs are 8 characters, and thus indentations are also 8 characters. There are heretic movements that try to make indentations 4 (or even 2!) @@ -56,7 +56,6 @@ instead of "double-indenting" the "case" labels. E.g.: break; } - Don't put multiple statements on a single line unless you have something to hide: @@ -156,25 +155,25 @@ comments on. Do not unnecessarily use braces where a single statement will do. -if (condition) - action(); + if (condition) + action(); and -if (condition) - do_this(); -else - do_that(); + if (condition) + do_this(); + else + do_that(); This does not apply if only one branch of a conditional statement is a single statement; in the latter case use braces in both branches: -if (condition) { - do_this(); - do_that(); -} else { - otherwise(); -} + if (condition) { + do_this(); + do_that(); + } else { + otherwise(); + } 3.1: Spaces @@ -186,8 +185,11 @@ although they are not required in the language, as in: "sizeof info" after "struct fileinfo info;" is declared). So use a space after these keywords: + if, switch, case, for, do, while + but not with sizeof, typeof, alignof, or __attribute__. E.g., + s = sizeof(struct file); Do not add spaces around (inside) parenthesized expressions. This example is @@ -209,12 +211,15 @@ such as any of these: = + - < > * / % | & ^ <= >= == != ? : but no space after unary operators: + & * + - ~ ! sizeof typeof alignof __attribute__ defined no space before the postfix increment & decrement unary operators: + ++ -- no space after the prefix increment & decrement unary operators: + ++ -- and no space around the '.' and "->" structure member operators. @@ -268,13 +273,11 @@ See chapter 6 (Functions). Chapter 5: Typedefs Please don't use things like "vps_t". - It's a _mistake_ to use typedef for structures and pointers. When you see a vps_t a; in the source, what does it mean? - In contrast, if it says struct virtual_container *a; @@ -372,11 +375,11 @@ In source files, separate functions with one blank line. If the function is exported, the EXPORT* macro for it should follow immediately after the closing function brace line. E.g.: -int system_is_up(void) -{ - return system_state == SYSTEM_RUNNING; -} -EXPORT_SYMBOL(system_is_up); + int system_is_up(void) + { + return system_state == SYSTEM_RUNNING; + } + EXPORT_SYMBOL(system_is_up); In function prototypes, include parameter names with their data types. Although this is not required by the C language, it is preferred in Linux @@ -405,34 +408,34 @@ The rationale for using gotos is: modifications are prevented - saves the compiler work to optimize redundant code away ;) -int fun(int a) -{ - int result = 0; - char *buffer; - - buffer = kmalloc(SIZE, GFP_KERNEL); - if (!buffer) - return -ENOMEM; - - if (condition1) { - while (loop1) { - ... + int fun(int a) + { + int result = 0; + char *buffer; + + buffer = kmalloc(SIZE, GFP_KERNEL); + if (!buffer) + return -ENOMEM; + + if (condition1) { + while (loop1) { + ... + } + result = 1; + goto out_buffer; } - result = 1; - goto out_buffer; + ... + out_buffer: + kfree(buffer); + return result; } - ... -out_buffer: - kfree(buffer); - return result; -} A common type of bug to be aware of it "one err bugs" which look like this: -err: - kfree(foo->bar); - kfree(foo); - return ret; + err: + kfree(foo->bar); + kfree(foo); + return ret; The bug in this code is that on some exit paths "foo" is NULL. Normally the fix for this is to split it up into two error labels "err_bar:" and "err_foo:". @@ -503,9 +506,9 @@ values. To do the latter, you can stick the following in your .emacs file: (defun c-lineup-arglist-tabs-only (ignored) "Line up argument lists by tabs, not spaces" (let* ((anchor (c-langelem-pos c-syntactic-element)) - (column (c-langelem-2nd-pos c-syntactic-element)) - (offset (- (1+ column) anchor)) - (steps (floor offset c-basic-offset))) + (column (c-langelem-2nd-pos c-syntactic-element)) + (offset (- (1+ column) anchor)) + (steps (floor offset c-basic-offset))) (* (max steps 1) c-basic-offset))) @@ -612,7 +615,7 @@ have a reference count on it, you almost certainly have a bug. Names of macros defining constants and labels in enums are capitalized. -#define CONSTANT 0x12345 + #define CONSTANT 0x12345 Enums are preferred when defining several related constants. @@ -623,28 +626,28 @@ Generally, inline functions are preferable to macros resembling functions. Macros with multiple statements should be enclosed in a do - while block: -#define macrofun(a, b, c) \ - do { \ - if (a == 5) \ - do_this(b, c); \ - } while (0) + #define macrofun(a, b, c) \ + do { \ + if (a == 5) \ + do_this(b, c); \ + } while (0) Things to avoid when using macros: 1) macros that affect control flow: -#define FOO(x) \ - do { \ - if (blah(x) < 0) \ - return -EBUGGERED; \ - } while(0) + #define FOO(x) \ + do { \ + if (blah(x) < 0) \ + return -EBUGGERED; \ + } while(0) is a _very_ bad idea. It looks like a function call but exits the "calling" function; don't break the internal parsers of those who will read the code. 2) macros that depend on having a local variable with a magic name: -#define FOO(val) bar(index, val) + #define FOO(val) bar(index, val) might look like a good thing, but it's confusing as hell when one reads the code and it's prone to breakage from seemingly innocent changes. @@ -656,8 +659,8 @@ bite you if somebody e.g. turns FOO into an inline function. must enclose the expression in parentheses. Beware of similar issues with macros using parameters. -#define CONSTANT 0x4000 -#define CONSTEXP (CONSTANT | 3) + #define CONSTANT 0x4000 + #define CONSTEXP (CONSTANT | 3) 5) namespace collisions when defining local variables in macros resembling functions: @@ -809,11 +812,11 @@ you should use, rather than explicitly coding some variant of them yourself. For example, if you need to calculate the length of an array, take advantage of the macro - #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) Similarly, if you need to calculate the size of some structure member, use - #define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f)) + #define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f)) There are also min() and max() macros that do strict type checking if you need them. Feel free to peruse that header file to see what else is already @@ -826,19 +829,19 @@ Some editors can interpret configuration information embedded in source files, indicated with special markers. For example, emacs interprets lines marked like this: --*- mode: c -*- + -*- mode: c -*- Or like this: -/* -Local Variables: -compile-command: "gcc -DMAGIC_DEBUG_FLAG foo.c" -End: -*/ + /* + Local Variables: + compile-command: "gcc -DMAGIC_DEBUG_FLAG foo.c" + End: + */ Vim interprets markers that look like this: -/* vim:set sw=8 noet */ + /* vim:set sw=8 noet */ Do not include any of these in source files. People have their own personal editor configurations, and your source files should not override them. This @@ -915,9 +918,9 @@ At the end of any non-trivial #if or #ifdef block (more than a few lines), place a comment after the #endif on the same line, noting the conditional expression used. For instance: -#ifdef CONFIG_SOMETHING -... -#endif /* CONFIG_SOMETHING */ + #ifdef CONFIG_SOMETHING + ... + #endif /* CONFIG_SOMETHING */ Appendix I: References diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 03f1985a4bd1876d7b3e78d70b0c6939ef709eab..9765a4c0829df4307efaf773d8b887b35270ad31 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -1293,7 +1293,7 @@ int max_width, max_height; If a page flip can be successfully scheduled the driver must set the - drm_crtc-<fb field to the new framebuffer pointed to + drm_crtc->fb field to the new framebuffer pointed to by fb. This is important so that the reference counting on framebuffers stays balanced. @@ -3979,6 +3979,11 @@ int num_ioctls; !Fdrivers/gpu/drm/i915/i915_irq.c intel_runtime_pm_disable_interrupts !Fdrivers/gpu/drm/i915/i915_irq.c intel_runtime_pm_enable_interrupts + + Intel GVT-g Guest Support(vGPU) +!Pdrivers/gpu/drm/i915/i915_vgpu.c Intel GVT-g guest support +!Idrivers/gpu/drm/i915/i915_vgpu.c + Display Hardware Handling @@ -4046,6 +4051,17 @@ int num_ioctls; Frame Buffer Compression (FBC) !Pdrivers/gpu/drm/i915/intel_fbc.c Frame Buffer Compression (FBC) !Idrivers/gpu/drm/i915/intel_fbc.c + + + Display Refresh Rate Switching (DRRS) +!Pdrivers/gpu/drm/i915/intel_dp.c Display Refresh Rate Switching (DRRS) +!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_set_drrs_state +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_enable +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_disable +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_invalidate +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_flush +!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_drrs_init + DPIO @@ -4168,7 +4184,7 @@ int num_ioctls; Buffer Object Eviction - This section documents the interface function for evicting buffer + This section documents the interface functions for evicting buffer objects to make space available in the virtual gpu address spaces. Note that this is mostly orthogonal to shrinking buffer objects caches, which has the goal to make main memory (shared with the gpu @@ -4176,6 +4192,17 @@ int num_ioctls; !Idrivers/gpu/drm/i915/i915_gem_evict.c + + Buffer Object Memory Shrinking + + This section documents the interface function for shrinking memory + usage of buffer object caches. Shrinking is used to make main memory + available. Note that this is mostly orthogonal to evicting buffer + objects, which has the goal to make space in gpu virtual address + spaces. + +!Idrivers/gpu/drm/i915/i915_gem_shrinker.c + diff --git a/Documentation/DocBook/media/v4l/biblio.xml b/Documentation/DocBook/media/v4l/biblio.xml index 7ff01a23c2fe4835d848d6353e8bb78d66dc56eb..fdee6b3f3ecaaaabbbf7d3cd5b62cd8b3d1be257 100644 --- a/Documentation/DocBook/media/v4l/biblio.xml +++ b/Documentation/DocBook/media/v4l/biblio.xml @@ -1,14 +1,13 @@ References - - EIA 608-B + + CEA 608-E - Electronic Industries Alliance (http://www.eia.org) + Consumer Electronics Association (http://www.ce.org) - EIA 608-B "Recommended Practice for Line 21 Data -Service" + CEA-608-E R-2014 "Line 21 Data Services" diff --git a/Documentation/DocBook/media/v4l/compat.xml b/Documentation/DocBook/media/v4l/compat.xml index 350dfb3d71ea736aeeb379dcb69256b561c8a734..a0aef85d33c1f94041d46bd7f48db037385522cc 100644 --- a/Documentation/DocBook/media/v4l/compat.xml +++ b/Documentation/DocBook/media/v4l/compat.xml @@ -2491,7 +2491,7 @@ that used it. It was originally scheduled for removal in 2.6.35. Added V4L2_EVENT_CTRL_CH_RANGE control event - changes flag. See . + changes flag. See . diff --git a/Documentation/DocBook/media/v4l/dev-sliced-vbi.xml b/Documentation/DocBook/media/v4l/dev-sliced-vbi.xml index 7a8bf3011ee999861b3c338f1b47316052f99a85..0aec62ed2bf8e1a00e40b8025316c1fac00b6613 100644 --- a/Documentation/DocBook/media/v4l/dev-sliced-vbi.xml +++ b/Documentation/DocBook/media/v4l/dev-sliced-vbi.xml @@ -254,7 +254,7 @@ ETS 300 231, lsb first transmitted. V4L2_SLICED_CAPTION_525 0x1000 - + NTSC line 21, 284 (second field 21) Two bytes in transmission order, including parity bit, lsb first transmitted. diff --git a/Documentation/DocBook/media/v4l/media-ioc-enum-entities.xml b/Documentation/DocBook/media/v4l/media-ioc-enum-entities.xml index 116c301656e0bde1732c2e0dbe124cc68285ad8d..5872f8bbf7747efb848daf103b3d70271b18e1c6 100644 --- a/Documentation/DocBook/media/v4l/media-ioc-enum-entities.xml +++ b/Documentation/DocBook/media/v4l/media-ioc-enum-entities.xml @@ -143,86 +143,28 @@ struct - v4l + dev - Valid for V4L sub-devices and nodes only. + Valid for (sub-)devices that create a single device node. __u32 major - V4L device node major number. For V4L sub-devices with no - device node, set by the driver to 0. + Device node major number. __u32 minor - V4L device node minor number. For V4L sub-devices with no - device node, set by the driver to 0. - - - - struct - fb - - Valid for frame buffer nodes only. - - - - - __u32 - major - Frame buffer device node major number. - - - - - __u32 - minor - Frame buffer device node minor number. - - - - struct - alsa - - Valid for ALSA devices only. - - - - - __u32 - card - ALSA card number - - - - - __u32 - device - ALSA device number - - - - - __u32 - subdevice - ALSA sub-device number - - - - int - dvb - - DVB card number + Device node minor number. __u8 - raw[180] + raw[184] @@ -253,8 +195,24 @@ ALSA card - MEDIA_ENT_T_DEVNODE_DVB - DVB card + MEDIA_ENT_T_DEVNODE_DVB_FE + DVB frontend devnode + + + MEDIA_ENT_T_DEVNODE_DVB_DEMUX + DVB demux devnode + + + MEDIA_ENT_T_DEVNODE_DVB_DVR + DVB DVR devnode + + + MEDIA_ENT_T_DEVNODE_DVB_CA + DVB CAM devnode + + + MEDIA_ENT_T_DEVNODE_DVB_NET + DVB network devnode MEDIA_ENT_T_V4L2_SUBDEV @@ -282,6 +240,10 @@ it in some digital video standard, with appropriate embedded timing signals. + + MEDIA_ENT_T_V4L2_SUBDEV_TUNER + TV and/or radio tuner + diff --git a/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml b/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml index 6ab4f0f3db64abdc9de76ff3ccf458881f9b49e2..b60fb935b91b8b9282344fd5b17a3650ce150800 100644 --- a/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml +++ b/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml @@ -303,45 +303,6 @@ for a pixel lie next to each other in memory. b1 b0 - - V4L2_PIX_FMT_BGR666 - 'BGRH' - - b5 - b4 - b3 - b2 - b1 - b0 - g5 - g4 - - g3 - g2 - g1 - g0 - r5 - r4 - r3 - r2 - - r1 - r0 - - - - - - - - - - - - - - - V4L2_PIX_FMT_BGR24 'BGR3' @@ -404,6 +365,46 @@ for a pixel lie next to each other in memory. b1 b0 + + V4L2_PIX_FMT_BGR666 + 'BGRH' + + b5 + b4 + b3 + b2 + b1 + b0 + g5 + g4 + + g3 + g2 + g1 + g0 + r5 + r4 + r3 + r2 + + r1 + r0 + - + - + - + - + - + - + + - + - + - + - + - + - + - + - + V4L2_PIX_FMT_ABGR32 'AR24' diff --git a/Documentation/DocBook/media/v4l/pixfmt-sgrbg8.xml b/Documentation/DocBook/media/v4l/pixfmt-sgrbg8.xml index 19727ab4c75752035bc59c89b693a0a3242c95cf..7803b8c41b45d2ffd2000d91abf8152886dd2654 100644 --- a/Documentation/DocBook/media/v4l/pixfmt-sgrbg8.xml +++ b/Documentation/DocBook/media/v4l/pixfmt-sgrbg8.xml @@ -38,10 +38,10 @@ columns and rows. start + 4: - R10 - B11 - R12 - B13 + B10 + G11 + B12 + G13 start + 8: @@ -52,10 +52,10 @@ columns and rows. start + 12: - R30 - B31 - R32 - B33 + B30 + G31 + B32 + G33 diff --git a/Documentation/DocBook/media/v4l/pixfmt-srggb10p.xml b/Documentation/DocBook/media/v4l/pixfmt-srggb10p.xml index 30aa63581fe33d224f060acab75f9faef3b10c3e..a8cc102cde4fc3e5b446822cfb66f5493523ef38 100644 --- a/Documentation/DocBook/media/v4l/pixfmt-srggb10p.xml +++ b/Documentation/DocBook/media/v4l/pixfmt-srggb10p.xml @@ -38,7 +38,7 @@ Byte Order. Each cell is one byte. - + diff --git a/Documentation/DocBook/media/v4l/pixfmt-yuv420m.xml b/Documentation/DocBook/media/v4l/pixfmt-yuv420m.xml index 60308f1eefdfea59a33d83f30d32747c8f5c1aa4..e781cc61786c52b93f3f2973110f6040c56dac0e 100644 --- a/Documentation/DocBook/media/v4l/pixfmt-yuv420m.xml +++ b/Documentation/DocBook/media/v4l/pixfmt-yuv420m.xml @@ -29,12 +29,12 @@ and Cr planes have half as many pad bytes after their rows. In other words, two Cx rows (including padding) is exactly as long as one Y row (including padding). - V4L2_PIX_FMT_NV12M is intended to be + V4L2_PIX_FMT_YUV420M is intended to be used only in drivers and applications that support the multi-planar API, described in . - <constant>V4L2_PIX_FMT_YVU420M</constant> 4 × 4 + <title><constant>V4L2_PIX_FMT_YUV420M</constant> 4 × 4 pixel image diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml index 5e0352c5032414bf7e89ed34ed4c1b875998798d..fcde4e20205e18885419176491f0fec863e87dfd 100644 --- a/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/Documentation/DocBook/media/v4l/pixfmt.xml @@ -80,9 +80,9 @@ padding bytes after the last line of an image cross a system page boundary. Input devices may write padding bytes, the value is undefined. Output devices ignore the contents of padding bytes.When the image format is planar the -bytesperline value applies to the largest +bytesperline value applies to the first plane and is divided by the same factor as the -width field for any smaller planes. For +width field for the other planes. For example the Cb and Cr planes of a YUV 4:2:0 image have half as many padding bytes following each line as the Y plane. To avoid ambiguities drivers must return a bytesperline value @@ -182,14 +182,14 @@ see . - __u16 + __u32 bytesperline Distance in bytes between the leftmost pixels in two adjacent lines. See &v4l2-pix-format;. __u16 - reserved[7] + reserved[6] Reserved for future extensions. Should be zeroed by the application. @@ -483,8 +483,8 @@ is the Y'CbCr encoding identifier (&v4l2-ycbcr-encoding;) to specify non-standar Y'CbCr encodings and the third is the quantization identifier (&v4l2-quantization;) to specify non-standard quantization methods. Most of the time only the colorspace field of &v4l2-pix-format; or &v4l2-pix-format-mplane; needs to be filled in. Note -that the default R'G'B' quantization is always full range for all colorspaces, -so this won't be mentioned explicitly for each colorspace description. +that the default R'G'B' quantization is full range for all colorspaces except for +BT.2020 which uses limited range R'G'B' quantization. V4L2 Colorspaces @@ -598,7 +598,8 @@ so this won't be mentioned explicitly for each colorspace description. V4L2_QUANTIZATION_DEFAULT Use the default quantization encoding as defined by the colorspace. -This is always full range for R'G'B' and usually limited range for Y'CbCr. +This is always full range for R'G'B' (except for the BT.2020 colorspace) and usually +limited range for Y'CbCr. V4L2_QUANTIZATION_FULL_RANGE @@ -620,8 +621,8 @@ is mapped to [16…235]. Cb and Cr are mapped from [-0.5…0.5] to [16
Detailed Colorspace Descriptions -
- Colorspace SMPTE 170M (<constant>V4L2_COLORSPACE_SMPTE170M</constant>) +
+ Colorspace SMPTE 170M (<constant>V4L2_COLORSPACE_SMPTE170M</constant>) The standard defines the colorspace used by NTSC and PAL and by SDTV in general. The default Y'CbCr encoding is V4L2_YCBCR_ENC_601. The default Y'CbCr quantization is limited range. The chromaticities of the primary colors and @@ -666,8 +667,7 @@ as the SMPTE C set, so this colorspace is sometimes called SMPTE C as well. The transfer function defined for SMPTE 170M is the same as the -one defined in Rec. 709. Normally L is in the range [0…1], but for the extended -gamut xvYCC encoding values outside that range are allowed. +one defined in Rec. 709. L' = -1.099(-L)0.45 + 0.099 for L ≤ -0.018 L' = 4.5L for -0.018 < L < 0.018 @@ -702,29 +702,10 @@ defined in the standard and this colorspace is sometim though BT.601 does not mention any color primaries. The default quantization is limited range, but full range is possible although rarely seen. - The V4L2_YCBCR_ENC_601 encoding as described above is the -default for this colorspace, but it can be overridden with V4L2_YCBCR_ENC_709, -in which case the Rec. 709 Y'CbCr encoding is used. - - - The xvYCC 601 encoding (V4L2_YCBCR_ENC_XV601, ) is similar -to the BT.601 encoding, but it allows for R', G' and B' values that are outside the range -[0…1]. The resulting Y', Cb and Cr values are scaled and offset: - - Y' = (219 / 255) * (0.299R' + 0.587G' + 0.114B') + (16 / 255) - Cb = (224 / 255) * (-0.169R' - 0.331G' + 0.5B') - Cr = (224 / 255) * (0.5R' - 0.419G' - 0.081B') - - - - Y' is clamped to the range [0…1] and Cb and Cr are clamped -to the range [-0.5…0.5]. The non-standard xvYCC 709 encoding can also be used by selecting -V4L2_YCBCR_ENC_XV709. The xvYCC encodings always use full range -quantization.
-
- Colorspace Rec. 709 (<constant>V4L2_COLORSPACE_REC709</constant>) +
+ Colorspace Rec. 709 (<constant>V4L2_COLORSPACE_REC709</constant>) The standard defines the colorspace used by HDTV in general. The default Y'CbCr encoding is V4L2_YCBCR_ENC_709. The default Y'CbCr quantization is limited range. The chromaticities of the primary colors and the white reference are: @@ -803,26 +784,39 @@ rarely seen. The V4L2_YCBCR_ENC_709 encoding described above is the default for this colorspace, but it can be overridden with V4L2_YCBCR_ENC_601, in which case the BT.601 Y'CbCr encoding is used. + Two additional extended gamut Y'CbCr encodings are also possible with this colorspace: The xvYCC 709 encoding (V4L2_YCBCR_ENC_XV709, ) is similar to the Rec. 709 encoding, but it allows for R', G' and B' values that are outside the range [0…1]. The resulting Y', Cb and Cr values are scaled and offset: - Y' = (219 / 255) * (0.2126R' + 0.7152G' + 0.0722B') + (16 / 255) - Cb = (224 / 255) * (-0.1146R' - 0.3854G' + 0.5B') - Cr = (224 / 255) * (0.5R' - 0.4542G' - 0.0458B') + Y' = (219 / 256) * (0.2126R' + 0.7152G' + 0.0722B') + (16 / 256) + Cb = (224 / 256) * (-0.1146R' - 0.3854G' + 0.5B') + Cr = (224 / 256) * (0.5R' - 0.4542G' - 0.0458B') + + + + + + The xvYCC 601 encoding (V4L2_YCBCR_ENC_XV601, ) is similar +to the BT.601 encoding, but it allows for R', G' and B' values that are outside the range +[0…1]. The resulting Y', Cb and Cr values are scaled and offset: + + Y' = (219 / 256) * (0.299R' + 0.587G' + 0.114B') + (16 / 256) + Cb = (224 / 256) * (-0.169R' - 0.331G' + 0.5B') + Cr = (224 / 256) * (0.5R' - 0.419G' - 0.081B') Y' is clamped to the range [0…1] and Cb and Cr are clamped -to the range [-0.5…0.5]. The non-standard xvYCC 601 encoding can also be used by -selecting V4L2_YCBCR_ENC_XV601. The xvYCC encodings always use full -range quantization. +to the range [-0.5…0.5]. The non-standard xvYCC 709 or xvYCC 601 encodings can be used by +selecting V4L2_YCBCR_ENC_XV709 or V4L2_YCBCR_ENC_XV601. +The xvYCC encodings always use full range quantization.
-
- Colorspace sRGB (<constant>V4L2_COLORSPACE_SRGB</constant>) +
+ Colorspace sRGB (<constant>V4L2_COLORSPACE_SRGB</constant>) The standard defines the colorspace used by most webcams and computer graphics. The default Y'CbCr encoding is V4L2_YCBCR_ENC_SYCC. The default Y'CbCr quantization is full range. The chromaticities of the primary colors and the white reference are: @@ -898,8 +892,8 @@ encoding, it is not. The V4L2_YCBCR_ENC_XV601 scales and of values before quantization, but this encoding does not do that.
-
- Colorspace Adobe RGB (<constant>V4L2_COLORSPACE_ADOBERGB</constant>) +
+ Colorspace Adobe RGB (<constant>V4L2_COLORSPACE_ADOBERGB</constant>) The standard defines the colorspace used by computer graphics that use the AdobeRGB colorspace. This is also known as the standard. The default Y'CbCr encoding is V4L2_YCBCR_ENC_601. The default Y'CbCr @@ -970,12 +964,12 @@ clamped to the range [-0.5…0.5]. This transform is identical to one defin SMPTE 170M/BT.601. The Y'CbCr quantization is limited range.
-
- Colorspace BT.2020 (<constant>V4L2_COLORSPACE_BT2020</constant>) +
+ Colorspace BT.2020 (<constant>V4L2_COLORSPACE_BT2020</constant>) The standard defines the colorspace used by Ultra-high definition television (UHDTV). The default Y'CbCr encoding is V4L2_YCBCR_ENC_BT2020. -The default Y'CbCr quantization is limited range. The chromaticities of the primary colors and -the white reference are: +The default R'G'B' quantization is limited range (!), and so is the default Y'CbCr quantization. +The chromaticities of the primary colors and the white reference are:
BT.2020 Chromaticities @@ -1032,7 +1026,7 @@ the white reference are: The luminance (Y') and color difference (Cb and Cr) are obtained with the following V4L2_YCBCR_ENC_BT2020 encoding: - Y' = 0.2627R' + 0.6789G' + 0.0593B' + Y' = 0.2627R' + 0.6780G' + 0.0593B' Cb = -0.1396R' - 0.3604G' + 0.5B' Cr = 0.5R' - 0.4598G' - 0.0402B' @@ -1046,7 +1040,7 @@ clamped to the range [-0.5…0.5]. The Y'CbCr quantization is limited range Luma: - Yc' = (0.2627R + 0.6789G + 0.0593B)' + Yc' = (0.2627R + 0.6780G + 0.0593B)' @@ -1054,7 +1048,7 @@ clamped to the range [-0.5…0.5]. The Y'CbCr quantization is limited range B' - Yc' ≤ 0: - Cbc = (B' - Y') / 1.9404 + Cbc = (B' - Yc') / 1.9404 @@ -1062,7 +1056,7 @@ clamped to the range [-0.5…0.5]. The Y'CbCr quantization is limited range B' - Yc' > 0: - Cbc = (B' - Y') / 1.5816 + Cbc = (B' - Yc') / 1.5816 @@ -1086,8 +1080,8 @@ clamped to the range [-0.5…0.5]. The Y'CbCr quantization is limited range clamped to the range [-0.5…0.5]. The Yc'CbcCrc quantization is limited range. -
- Colorspace SMPTE 240M (<constant>V4L2_COLORSPACE_SMPTE240M</constant>) +
+ Colorspace SMPTE 240M (<constant>V4L2_COLORSPACE_SMPTE240M</constant>) The standard was an interim standard used during the early days of HDTV (1988-1998). It has been superseded by Rec. 709. The default Y'CbCr encoding is V4L2_YCBCR_ENC_SMPTE240M. The default Y'CbCr quantization is limited range. The chromaticities of the primary colors and the @@ -1159,8 +1153,8 @@ following V4L2_YCBCR_ENC_SMPTE240M encoding: clamped to the range [-0.5…0.5]. The Y'CbCr quantization is limited range.
-
- Colorspace NTSC 1953 (<constant>V4L2_COLORSPACE_470_SYSTEM_M</constant>) +
+ Colorspace NTSC 1953 (<constant>V4L2_COLORSPACE_470_SYSTEM_M</constant>) This standard defines the colorspace used by NTSC in 1953. In practice this colorspace is obsolete and SMPTE 170M should be used instead. The default Y'CbCr encoding is V4L2_YCBCR_ENC_601. The default Y'CbCr quantization is limited range. @@ -1237,8 +1231,8 @@ clamped to the range [-0.5…0.5]. The Y'CbCr quantization is limited range This transform is identical to one defined in SMPTE 170M/BT.601.
-
- Colorspace EBU Tech. 3213 (<constant>V4L2_COLORSPACE_470_SYSTEM_BG</constant>) +
+ Colorspace EBU Tech. 3213 (<constant>V4L2_COLORSPACE_470_SYSTEM_BG</constant>) The standard defines the colorspace used by PAL/SECAM in 1975. In practice this colorspace is obsolete and SMPTE 170M should be used instead. The default Y'CbCr encoding is V4L2_YCBCR_ENC_601. The default Y'CbCr quantization is limited range. @@ -1311,8 +1305,8 @@ clamped to the range [-0.5…0.5]. The Y'CbCr quantization is limited range This transform is identical to one defined in SMPTE 170M/BT.601.
-
- Colorspace JPEG (<constant>V4L2_COLORSPACE_JPEG</constant>) +
+ Colorspace JPEG (<constant>V4L2_COLORSPACE_JPEG</constant>) This colorspace defines the colorspace used by most (Motion-)JPEG formats. The chromaticities of the primary colors and the white reference are identical to sRGB. The Y'CbCr encoding is V4L2_YCBCR_ENC_601 with full range quantization where diff --git a/Documentation/DocBook/media/v4l/subdev-formats.xml b/Documentation/DocBook/media/v4l/subdev-formats.xml index c5ea868e390958d499681d1b63570c11c9933721..2588ad781242e2d3f655fa1fcc2d35fe09257293 100644 --- a/Documentation/DocBook/media/v4l/subdev-formats.xml +++ b/Documentation/DocBook/media/v4l/subdev-formats.xml @@ -91,7 +91,9 @@ see . For formats where the total number of bits per pixel is smaller than the number of bus samples per pixel times the bus width, a padding value stating if the bytes are padded in their most high order bits - (PADHI) or low order bits (PADLO). + (PADHI) or low order bits (PADLO). A "C" prefix is used for component-wise + padding in the most high order bits (CPADHI) or low order bits (CPADLO) + of each separate component. For formats where the number of bus samples per pixel is larger than 1, an endianness value stating if the pixel is transferred MSB first (BE) or LSB first (LE). @@ -192,6 +194,24 @@ see .
+ + MEDIA_BUS_FMT_RGB444_1X12 + 0x1016 + + &dash-ent-20; + r3 + r2 + r1 + r0 + g3 + g2 + g1 + g0 + b3 + b2 + b1 + b0 + MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 @@ -304,6 +324,28 @@ see . g4 g3 + + MEDIA_BUS_FMT_RGB565_1X16 + 0x1017 + + &dash-ent-16; + r4 + r3 + r2 + r1 + r0 + g5 + g4 + g3 + g2 + g1 + g0 + b4 + b3 + b2 + b1 + b0 + MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005 @@ -440,6 +482,126 @@ see . b1 b0 + + MEDIA_BUS_FMT_RBG888_1X24 + 0x100e + + &dash-ent-8; + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + + + MEDIA_BUS_FMT_RGB666_1X24_CPADHI + 0x1015 + + &dash-ent-8; + 0 + 0 + r5 + r4 + r3 + r2 + r1 + r0 + 0 + 0 + g5 + g4 + g3 + g2 + g1 + g0 + 0 + 0 + b5 + b4 + b3 + b2 + b1 + b0 + + + MEDIA_BUS_FMT_BGR888_1X24 + 0x1013 + + &dash-ent-8; + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + + + MEDIA_BUS_FMT_GBR888_1X24 + 0x1014 + + &dash-ent-8; + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + MEDIA_BUS_FMT_RGB888_1X24 0x100a @@ -579,99 +741,81 @@ see . b1 b0 + + MEDIA_BUS_FMT_RGB888_1X32_PADHI + 0x100f + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 +
- - -
- Bayer Formats - - Those formats transfer pixel data as red, green and blue components. - The format code is made of the following information. - - The red, green and blue components order code, as encoded in a - pixel sample. The possible values are shown in . - The number of bits per pixel component. All components are - transferred on the same number of bits. Common values are 8, 10 and 12. - - The compression (optional). If the pixel components are - ALAW- or DPCM-compressed, a mention of the compression scheme and the - number of bits per compressed pixel component. - The number of bus samples per pixel. Pixels that are wider than - the bus width must be transferred in multiple samples. Common values are - 1 and 2. - The bus width. - For formats where the total number of bits per pixel is smaller - than the number of bus samples per pixel times the bus width, a padding - value stating if the bytes are padded in their most high order bits - (PADHI) or low order bits (PADLO). - For formats where the number of bus samples per pixel is larger - than 1, an endianness value stating if the pixel is transferred MSB first - (BE) or LSB first (LE). - - - For instance, a format with uncompressed 10-bit Bayer components - arranged in a red, green, green, blue pattern transferred as 2 8-bit - samples per pixel with the least significant bits transferred first will - be named MEDIA_BUS_FMT_SRGGB10_2X8_PADHI_LE. + On LVDS buses, usually each sample is transferred serialized in + seven time slots per pixel clock, on three (18-bit) or four (24-bit) + differential data pairs at the same time. The remaining bits are used for + control signals as defined by SPWG/PSWG/VESA or JEIDA standards. + The 24-bit RGB format serialized in seven time slots on four lanes using + JEIDA defined bit mapping will be named + MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, for example. -
- Bayer Patterns - - - - - - Bayer filter color patterns - - -
- - The following table lists existing packed Bayer formats. The data - organization is given as an example for the first pixel only. - - - Bayer Formats - +
+ LVDS RGB formats + - - - - - - - - - - - - - - - + + + + + + + + Identifier Code - Data organization + + Data organization - Bit - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 + Timeslot + Lane 3 2 1 @@ -679,7 +823,317 @@ see . - + + MEDIA_BUS_FMT_RGB666_1X7X3_SPWG + 0x1010 + 0 + + - + d + b1 + g0 + + + + + 1 + + - + d + b0 + r5 + + + + + 2 + + - + d + g5 + r4 + + + + + 3 + + - + b5 + g4 + r3 + + + + + 4 + + - + b4 + g3 + r2 + + + + + 5 + + - + b3 + g2 + r1 + + + + + 6 + + - + b2 + g1 + r0 + + + MEDIA_BUS_FMT_RGB888_1X7X4_SPWG + 0x1011 + 0 + + d + d + b1 + g0 + + + + + 1 + + b7 + d + b0 + r5 + + + + + 2 + + b6 + d + g5 + r4 + + + + + 3 + + g7 + b5 + g4 + r3 + + + + + 4 + + g6 + b4 + g3 + r2 + + + + + 5 + + r7 + b3 + g2 + r1 + + + + + 6 + + r6 + b2 + g1 + r0 + + + MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA + 0x1012 + 0 + + d + d + b3 + g2 + + + + + 1 + + b1 + d + b2 + r7 + + + + + 2 + + b0 + d + g7 + r6 + + + + + 3 + + g1 + b7 + g6 + r5 + + + + + 4 + + g0 + b6 + g5 + r4 + + + + + 5 + + r1 + b5 + g4 + r3 + + + + + 6 + + r0 + b4 + g3 + r2 + + + +
+
+ +
+ Bayer Formats + + Those formats transfer pixel data as red, green and blue components. + The format code is made of the following information. + + The red, green and blue components order code, as encoded in a + pixel sample. The possible values are shown in . + The number of bits per pixel component. All components are + transferred on the same number of bits. Common values are 8, 10 and 12. + + The compression (optional). If the pixel components are + ALAW- or DPCM-compressed, a mention of the compression scheme and the + number of bits per compressed pixel component. + The number of bus samples per pixel. Pixels that are wider than + the bus width must be transferred in multiple samples. Common values are + 1 and 2. + The bus width. + For formats where the total number of bits per pixel is smaller + than the number of bus samples per pixel times the bus width, a padding + value stating if the bytes are padded in their most high order bits + (PADHI) or low order bits (PADLO). + For formats where the number of bus samples per pixel is larger + than 1, an endianness value stating if the pixel is transferred MSB first + (BE) or LSB first (LE). + + + + For instance, a format with uncompressed 10-bit Bayer components + arranged in a red, green, green, blue pattern transferred as 2 8-bit + samples per pixel with the least significant bits transferred first will + be named MEDIA_BUS_FMT_SRGGB10_2X8_PADHI_LE. + + +
+ Bayer Patterns + + + + + + Bayer filter color patterns + + +
+ + The following table lists existing packed Bayer formats. The data + organization is given as an example for the first pixel only. + + + Bayer Formats + + + + + + + + + + + + + + + + + + + + Identifier + Code + + Data organization + + + + + Bit + 11 + 10 + 9 + 8 + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 + + + + MEDIA_BUS_FMT_SBGGR8_1X8 0x3001 @@ -2188,11 +2642,15 @@ see . y1 y0 - - MEDIA_BUS_FMT_UYVY8_1X16 - 0x200f + + MEDIA_BUS_FMT_UYVY12_2X12 + 0x201c - &dash-ent-16; + &dash-ent-20; + u11 + u10 + u9 + u8 u7 u6 u5 @@ -2201,28 +2659,16 @@ see . u2 u1 u0 - y7 - y6 - y5 - y4 - y3 - y2 - y1 - y0 - &dash-ent-16; - v7 - v6 - v5 - v4 - v3 - v2 - v1 - v0 + &dash-ent-20; + y11 + y10 + y9 + y8 y7 y6 y5 @@ -2232,11 +2678,15 @@ see . y1 y0 - - MEDIA_BUS_FMT_VYUY8_1X16 - 0x2010 + - &dash-ent-16; + + + &dash-ent-20; + v11 + v10 + v9 + v8 v7 v6 v5 @@ -2245,28 +2695,16 @@ see . v2 v1 v0 - y7 - y6 - y5 - y4 - y3 - y2 - y1 - y0 - &dash-ent-16; - u7 - u6 - u5 - u4 - u3 - u2 - u1 - u0 + &dash-ent-20; + y11 + y10 + y9 + y8 y7 y6 y5 @@ -2276,41 +2714,15 @@ see . y1 y0 - - MEDIA_BUS_FMT_YUYV8_1X16 - 0x2011 - - &dash-ent-16; - y7 - y6 - y5 - y4 - y3 - y2 - y1 - y0 - u7 - u6 - u5 - u4 - u3 - u2 - u1 - u0 - - - - + + MEDIA_BUS_FMT_VYUY12_2X12 + 0x201d - &dash-ent-16; - y7 - y6 - y5 - y4 - y3 - y2 - y1 - y0 + &dash-ent-20; + v11 + v10 + v9 + v8 v7 v6 v5 @@ -2320,11 +2732,15 @@ see . v1 v0 - - MEDIA_BUS_FMT_YVYU8_1X16 - 0x2012 + - &dash-ent-16; + + + &dash-ent-20; + y11 + y10 + y9 + y8 y7 y6 y5 @@ -2333,28 +2749,16 @@ see . y2 y1 y0 - v7 - v6 - v5 - v4 - v3 - v2 - v1 - v0 - &dash-ent-16; - y7 - y6 - y5 - y4 - y3 - y2 - y1 - y0 + &dash-ent-20; + u11 + u10 + u9 + u8 u7 u6 u5 @@ -2364,11 +2768,15 @@ see . u1 u0 - - MEDIA_BUS_FMT_YDYUYDYV8_1X16 - 0x2014 + - &dash-ent-16; + + + &dash-ent-20; + y11 + y10 + y9 + y8 y7 y6 y5 @@ -2377,20 +2785,16 @@ see . y2 y1 y0 - d - d - d - d - d - d - d - d - - - + + MEDIA_BUS_FMT_YUYV12_2X12 + 0x201e - &dash-ent-16; + &dash-ent-20; + y11 + y10 + y9 + y8 y7 y6 y5 @@ -2399,6 +2803,16 @@ see . y2 y1 y0 + + + + + + &dash-ent-20; + u11 + u10 + u9 + u8 u7 u6 u5 @@ -2412,7 +2826,11 @@ see . - &dash-ent-16; + &dash-ent-20; + y11 + y10 + y9 + y8 y7 y6 y5 @@ -2421,20 +2839,34 @@ see . y2 y1 y0 - d - d - d - d - d - d - d - d - &dash-ent-16; + &dash-ent-20; + v11 + v10 + v9 + v8 + v7 + v6 + v5 + v4 + v3 + v2 + v1 + v0 + + + MEDIA_BUS_FMT_YVYU12_2X12 + 0x201f + + &dash-ent-20; + y11 + y10 + y9 + y8 y7 y6 y5 @@ -2443,6 +2875,16 @@ see . y2 y1 y0 + + + + + + &dash-ent-20; + v11 + v10 + v9 + v8 v7 v6 v5 @@ -2452,11 +2894,31 @@ see . v1 v0 - - MEDIA_BUS_FMT_UYVY10_1X20 - 0x201a + - &dash-ent-12; + + + &dash-ent-20; + y11 + y10 + y9 + y8 + y7 + y6 + y5 + y4 + y3 + y2 + y1 + y0 + + + + + + &dash-ent-20; + u11 + u10 u9 u8 u7 @@ -2467,8 +2929,20 @@ see . u2 u1 u0 - y9 - y8 + + + MEDIA_BUS_FMT_UYVY8_1X16 + 0x200f + + &dash-ent-16; + u7 + u6 + u5 + u4 + u3 + u2 + u1 + u0 y7 y6 y5 @@ -2482,9 +2956,7 @@ see . - &dash-ent-12; - v9 - v8 + &dash-ent-16; v7 v6 v5 @@ -2493,8 +2965,6 @@ see . v2 v1 v0 - y9 - y8 y7 y6 y5 @@ -2504,13 +2974,11 @@ see . y1 y0 - - MEDIA_BUS_FMT_VYUY10_1X20 - 0x201b + + MEDIA_BUS_FMT_VYUY8_1X16 + 0x2010 - &dash-ent-12; - v9 - v8 + &dash-ent-16; v7 v6 v5 @@ -2519,8 +2987,6 @@ see . v2 v1 v0 - y9 - y8 y7 y6 y5 @@ -2534,9 +3000,7 @@ see . - &dash-ent-12; - u9 - u8 + &dash-ent-16; u7 u6 u5 @@ -2545,8 +3009,6 @@ see . u2 u1 u0 - y9 - y8 y7 y6 y5 @@ -2556,13 +3018,11 @@ see . y1 y0 - - MEDIA_BUS_FMT_YUYV10_1X20 - 0x200d + + MEDIA_BUS_FMT_YUYV8_1X16 + 0x2011 - &dash-ent-12; - y9 - y8 + &dash-ent-16; y7 y6 y5 @@ -2571,8 +3031,6 @@ see . y2 y1 y0 - u9 - u8 u7 u6 u5 @@ -2586,9 +3044,7 @@ see . - &dash-ent-12; - y9 - y8 + &dash-ent-16; y7 y6 y5 @@ -2597,8 +3053,6 @@ see . y2 y1 y0 - v9 - v8 v7 v6 v5 @@ -2608,13 +3062,11 @@ see . v1 v0 - - MEDIA_BUS_FMT_YVYU10_1X20 - 0x200e + + MEDIA_BUS_FMT_YVYU8_1X16 + 0x2012 - &dash-ent-12; - y9 - y8 + &dash-ent-16; y7 y6 y5 @@ -2623,8 +3075,6 @@ see . y2 y1 y0 - v9 - v8 v7 v6 v5 @@ -2638,9 +3088,7 @@ see . - &dash-ent-12; - y9 - y8 + &dash-ent-16; y7 y6 y5 @@ -2649,8 +3097,6 @@ see . y2 y1 y0 - u9 - u8 u7 u6 u5 @@ -2660,14 +3106,11 @@ see . u1 u0 - - MEDIA_BUS_FMT_YUV10_1X30 - 0x2016 + + MEDIA_BUS_FMT_YDYUYDYV8_1X16 + 0x2014 - - - - - y9 - y8 + &dash-ent-16; y7 y6 y5 @@ -2676,39 +3119,20 @@ see . y2 y1 y0 - u9 - u8 - u7 - u6 - u5 - u4 - u3 - u2 - u1 - u0 - v9 - v8 - v7 - v6 - v5 - v4 - v3 - v2 - v1 - v0 + d + d + d + d + d + d + d + d - - MEDIA_BUS_FMT_AYUV8_1X32 - 0x2017 + - a7 - a6 - a5 - a4 - a3 - a2 - a1 - a0 + + + &dash-ent-16; y7 y6 y5 @@ -2725,6 +3149,42 @@ see . u2 u1 u0 + + + + + + &dash-ent-16; + y7 + y6 + y5 + y4 + y3 + y2 + y1 + y0 + d + d + d + d + d + d + d + d + + + + + + &dash-ent-16; + y7 + y6 + y5 + y4 + y3 + y2 + y1 + y0 v7 v6 v5 @@ -2734,13 +3194,11 @@ see . v1 v0 - - MEDIA_BUS_FMT_UYVY12_2X12 - 0x201c + + MEDIA_BUS_FMT_UYVY10_1X20 + 0x201a - &dash-ent-20; - u11 - u10 + &dash-ent-12; u9 u8 u7 @@ -2751,14 +3209,6 @@ see . u2 u1 u0 - - - - - - &dash-ent-20; - y11 - y10 y9 y8 y7 @@ -2774,9 +3224,7 @@ see . - &dash-ent-20; - v11 - v10 + &dash-ent-12; v9 v8 v7 @@ -2787,14 +3235,6 @@ see . v2 v1 v0 - - - - - - &dash-ent-20; - y11 - y10 y9 y8 y7 @@ -2806,13 +3246,11 @@ see . y1 y0 - - MEDIA_BUS_FMT_VYUY12_2X12 - 0x201d + + MEDIA_BUS_FMT_VYUY10_1X20 + 0x201b - &dash-ent-20; - v11 - v10 + &dash-ent-12; v9 v8 v7 @@ -2823,14 +3261,6 @@ see . v2 v1 v0 - - - - - - &dash-ent-20; - y11 - y10 y9 y8 y7 @@ -2846,9 +3276,7 @@ see . - &dash-ent-20; - u11 - u10 + &dash-ent-12; u9 u8 u7 @@ -2859,14 +3287,6 @@ see . u2 u1 u0 - - - - - - &dash-ent-20; - y11 - y10 y9 y8 y7 @@ -2878,13 +3298,11 @@ see . y1 y0 - - MEDIA_BUS_FMT_YUYV12_2X12 - 0x201e + + MEDIA_BUS_FMT_YUYV10_1X20 + 0x200d - &dash-ent-20; - y11 - y10 + &dash-ent-12; y9 y8 y7 @@ -2895,14 +3313,6 @@ see . y2 y1 y0 - - - - - - &dash-ent-20; - u11 - u10 u9 u8 u7 @@ -2918,9 +3328,7 @@ see . - &dash-ent-20; - y11 - y10 + &dash-ent-12; y9 y8 y7 @@ -2931,14 +3339,6 @@ see . y2 y1 y0 - - - - - - &dash-ent-20; - v11 - v10 v9 v8 v7 @@ -2950,13 +3350,11 @@ see . v1 v0 - - MEDIA_BUS_FMT_YVYU12_2X12 - 0x201f + + MEDIA_BUS_FMT_YVYU10_1X20 + 0x200e - &dash-ent-20; - y11 - y10 + &dash-ent-12; y9 y8 y7 @@ -2967,14 +3365,6 @@ see . y2 y1 y0 - - - - - - &dash-ent-20; - v11 - v10 v9 v8 v7 @@ -2990,9 +3380,7 @@ see . - &dash-ent-20; - y11 - y10 + &dash-ent-12; y9 y8 y7 @@ -3003,16 +3391,67 @@ see . y2 y1 y0 + u9 + u8 + u7 + u6 + u5 + u4 + u3 + u2 + u1 + u0 - - + + MEDIA_BUS_FMT_VUY8_1X24 + 0x201a + &dash-ent-8; + v7 + v6 + v5 + v4 + v3 + v2 + v1 + v0 + u7 + u6 + u5 + u4 + u3 + u2 + u1 + u0 + y7 + y6 + y5 + y4 + y3 + y2 + y1 + y0 + + + MEDIA_BUS_FMT_YUV8_1X24 + 0x2025 - &dash-ent-20; - u11 - u10 - u9 - u8 + - + - + - + - + - + - + - + - + y7 + y6 + y5 + y4 + y3 + y2 + y1 + y0 u7 u6 u5 @@ -3021,6 +3460,14 @@ see . u2 u1 u0 + v7 + v6 + v5 + v4 + v3 + v2 + v1 + v0 MEDIA_BUS_FMT_UYVY12_1X24 @@ -3262,6 +3709,80 @@ see . u1 u0 + + MEDIA_BUS_FMT_YUV10_1X30 + 0x2016 + + - + - + y9 + y8 + y7 + y6 + y5 + y4 + y3 + y2 + y1 + y0 + u9 + u8 + u7 + u6 + u5 + u4 + u3 + u2 + u1 + u0 + v9 + v8 + v7 + v6 + v5 + v4 + v3 + v2 + v1 + v0 + + + MEDIA_BUS_FMT_AYUV8_1X32 + 0x2017 + + a7 + a6 + a5 + a4 + a3 + a2 + a1 + a0 + y7 + y6 + y5 + y4 + y3 + y2 + y1 + y0 + u7 + u6 + u5 + u4 + u3 + u2 + u1 + u0 + v7 + v6 + v5 + v4 + v3 + v2 + v1 + v0 +
diff --git a/Documentation/DocBook/media/v4l/v4l2.xml b/Documentation/DocBook/media/v4l/v4l2.xml index ac0f8d9d2a4976a59f6c02b44de1b6859e768134..e98caa1c39bd21ed89ca24e47a85f1733bf38be9 100644 --- a/Documentation/DocBook/media/v4l/v4l2.xml +++ b/Documentation/DocBook/media/v4l/v4l2.xml @@ -136,6 +136,7 @@ Remote Controller chapter. 2012 2013 2014 + 2015 Bill Dirks, Michael H. Schimek, Hans Verkuil, Martin Rubli, Andy Walls, Muralidharan Karicheri, Mauro Carvalho Chehab, Pawel Osciak @@ -151,6 +152,14 @@ structs, ioctls) must be noted in more detail in the history chapter (compat.xml), along with the possible impact on existing drivers and applications. --> + + 3.21 + 2015-02-13 + mcc + Fix documentation for media controller device nodes and add support for DVB device nodes. +Add support for Tuner sub-device. + + 3.19 2014-12-05 diff --git a/Documentation/DocBook/media/v4l/vidioc-cropcap.xml b/Documentation/DocBook/media/v4l/vidioc-cropcap.xml index 1f5ed64cd75a0e5c2aeb3cc0ea4c7ff670aceeea..50cb940cbe5ca97eb915e2044eb7ab2a7780a4f9 100644 --- a/Documentation/DocBook/media/v4l/vidioc-cropcap.xml +++ b/Documentation/DocBook/media/v4l/vidioc-cropcap.xml @@ -59,6 +59,11 @@ constant except when switching the video standard. Remember this switch can occur implicit when switching the video input or output. +Do not use the multiplanar buffer types. Use V4L2_BUF_TYPE_VIDEO_CAPTURE +instead of V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE +and use V4L2_BUF_TYPE_VIDEO_OUTPUT instead of +V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE. + This ioctl must be implemented for video capture or output devices that support cropping and/or scaling and/or have non-square pixels, and for overlay devices. @@ -73,9 +78,7 @@ support cropping and/or scaling and/or have non-square pixels, and for overlay d Type of the data stream, set by the application. Only these types are valid here: V4L2_BUF_TYPE_VIDEO_CAPTURE, -V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, -V4L2_BUF_TYPE_VIDEO_OUTPUT, -V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE and +V4L2_BUF_TYPE_VIDEO_OUTPUT and V4L2_BUF_TYPE_VIDEO_OVERLAY. See . diff --git a/Documentation/DocBook/media/v4l/vidioc-dqevent.xml b/Documentation/DocBook/media/v4l/vidioc-dqevent.xml index b036f8963353a2a2f88c336855da9282e7d68fb6..50ccd33948c1cbee6fb8bbd28864681780c1b833 100644 --- a/Documentation/DocBook/media/v4l/vidioc-dqevent.xml +++ b/Documentation/DocBook/media/v4l/vidioc-dqevent.xml @@ -64,7 +64,7 @@ __u32 type - Type of the event. + Type of the event, see . union @@ -154,6 +154,113 @@ + + Event Types + + &cs-def; + + + V4L2_EVENT_ALL + 0 + All events. V4L2_EVENT_ALL is valid only for + VIDIOC_UNSUBSCRIBE_EVENT for unsubscribing all events at once. + + + + V4L2_EVENT_VSYNC + 1 + This event is triggered on the vertical sync. + This event has a &v4l2-event-vsync; associated with it. + + + + V4L2_EVENT_EOS + 2 + This event is triggered when the end of a stream is reached. + This is typically used with MPEG decoders to report to the application + when the last of the MPEG stream has been decoded. + + + + V4L2_EVENT_CTRL + 3 + This event requires that the id + matches the control ID from which you want to receive events. + This event is triggered if the control's value changes, if a + button control is pressed or if the control's flags change. + This event has a &v4l2-event-ctrl; associated with it. This struct + contains much of the same information as &v4l2-queryctrl; and + &v4l2-control;. + + If the event is generated due to a call to &VIDIOC-S-CTRL; or + &VIDIOC-S-EXT-CTRLS;, then the event will not be sent to + the file handle that called the ioctl function. This prevents + nasty feedback loops. If you do want to get the + event, then set the V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK + flag. + + + This event type will ensure that no information is lost when + more events are raised than there is room internally. In that + case the &v4l2-event-ctrl; of the second-oldest event is kept, + but the changes field of the + second-oldest event is ORed with the changes + field of the oldest event. + + + + V4L2_EVENT_FRAME_SYNC + 4 + + Triggered immediately when the reception of a + frame has begun. This event has a + &v4l2-event-frame-sync; associated with it. + + If the hardware needs to be stopped in the case of a + buffer underrun it might not be able to generate this event. + In such cases the frame_sequence + field in &v4l2-event-frame-sync; will not be incremented. This + causes two consecutive frame sequence numbers to have n times + frame interval in between them. + + + + V4L2_EVENT_SOURCE_CHANGE + 5 + + This event is triggered when a source parameter change is + detected during runtime by the video device. It can be a + runtime resolution change triggered by a video decoder or the + format change happening on an input connector. + This event requires that the id + matches the input index (when used with a video device node) + or the pad index (when used with a subdevice node) from which + you want to receive events. + + This event has a &v4l2-event-src-change; associated + with it. The changes bitfield denotes + what has changed for the subscribed pad. If multiple events + occurred before application could dequeue them, then the changes + will have the ORed value of all the events generated. + + + + V4L2_EVENT_MOTION_DET + 6 + + Triggered whenever the motion detection state for one or more of the regions + changes. This event has a &v4l2-event-motion-det; associated with it. + + + + V4L2_EVENT_PRIVATE_START + 0x08000000 + Base event number for driver-private events. + + + +
+ struct <structname>v4l2_event_vsync</structname> @@ -177,7 +284,7 @@ __u32 changes - A bitmask that tells what has changed. See . + A bitmask that tells what has changed. See . __u32 @@ -309,8 +416,8 @@
- - Changes +
+ Control Changes &cs-def; @@ -318,9 +425,9 @@ V4L2_EVENT_CTRL_CH_VALUE0x0001This control event was triggered because the value of the control - changed. Special case: if a button control is pressed, then this - event is sent as well, even though there is not explicit value - associated with a button control. + changed. Special cases: Volatile controls do no generate this event; + If a control has the V4L2_CTRL_FLAG_EXECUTE_ON_WRITE + flag set, then this event is sent as well, regardless its value. V4L2_EVENT_CTRL_CH_FLAGS diff --git a/Documentation/DocBook/media/v4l/vidioc-g-crop.xml b/Documentation/DocBook/media/v4l/vidioc-g-crop.xml index 75c6a93de3c173246aff4763da48cfdc4b3ce81f..e6c4efb9e8b412517b7b71f2566d0ada66550bf2 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-crop.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-crop.xml @@ -70,6 +70,11 @@ structure or returns the &EINVAL; if cropping is not supported. VIDIOC_S_CROP ioctl with a pointer to this structure. +Do not use the multiplanar buffer types. Use V4L2_BUF_TYPE_VIDEO_CAPTURE +instead of V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE +and use V4L2_BUF_TYPE_VIDEO_OUTPUT instead of +V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE. + The driver first adjusts the requested dimensions against hardware limits, &ie; the bounds given by the capture/output window, and it rounds to the closest possible values of horizontal and diff --git a/Documentation/DocBook/media/v4l/vidioc-g-dv-timings.xml b/Documentation/DocBook/media/v4l/vidioc-g-dv-timings.xml index c4336577ff066a34ba7149ffde35e5e93ed2ef2c..764b635ed4cf7102e04eb3ae0de2a24f0a7f1238 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-dv-timings.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-dv-timings.xml @@ -318,10 +318,20 @@ can't generate such frequencies, then the flag will also be cleared. V4L2_DV_FL_HALF_LINE - Specific to interlaced formats: if set, then field 1 (aka the odd field) -is really one half-line longer and field 2 (aka the even field) is really one half-line -shorter, so each field has exactly the same number of half-lines. Whether half-lines can be -detected or used depends on the hardware. + Specific to interlaced formats: if set, then the vertical frontporch +of field 1 (aka the odd field) is really one half-line longer and the vertical backporch +of field 2 (aka the even field) is really one half-line shorter, so each field has exactly +the same number of half-lines. Whether half-lines can be detected or used depends on +the hardware. + + + + V4L2_DV_FL_IS_CE_VIDEO + If set, then this is a Consumer Electronics (CE) video format. +Such formats differ from other formats (commonly called IT formats) in that if +R'G'B' encoding is used then by default the R'G'B' values use limited range +(i.e. 16-235) as opposed to full range (i.e. 0-255). All formats defined in CEA-861 +except for the 640x480p59.94 format are CE formats. diff --git a/Documentation/DocBook/media/v4l/vidioc-g-fbuf.xml b/Documentation/DocBook/media/v4l/vidioc-g-fbuf.xml index 20460730b02ca242e0ba5d096761ac00ea8239af..77607cc196889b6fc14e412d72fc229fdf3210d0 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-fbuf.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-fbuf.xml @@ -240,9 +240,9 @@ where padding bytes after the last line of an image cross a system page boundary. Capture devices may write padding bytes, the value is undefined. Output devices ignore the contents of padding bytes.When the image format is planar the -bytesperline value applies to the largest +bytesperline value applies to the first plane and is divided by the same factor as the -width field for any smaller planes. For +width field for the other planes. For example the Cb and Cr planes of a YUV 4:2:0 image have half as many padding bytes following each line as the Y plane. To avoid ambiguities drivers must return a bytesperline value diff --git a/Documentation/DocBook/media/v4l/vidioc-g-selection.xml b/Documentation/DocBook/media/v4l/vidioc-g-selection.xml index 9c04ac8661b10eed113e74fb57d7a14b2fb792b1..0bb5c060db27847a7a93e2f22ae51743fe413d11 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-selection.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-selection.xml @@ -60,8 +60,8 @@ To query the cropping (composing) rectangle set &v4l2-selection; type field to the respective buffer type. -Do not use multiplanar buffers. Use V4L2_BUF_TYPE_VIDEO_CAPTURE -instead of V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE. Use +Do not use the multiplanar buffer types. Use V4L2_BUF_TYPE_VIDEO_CAPTURE +instead of V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE and use V4L2_BUF_TYPE_VIDEO_OUTPUT instead of V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE. The next step is setting the value of &v4l2-selection; target field diff --git a/Documentation/DocBook/media/v4l/vidioc-g-sliced-vbi-cap.xml b/Documentation/DocBook/media/v4l/vidioc-g-sliced-vbi-cap.xml index bd015d1563ffe45b8137eabeb9e463db2078cdcd..d05623c554037c6471b1acf38f3d32d4a55c289e 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-sliced-vbi-cap.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-sliced-vbi-cap.xml @@ -205,7 +205,7 @@ ETS 300 231, lsb first transmitted. V4L2_SLICED_CAPTION_525 0x1000 - + NTSC line 21, 284 (second field 21) Two bytes in transmission order, including parity bit, lsb first transmitted. diff --git a/Documentation/DocBook/media/v4l/vidioc-querycap.xml b/Documentation/DocBook/media/v4l/vidioc-querycap.xml index d0c5e604f014f3080966510d39cf7877e018d2be..20fda75a012dc130e8a94b1935d5efe574a5dae3 100644 --- a/Documentation/DocBook/media/v4l/vidioc-querycap.xml +++ b/Documentation/DocBook/media/v4l/vidioc-querycap.xml @@ -102,10 +102,10 @@ The bus_info must start with "PCI:" for PCI boards, "PCIe:" for PCI Express boar __u32 version Version number of the driver. -Starting on kernel 3.1, the version reported is provided per -V4L2 subsystem, following the same Kernel numberation scheme. However, it -should not always return the same version as the kernel, if, for example, -an stable or distribution-modified kernel uses the V4L2 stack from a +Starting with kernel 3.1, the version reported is provided by the +V4L2 subsystem following the kernel numbering scheme. However, it +may not always return the same version as the kernel if, for example, +a stable or distribution-modified kernel uses the V4L2 stack from a newer kernel. The version number is formatted using the KERNEL_VERSION() macro: diff --git a/Documentation/DocBook/media/v4l/vidioc-queryctrl.xml b/Documentation/DocBook/media/v4l/vidioc-queryctrl.xml index 2bd98fd7a4e51ac542d423ab74e335b8de0a9e7a..dc83ad70f8dc8ff30c1b31c4cb833df169de80b2 100644 --- a/Documentation/DocBook/media/v4l/vidioc-queryctrl.xml +++ b/Documentation/DocBook/media/v4l/vidioc-queryctrl.xml @@ -600,7 +600,9 @@ writing a value will cause the device to carry out a given action changes continuously. A typical example would be the current gain value if the device is in auto-gain mode. In such a case the hardware calculates the gain value based on the lighting conditions which can change over time. Note that setting a new value for -a volatile control will have no effect. The new value will just be ignored. +a volatile control will have no effect and no V4L2_EVENT_CTRL_CH_VALUE +will be sent, unless the V4L2_CTRL_FLAG_EXECUTE_ON_WRITE flag +(see below) is also set. Otherwise the new value will just be ignored. V4L2_CTRL_FLAG_HAS_PAYLOAD @@ -610,6 +612,14 @@ using one of the pointer fields of &v4l2-ext-control;. This flag is set for cont that are an array, string, or have a compound type. In all cases you have to set a pointer to memory containing the payload of the control. + + V4L2_CTRL_FLAG_EXECUTE_ON_WRITE + 0x0200 + The value provided to the control will be propagated to the driver +even if remains constant. This is required when the control represents an action +on the hardware. For example: clearing an error flag or triggering the flash. All the +controls of the type V4L2_CTRL_TYPE_BUTTON have this flag set. +
diff --git a/Documentation/DocBook/media/v4l/vidioc-subdev-enum-frame-interval.xml b/Documentation/DocBook/media/v4l/vidioc-subdev-enum-frame-interval.xml index 2f8f4f0a023596c5b75d0ec22e8ce3d1be9ae350..cff59f5cbf044ce1c2545be614afb4fd74b25762 100644 --- a/Documentation/DocBook/media/v4l/vidioc-subdev-enum-frame-interval.xml +++ b/Documentation/DocBook/media/v4l/vidioc-subdev-enum-frame-interval.xml @@ -67,9 +67,9 @@ To enumerate frame intervals applications initialize the index, pad, - code, width and - height fields of - &v4l2-subdev-frame-interval-enum; and call the + which, code, + width and height + fields of &v4l2-subdev-frame-interval-enum; and call the VIDIOC_SUBDEV_ENUM_FRAME_INTERVAL ioctl with a pointer to this structure. Drivers fill the rest of the structure or return an &EINVAL; if one of the input fields is invalid. All frame intervals are @@ -123,7 +123,12 @@ __u32 - reserved[9] + which + Frame intervals to be enumerated, from &v4l2-subdev-format-whence;. + + + __u32 + reserved[8] Reserved for future extensions. Applications and drivers must set the array to zero. diff --git a/Documentation/DocBook/media/v4l/vidioc-subdev-enum-frame-size.xml b/Documentation/DocBook/media/v4l/vidioc-subdev-enum-frame-size.xml index 79ce42b7c60cf87b363fa5bc02ad1281358b83d8..abd545ede67ae1dd357af54b45b896c59163d3c8 100644 --- a/Documentation/DocBook/media/v4l/vidioc-subdev-enum-frame-size.xml +++ b/Documentation/DocBook/media/v4l/vidioc-subdev-enum-frame-size.xml @@ -61,9 +61,9 @@ ioctl. To enumerate frame sizes applications initialize the - pad, code and - index fields of the - &v4l2-subdev-mbus-code-enum; and call the + pad, which , + code and index + fields of the &v4l2-subdev-mbus-code-enum; and call the VIDIOC_SUBDEV_ENUM_FRAME_SIZE ioctl with a pointer to the structure. Drivers fill the minimum and maximum frame sizes or return an &EINVAL; if one of the input parameters is invalid. @@ -127,7 +127,12 @@ __u32 - reserved[9] + which + Frame sizes to be enumerated, from &v4l2-subdev-format-whence;. + + + __u32 + reserved[8] Reserved for future extensions. Applications and drivers must set the array to zero. diff --git a/Documentation/DocBook/media/v4l/vidioc-subdev-enum-mbus-code.xml b/Documentation/DocBook/media/v4l/vidioc-subdev-enum-mbus-code.xml index a6b3432449f64a8cab4fe9b5c5c84a7b8aa0412a..0bcb278fd062604f66a902b8a41c6ba166fd205c 100644 --- a/Documentation/DocBook/media/v4l/vidioc-subdev-enum-mbus-code.xml +++ b/Documentation/DocBook/media/v4l/vidioc-subdev-enum-mbus-code.xml @@ -56,8 +56,8 @@ To enumerate media bus formats available at a given sub-device pad - applications initialize the pad and - index fields of &v4l2-subdev-mbus-code-enum; and + applications initialize the pad, which + and index fields of &v4l2-subdev-mbus-code-enum; and call the VIDIOC_SUBDEV_ENUM_MBUS_CODE ioctl with a pointer to this structure. Drivers fill the rest of the structure or return an &EINVAL; if either the pad or @@ -93,7 +93,12 @@ __u32 - reserved[9] + which + Media bus format codes to be enumerated, from &v4l2-subdev-format-whence;. + + + __u32 + reserved[8] Reserved for future extensions. Applications and drivers must set the array to zero. diff --git a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml index d7c9365ecdbe245e05aee3875ee09ab5b8fa0199..d0332f6109296e1eccd530ee6e85da157b3855e3 100644 --- a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml +++ b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml @@ -60,7 +60,9 @@ __u32 type - Type of the event. + Type of the event, see . Note that +V4L2_EVENT_ALL can be used with VIDIOC_UNSUBSCRIBE_EVENT +for unsubscribing all events at once. __u32 @@ -84,113 +86,6 @@ - - Event Types - - &cs-def; - - - V4L2_EVENT_ALL - 0 - All events. V4L2_EVENT_ALL is valid only for - VIDIOC_UNSUBSCRIBE_EVENT for unsubscribing all events at once. - - - - V4L2_EVENT_VSYNC - 1 - This event is triggered on the vertical sync. - This event has a &v4l2-event-vsync; associated with it. - - - - V4L2_EVENT_EOS - 2 - This event is triggered when the end of a stream is reached. - This is typically used with MPEG decoders to report to the application - when the last of the MPEG stream has been decoded. - - - - V4L2_EVENT_CTRL - 3 - This event requires that the id - matches the control ID from which you want to receive events. - This event is triggered if the control's value changes, if a - button control is pressed or if the control's flags change. - This event has a &v4l2-event-ctrl; associated with it. This struct - contains much of the same information as &v4l2-queryctrl; and - &v4l2-control;. - - If the event is generated due to a call to &VIDIOC-S-CTRL; or - &VIDIOC-S-EXT-CTRLS;, then the event will not be sent to - the file handle that called the ioctl function. This prevents - nasty feedback loops. If you do want to get the - event, then set the V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK - flag. - - - This event type will ensure that no information is lost when - more events are raised than there is room internally. In that - case the &v4l2-event-ctrl; of the second-oldest event is kept, - but the changes field of the - second-oldest event is ORed with the changes - field of the oldest event. - - - - V4L2_EVENT_FRAME_SYNC - 4 - - Triggered immediately when the reception of a - frame has begun. This event has a - &v4l2-event-frame-sync; associated with it. - - If the hardware needs to be stopped in the case of a - buffer underrun it might not be able to generate this event. - In such cases the frame_sequence - field in &v4l2-event-frame-sync; will not be incremented. This - causes two consecutive frame sequence numbers to have n times - frame interval in between them. - - - - V4L2_EVENT_SOURCE_CHANGE - 5 - - This event is triggered when a source parameter change is - detected during runtime by the video device. It can be a - runtime resolution change triggered by a video decoder or the - format change happening on an input connector. - This event requires that the id - matches the input index (when used with a video device node) - or the pad index (when used with a subdevice node) from which - you want to receive events. - - This event has a &v4l2-event-src-change; associated - with it. The changes bitfield denotes - what has changed for the subscribed pad. If multiple events - occurred before application could dequeue them, then the changes - will have the ORed value of all the events generated. - - - - V4L2_EVENT_MOTION_DET - 6 - - Triggered whenever the motion detection state for one or more of the regions - changes. This event has a &v4l2-event-motion-det; associated with it. - - - - V4L2_EVENT_PRIVATE_START - 0x08000000 - Base event number for driver-private events. - - - -
- Event Flags diff --git a/Documentation/IPMI.txt b/Documentation/IPMI.txt index 653d5d739d7ff5b55dbcd8d606b5d7e1da51a99f..31d1d658827f082f66c88c3147e99be3321635cf 100644 --- a/Documentation/IPMI.txt +++ b/Documentation/IPMI.txt @@ -505,7 +505,10 @@ at module load time (for a module) with: The addresses are normal I2C addresses. The adapter is the string name of the adapter, as shown in /sys/class/i2c-adapter/i2c-/name. -It is *NOT* i2c- itself. +It is *NOT* i2c- itself. Also, the comparison is done ignoring +spaces, so if the name is "This is an I2C chip" you can say +adapter_name=ThisisanI2cchip. This is because it's hard to pass in +spaces in kernel parameters. The debug flags are bit flags for each BMC found, they are: IPMI messages: 1, driver state: 2, timing: 4, I2C probe: 8 diff --git a/Documentation/Makefile b/Documentation/Makefile index 6883a1b9b351d9942112a7c450d53f3152453a4a..bc0548201755e1a8d29614bccbd78fcbbe5a34ae 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -1,4 +1,4 @@ -subdir-y := accounting arm auxdisplay blackfin connector \ +subdir-y := accounting auxdisplay blackfin connector \ filesystems filesystems ia64 laptops mic misc-devices \ networking pcmcia prctl ptp spi timers vDSO video4linux \ watchdog diff --git a/Documentation/PCI/MSI-HOWTO.txt b/Documentation/PCI/MSI-HOWTO.txt index 0d920d54536df88b07f5b46637cfa32b5970100e..1179850f453c66849c1808f83b0955a63cd33ad1 100644 --- a/Documentation/PCI/MSI-HOWTO.txt +++ b/Documentation/PCI/MSI-HOWTO.txt @@ -353,7 +353,7 @@ retry: rc = pci_enable_msix_range(adapter->pdev, adapter->msix_entries, maxvec, maxvec); /* - * -ENOSPC is the only error code allowed to be analized + * -ENOSPC is the only error code allowed to be analyzed */ if (rc == -ENOSPC) { if (maxvec == 1) @@ -370,7 +370,7 @@ retry: return rc; } -Note how pci_enable_msix_range() return value is analized for a fallback - +Note how pci_enable_msix_range() return value is analyzed for a fallback - any error code other than -ENOSPC indicates a fatal error and should not be retried. @@ -486,7 +486,7 @@ during development. If your device supports both MSI-X and MSI capabilities, you should use the MSI-X facilities in preference to the MSI facilities. As mentioned above, MSI-X supports any number of interrupts between 1 and 2048. -In constrast, MSI is restricted to a maximum of 32 interrupts (and +In contrast, MSI is restricted to a maximum of 32 interrupts (and must be a power of two). In addition, the MSI interrupt vectors must be allocated consecutively, so the system might not be able to allocate as many vectors for MSI as it could for MSI-X. On some platforms, MSI @@ -501,18 +501,9 @@ necessary to disable interrupts (Linux guarantees the same interrupt will not be re-entered). If a device uses multiple interrupts, the driver must disable interrupts while the lock is held. If the device sends a different interrupt, the driver will deadlock trying to recursively -acquire the spinlock. - -There are two solutions. The first is to take the lock with -spin_lock_irqsave() or spin_lock_irq() (see -Documentation/DocBook/kernel-locking). The second is to specify -IRQF_DISABLED to request_irq() so that the kernel runs the entire -interrupt routine with interrupts disabled. - -If your MSI interrupt routine does not hold the lock for the whole time -it is running, the first solution may be best. The second solution is -normally preferred as it avoids making two transitions from interrupt -disabled to enabled and back again. +acquire the spinlock. Such deadlocks can be avoided by using +spin_lock_irqsave() or spin_lock_irq() which disable local interrupts +and acquire the lock (see Documentation/DocBook/kernel-locking). 4.6 How to tell whether MSI/MSI-X is enabled on a device diff --git a/Documentation/PCI/pci-error-recovery.txt b/Documentation/PCI/pci-error-recovery.txt index 898ded24510de978c287116e03094e4a052d48da..ac26869c7db450dc2861fb0b617ef8045610c3b2 100644 --- a/Documentation/PCI/pci-error-recovery.txt +++ b/Documentation/PCI/pci-error-recovery.txt @@ -256,7 +256,7 @@ STEP 4: Slot Reset ------------------ In response to a return value of PCI_ERS_RESULT_NEED_RESET, the -the platform will peform a slot reset on the requesting PCI device(s). +the platform will perform a slot reset on the requesting PCI device(s). The actual steps taken by a platform to perform a slot reset will be platform-dependent. Upon completion of slot reset, the platform will call the device slot_reset() callback. diff --git a/Documentation/PCI/pcieaer-howto.txt b/Documentation/PCI/pcieaer-howto.txt index 26d3d945c3c21aa965cd9b48c49cc42abf09df3f..b4987c0bcb20fd86e6fe8b989fab15d8b6fbed51 100644 --- a/Documentation/PCI/pcieaer-howto.txt +++ b/Documentation/PCI/pcieaer-howto.txt @@ -66,8 +66,8 @@ hardware (mostly chipsets) has root ports that cannot obtain the reporting source ID. nosourceid=n by default. 2.3 AER error output -When a PCI-E AER error is captured, an error message will be outputed to -console. If it's a correctable error, it is outputed as a warning. +When a PCI-E AER error is captured, an error message will be outputted to +console. If it's a correctable error, it is outputted as a warning. Otherwise, it is printed as an error. So users could choose different log level to filter out correctable error messages. diff --git a/Documentation/acpi/enumeration.txt b/Documentation/acpi/enumeration.txt index 750401f9134190a210c8c24089a08ca9cb16559c..15dfce708ebf6ec3263ac0d66ff2b6f3a57471d4 100644 --- a/Documentation/acpi/enumeration.txt +++ b/Documentation/acpi/enumeration.txt @@ -253,7 +253,7 @@ input driver: GPIO support ~~~~~~~~~~~~ ACPI 5 introduced two new resources to describe GPIO connections: GpioIo -and GpioInt. These resources are used be used to pass GPIO numbers used by +and GpioInt. These resources can be used to pass GPIO numbers used by the device to the driver. ACPI 5.1 extended this with _DSD (Device Specific Data) which made it possible to name the GPIOs among other things. diff --git a/Documentation/acpi/gpio-properties.txt b/Documentation/acpi/gpio-properties.txt index ae36fcf86dc7213c8b1a72bb0e698f89e51c878f..f35dad11f0de78955a2e4661f8ef5c9d51eb27d9 100644 --- a/Documentation/acpi/gpio-properties.txt +++ b/Documentation/acpi/gpio-properties.txt @@ -1,9 +1,9 @@ _DSD Device Properties Related to GPIO -------------------------------------- -With the release of ACPI 5.1 and the _DSD configuration objecte names -can finally be given to GPIOs (and other things as well) returned by -_CRS. Previously, we were only able to use an integer index to find +With the release of ACPI 5.1, the _DSD configuration object finally +allows names to be given to GPIOs (and other things as well) returned +by _CRS. Previously, we were only able to use an integer index to find the corresponding GPIO, which is pretty error prone (it depends on the _CRS output ordering, for example). diff --git a/Documentation/arm/00-INDEX b/Documentation/arm/00-INDEX index 8edb9007844e1b6c6f49655b4e71df4da845eff1..dea011c8d7c718a8ff7a37dea7d35a81d0f67271 100644 --- a/Documentation/arm/00-INDEX +++ b/Documentation/arm/00-INDEX @@ -10,8 +10,6 @@ IXP4xx - Intel IXP4xx Network processor. Makefile - Build sourcefiles as part of the Documentation-build for arm -msm/ - - MSM specific documentation Netwinder - Netwinder specific documentation Porting diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting index 371814a36719f7979402f41c63ca3609fcdae6a9..83c1df2fc758ba4b92dd900785ed7f0920ad9619 100644 --- a/Documentation/arm/Booting +++ b/Documentation/arm/Booting @@ -58,13 +58,18 @@ serial format options as described in -------------------------- Existing boot loaders: OPTIONAL -New boot loaders: MANDATORY +New boot loaders: MANDATORY except for DT-only platforms The boot loader should detect the machine type its running on by some method. Whether this is a hard coded value or some algorithm that looks at the connected hardware is beyond the scope of this document. The boot loader must ultimately be able to provide a MACH_TYPE_xxx -value to the kernel. (see linux/arch/arm/tools/mach-types). +value to the kernel. (see linux/arch/arm/tools/mach-types). This +should be passed to the kernel in register r1. + +For DT-only platforms, the machine type will be determined by device +tree. set the machine type to all ones (~0). This is not strictly +necessary, but assures that it will not match any existing types. 4. Setup boot data ------------------ diff --git a/Documentation/arm/Makefile b/Documentation/arm/Makefile deleted file mode 100644 index 732c77050cff6737bfb7538dd832fa4957d257eb..0000000000000000000000000000000000000000 --- a/Documentation/arm/Makefile +++ /dev/null @@ -1 +0,0 @@ -subdir-y := SH-Mobile diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index 17453794fca5d518be980b1350784a9e3a11ecd2..18a775d101723be46320bbf475f04c066b4c3ea2 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README @@ -96,6 +96,11 @@ EBU Armada family 88F6820 88F6828 + Armada 390/398 Flavors: + 88F6920 + 88F6928 + Product infos: http://www.marvell.com/embedded-processors/armada-39x/ + Armada XP Flavors: MV78230 MV78260 diff --git a/Documentation/arm/README b/Documentation/arm/README index aea34095cdcfcc5c61a8fe7254cb2e8761992e90..9d1e5b2c92e62b7554492b27516611b4adedc2dd 100644 --- a/Documentation/arm/README +++ b/Documentation/arm/README @@ -185,13 +185,20 @@ Kernel entry (head.S) board devices are used, or the device is setup, and provides that machine specific "personality." - This fine-grained machine specific selection is controlled by the machine - type ID, which acts both as a run-time and a compile-time code selection - method. + For platforms that support device tree (DT), the machine selection is + controlled at runtime by passing the device tree blob to the kernel. At + compile-time, support for the machine type must be selected. This allows for + a single multiplatform kernel build to be used for several machine types. - You can register a new machine via the web site at: + For platforms that do not use device tree, this machine selection is + controlled by the machine type ID, which acts both as a run-time and a + compile-time code selection method. You can register a new machine via the + web site at: + Note: Please do not register a machine type for DT-only platforms. If your + platform is DT-only, you do not need a registered machine type. + --- Russell King (15/03/2004) diff --git a/Documentation/arm/SH-Mobile/Makefile b/Documentation/arm/SH-Mobile/Makefile deleted file mode 100644 index bca8a7ef6bbef153e89edfcc8d27eeb79c5f22be..0000000000000000000000000000000000000000 --- a/Documentation/arm/SH-Mobile/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# List of programs to build -hostprogs-y := vrl4 - -# Tell kbuild to always build the programs -always := $(hostprogs-y) - -HOSTCFLAGS_vrl4.o += -I$(objtree)/usr/include -I$(srctree)/tools/include diff --git a/Documentation/arm/SH-Mobile/vrl4.c b/Documentation/arm/SH-Mobile/vrl4.c deleted file mode 100644 index f4cd8ad4e720c9346799487b3829db5bb3294f16..0000000000000000000000000000000000000000 --- a/Documentation/arm/SH-Mobile/vrl4.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * vrl4 format generator - * - * Copyright (C) 2010 Simon Horman - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -/* - * usage: vrl4 < zImage > out - * dd if=out of=/dev/sdx bs=512 seek=1 # Write the image to sector 1 - * - * Reads a zImage from stdin and writes a vrl4 image to stdout. - * In practice this means writing a padded vrl4 header to stdout followed - * by the zImage. - * - * The padding places the zImage at ALIGN bytes into the output. - * The vrl4 uses ALIGN + START_BASE as the start_address. - * This is where the mask ROM will jump to after verifying the header. - * - * The header sets copy_size to min(sizeof(zImage), MAX_BOOT_PROG_LEN) + ALIGN. - * That is, the mask ROM will load the padded header (ALIGN bytes) - * And then MAX_BOOT_PROG_LEN bytes of the image, or the entire image, - * whichever is smaller. - * - * The zImage is not modified in any way. - */ - -#define _BSD_SOURCE -#include -#include -#include -#include -#include -#include - -struct hdr { - uint32_t magic1; - uint32_t reserved1; - uint32_t magic2; - uint32_t reserved2; - uint16_t copy_size; - uint16_t boot_options; - uint32_t reserved3; - uint32_t start_address; - uint32_t reserved4; - uint32_t reserved5; - char reserved6[308]; -}; - -#define DECLARE_HDR(h) \ - struct hdr (h) = { \ - .magic1 = htole32(0xea000000), \ - .reserved1 = htole32(0x56), \ - .magic2 = htole32(0xe59ff008), \ - .reserved3 = htole16(0x1) } - -/* Align to 512 bytes, the MMCIF sector size */ -#define ALIGN_BITS 9 -#define ALIGN (1 << ALIGN_BITS) - -#define START_BASE 0xe55b0000 - -/* - * With an alignment of 512 the header uses the first sector. - * There is a 128 sector (64kbyte) limit on the data loaded by the mask ROM. - * So there are 127 sectors left for the boot programme. But in practice - * Only a small portion of a zImage is needed, 16 sectors should be more - * than enough. - * - * Note that this sets how much of the zImage is copied by the mask ROM. - * The entire zImage is present after the header and is loaded - * by the code in the boot program (which is the first portion of the zImage). - */ -#define MAX_BOOT_PROG_LEN (16 * 512) - -#define ROUND_UP(x) ((x + ALIGN - 1) & ~(ALIGN - 1)) - -static ssize_t do_read(int fd, void *buf, size_t count) -{ - size_t offset = 0; - ssize_t l; - - while (offset < count) { - l = read(fd, buf + offset, count - offset); - if (!l) - break; - if (l < 0) { - if (errno == EAGAIN || errno == EWOULDBLOCK) - continue; - perror("read"); - return -1; - } - offset += l; - } - - return offset; -} - -static ssize_t do_write(int fd, const void *buf, size_t count) -{ - size_t offset = 0; - ssize_t l; - - while (offset < count) { - l = write(fd, buf + offset, count - offset); - if (l < 0) { - if (errno == EAGAIN || errno == EWOULDBLOCK) - continue; - perror("write"); - return -1; - } - offset += l; - } - - return offset; -} - -static ssize_t write_zero(int fd, size_t len) -{ - size_t i = len; - - while (i--) { - const char x = 0; - if (do_write(fd, &x, 1) < 0) - return -1; - } - - return len; -} - -int main(void) -{ - DECLARE_HDR(hdr); - char boot_program[MAX_BOOT_PROG_LEN]; - size_t aligned_hdr_len, alligned_prog_len; - ssize_t prog_len; - - prog_len = do_read(0, boot_program, sizeof(boot_program)); - if (prog_len <= 0) - return -1; - - aligned_hdr_len = ROUND_UP(sizeof(hdr)); - hdr.start_address = htole32(START_BASE + aligned_hdr_len); - alligned_prog_len = ROUND_UP(prog_len); - hdr.copy_size = htole16(aligned_hdr_len + alligned_prog_len); - - if (do_write(1, &hdr, sizeof(hdr)) < 0) - return -1; - if (write_zero(1, aligned_hdr_len - sizeof(hdr)) < 0) - return -1; - - if (do_write(1, boot_program, prog_len) < 0) - return 1; - - /* Write out the rest of the kernel */ - while (1) { - prog_len = do_read(0, boot_program, sizeof(boot_program)); - if (prog_len < 0) - return 1; - if (prog_len == 0) - break; - if (do_write(1, boot_program, prog_len) < 0) - return 1; - } - - return 0; -} diff --git a/Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt b/Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt deleted file mode 100644 index efff8ae2713dddf05420b2ca52f993f99ad20813..0000000000000000000000000000000000000000 --- a/Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt +++ /dev/null @@ -1,29 +0,0 @@ -ROM-able zImage boot from MMC ------------------------------ - -An ROM-able zImage compiled with ZBOOT_ROM_MMCIF may be written to MMC and -SuperH Mobile ARM will to boot directly from the MMCIF hardware block. - -This is achieved by the mask ROM loading the first portion of the image into -MERAM and then jumping to it. This portion contains loader code which -copies the entire image to SDRAM and jumps to it. From there the zImage -boot code proceeds as normal, uncompressing the image into its final -location and then jumping to it. - -This code has been tested on an AP4EB board using the developer 1A eMMC -boot mode which is configured using the following jumper settings. -The board used for testing required a patched mask ROM in order for -this mode to function. - - 8 7 6 5 4 3 2 1 - x|x|x|x|x| |x| -S4 -+-+-+-+-+-+-+- - | | | | |x| |x on - -The zImage must be written to the MMC card at sector 1 (512 bytes) in -vrl4 format. A utility vrl4 is supplied to accomplish this. - -e.g. - vrl4 < zImage | dd of=/dev/sdX bs=512 seek=1 - -A dual-voltage MMC 4.0 card was used for testing. diff --git a/Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt b/Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt deleted file mode 100644 index 441959846e1abd11b3767741db70568d4d579c28..0000000000000000000000000000000000000000 --- a/Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt +++ /dev/null @@ -1,42 +0,0 @@ -ROM-able zImage boot from eSD ------------------------------ - -An ROM-able zImage compiled with ZBOOT_ROM_SDHI may be written to eSD and -SuperH Mobile ARM will to boot directly from the SDHI hardware block. - -This is achieved by the mask ROM loading the first portion of the image into -MERAM and then jumping to it. This portion contains loader code which -copies the entire image to SDRAM and jumps to it. From there the zImage -boot code proceeds as normal, uncompressing the image into its final -location and then jumping to it. - -This code has been tested on an mackerel board using the developer 1A eSD -boot mode which is configured using the following jumper settings. - - 8 7 6 5 4 3 2 1 - x|x|x|x| |x|x| -S4 -+-+-+-+-+-+-+- - | | | |x| | |x on - -The eSD card needs to be present in SDHI slot 1 (CN7). -As such S1 and S33 also need to be configured as per -the notes in arch/arm/mach-shmobile/board-mackerel.c. - -A partial zImage must be written to physical partition #1 (boot) -of the eSD at sector 0 in vrl4 format. A utility vrl4 is supplied to -accomplish this. - -e.g. - vrl4 < zImage | dd of=/dev/sdX bs=512 count=17 - -A full copy of _the same_ zImage should be written to physical partition #1 -(boot) of the eSD at sector 0. This should _not_ be in vrl4 format. - - vrl4 < zImage | dd of=/dev/sdX bs=512 - -Note: The commands above assume that the physical partition has been -switched. No such facility currently exists in the Linux Kernel. - -Physical partitions are described in the eSD specification. At the time of -writing they are not the same as partitions that are typically configured -using fdisk and visible through /proc/partitions diff --git a/Documentation/arm/msm/gpiomux.txt b/Documentation/arm/msm/gpiomux.txt deleted file mode 100644 index 67a81620adf67d7830a5037d21a47ad48e2acdfc..0000000000000000000000000000000000000000 --- a/Documentation/arm/msm/gpiomux.txt +++ /dev/null @@ -1,176 +0,0 @@ -This document provides an overview of the msm_gpiomux interface, which -is used to provide gpio pin multiplexing and configuration on mach-msm -targets. - -History -======= - -The first-generation API for gpio configuration & multiplexing on msm -is the function gpio_tlmm_config(). This function has a few notable -shortcomings, which led to its deprecation and replacement by gpiomux: - -The 'disable' parameter: Setting the second parameter to -gpio_tlmm_config to GPIO_CFG_DISABLE tells the peripheral -processor in charge of the subsystem to perform a look-up into a -low-power table and apply the low-power/sleep setting for the pin. -As the msm family evolved this became problematic. Not all pins -have sleep settings, not all peripheral processors will accept requests -to apply said sleep settings, and not all msm targets have their gpio -subsystems managed by a peripheral processor. In order to get consistent -behavior on all targets, drivers are forced to ignore this parameter, -rendering it useless. - -The 'direction' flag: for all mux-settings other than raw-gpio (0), -the output-enable bit of a gpio is hard-wired to a known -input (usually VDD or ground). For those settings, the direction flag -is meaningless at best, and deceptive at worst. In addition, using the -direction flag to change output-enable (OE) directly can cause trouble in -gpiolib, which has no visibility into gpio direction changes made -in this way. Direction control in gpio mode should be made through gpiolib. - -Key Features of gpiomux -======================= - -- A consistent interface across all generations of msm. Drivers can expect -the same results on every target. -- gpiomux plays nicely with gpiolib. Functions that should belong to gpiolib -are left to gpiolib and not duplicated here. gpiomux is written with the -intent that gpio_chips will call gpiomux reference-counting methods -from their request() and free() hooks, providing full integration. -- Tabular configuration. Instead of having to call gpio_tlmm_config -hundreds of times, gpio configuration is placed in a single table. -- Per-gpio sleep. Each gpio is individually reference counted, allowing only -those lines which are in use to be put in high-power states. -- 0 means 'do nothing': all flags are designed so that the default memset-zero -equates to a sensible default of 'no configuration', preventing users -from having to provide hundreds of 'no-op' configs for unused or -unwanted lines. - -Usage -===== - -To use gpiomux, provide configuration information for relevant gpio lines -in the msm_gpiomux_configs table. Since a 0 equates to "unconfigured", -only those lines to be managed by gpiomux need to be specified. Here -is a completely fictional example: - -struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { - [12] = { - .active = GPIOMUX_VALID | GPIOMUX_DRV_8MA | GPIOMUX_FUNC_1, - .suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN, - }, - [34] = { - .suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN, - }, -}; - -To indicate that a gpio is in use, call msm_gpiomux_get() to increase -its reference count. To decrease the reference count, call msm_gpiomux_put(). - -The effect of this configuration is as follows: - -When the system boots, gpios 12 and 34 will be initialized with their -'suspended' configurations. All other gpios, which were left unconfigured, -will not be touched. - -When msm_gpiomux_get() is called on gpio 12 to raise its reference count -above 0, its active configuration will be applied. Since no other gpio -line has a valid active configuration, msm_gpiomux_get() will have no -effect on any other line. - -When msm_gpiomux_put() is called on gpio 12 or 34 to drop their reference -count to 0, their suspended configurations will be applied. -Since no other gpio line has a valid suspended configuration, no other -gpio line will be effected by msm_gpiomux_put(). Since gpio 34 has no valid -active configuration, this is effectively a no-op for gpio 34 as well, -with one small caveat, see the section "About Output-Enable Settings". - -All of the GPIOMUX_VALID flags may seem like unnecessary overhead, but -they address some important issues. As unused entries (all those -except 12 and 34) are zero-filled, gpiomux needs a way to distinguish -the used fields from the unused. In addition, the all-zero pattern -is a valid configuration! Therefore, gpiomux defines an additional bit -which is used to indicate when a field is used. This has the pleasant -side-effect of allowing calls to msm_gpiomux_write to use '0' to indicate -that a value should not be changed: - - msm_gpiomux_write(0, GPIOMUX_VALID, 0); - -replaces the active configuration of gpio 0 with an all-zero configuration, -but leaves the suspended configuration as it was. - -Static Configurations -===================== - -To install a static configuration, which is applied at boot and does -not change after that, install a configuration with a suspended component -but no active component, as in the previous example: - - [34] = { - .suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN, - }, - -The suspended setting is applied during boot, and the lack of any valid -active setting prevents any other setting from being applied at runtime. -If other subsystems attempting to access the line is a concern, one could -*really* anchor the configuration down by calling msm_gpiomux_get on the -line at initialization to move the line into active mode. With the line -held, it will never be re-suspended, and with no valid active configuration, -no new configurations will be applied. - -But then, if having other subsystems grabbing for the line is truly a concern, -it should be reserved with gpio_request instead, which carries an implicit -msm_gpiomux_get. - -gpiomux and gpiolib -=================== - -It is expected that msm gpio_chips will call msm_gpiomux_get() and -msm_gpiomux_put() from their request and free hooks, like this fictional -example: - -static int request(struct gpio_chip *chip, unsigned offset) -{ - return msm_gpiomux_get(chip->base + offset); -} - -static void free(struct gpio_chip *chip, unsigned offset) -{ - msm_gpiomux_put(chip->base + offset); -} - - ...somewhere in a gpio_chip declaration... - .request = request, - .free = free, - -This provides important functionality: -- It guarantees that a gpio line will have its 'active' config applied - when the line is requested, and will not be suspended while the line - remains requested; and -- It guarantees that gpio-direction settings from gpiolib behave sensibly. - See "About Output-Enable Settings." - -This mechanism allows for "auto-request" of gpiomux lines via gpiolib -when it is suitable. Drivers wishing more exact control are, of course, -free to also use msm_gpiomux_set and msm_gpiomux_get. - -About Output-Enable Settings -============================ - -Some msm targets do not have the ability to query the current gpio -configuration setting. This means that changes made to the output-enable -(OE) bit by gpiolib cannot be consistently detected and preserved by gpiomux. -Therefore, when gpiomux applies a configuration setting, any direction -settings which may have been applied by gpiolib are lost and the default -input settings are re-applied. - -For this reason, drivers should not assume that gpio direction settings -continue to hold if they free and then re-request a gpio. This seems like -common sense - after all, anybody could have obtained the line in the -meantime - but it needs saying. - -This also means that calls to msm_gpiomux_write will reset the OE bit, -which means that if the gpio line is held by a client of gpiolib and -msm_gpiomux_write is called, the direction setting has been lost and -gpiolib's internal state has been broken. -Release gpio lines before reconfiguring them. diff --git a/Documentation/arm64/acpi_object_usage.txt b/Documentation/arm64/acpi_object_usage.txt new file mode 100644 index 0000000000000000000000000000000000000000..a6e1a1805e514985b5cdfb7d46c39872378e8757 --- /dev/null +++ b/Documentation/arm64/acpi_object_usage.txt @@ -0,0 +1,593 @@ +ACPI Tables +----------- +The expectations of individual ACPI tables are discussed in the list that +follows. + +If a section number is used, it refers to a section number in the ACPI +specification where the object is defined. If "Signature Reserved" is used, +the table signature (the first four bytes of the table) is the only portion +of the table recognized by the specification, and the actual table is defined +outside of the UEFI Forum (see Section 5.2.6 of the specification). + +For ACPI on arm64, tables also fall into the following categories: + + -- Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT + + -- Recommended: BERT, EINJ, ERST, HEST, SSDT + + -- Optional: BGRT, CPEP, CSRT, DRTM, ECDT, FACS, FPDT, MCHI, MPST, + MSCT, RASF, SBST, SLIT, SPMI, SRAT, TCPA, TPM2, UEFI + + -- Not supported: BOOT, DBG2, DBGP, DMAR, ETDT, HPET, IBFT, IVRS, + LPIT, MSDM, RSDT, SLIC, WAET, WDAT, WDRT, WPBT + + +Table Usage for ARMv8 Linux +----- ---------------------------------------------------------------- +BERT Section 18.3 (signature == "BERT") + == Boot Error Record Table == + Must be supplied if RAS support is provided by the platform. It + is recommended this table be supplied. + +BOOT Signature Reserved (signature == "BOOT") + == simple BOOT flag table == + Microsoft only table, will not be supported. + +BGRT Section 5.2.22 (signature == "BGRT") + == Boot Graphics Resource Table == + Optional, not currently supported, with no real use-case for an + ARM server. + +CPEP Section 5.2.18 (signature == "CPEP") + == Corrected Platform Error Polling table == + Optional, not currently supported, and not recommended until such + time as ARM-compatible hardware is available, and the specification + suitably modified. + +CSRT Signature Reserved (signature == "CSRT") + == Core System Resources Table == + Optional, not currently supported. + +DBG2 Signature Reserved (signature == "DBG2") + == DeBuG port table 2 == + Microsoft only table, will not be supported. + +DBGP Signature Reserved (signature == "DBGP") + == DeBuG Port table == + Microsoft only table, will not be supported. + +DSDT Section 5.2.11.1 (signature == "DSDT") + == Differentiated System Description Table == + A DSDT is required; see also SSDT. + + ACPI tables contain only one DSDT but can contain one or more SSDTs, + which are optional. Each SSDT can only add to the ACPI namespace, + but cannot modify or replace anything in the DSDT. + +DMAR Signature Reserved (signature == "DMAR") + == DMA Remapping table == + x86 only table, will not be supported. + +DRTM Signature Reserved (signature == "DRTM") + == Dynamic Root of Trust for Measurement table == + Optional, not currently supported. + +ECDT Section 5.2.16 (signature == "ECDT") + == Embedded Controller Description Table == + Optional, not currently supported, but could be used on ARM if and + only if one uses the GPE_BIT field to represent an IRQ number, since + there are no GPE blocks defined in hardware reduced mode. This would + need to be modified in the ACPI specification. + +EINJ Section 18.6 (signature == "EINJ") + == Error Injection table == + This table is very useful for testing platform response to error + conditions; it allows one to inject an error into the system as + if it had actually occurred. However, this table should not be + shipped with a production system; it should be dynamically loaded + and executed with the ACPICA tools only during testing. + +ERST Section 18.5 (signature == "ERST") + == Error Record Serialization Table == + On a platform supports RAS, this table must be supplied if it is not + UEFI-based; if it is UEFI-based, this table may be supplied. When this + table is not present, UEFI run time service will be utilized to save + and retrieve hardware error information to and from a persistent store. + +ETDT Signature Reserved (signature == "ETDT") + == Event Timer Description Table == + Obsolete table, will not be supported. + +FACS Section 5.2.10 (signature == "FACS") + == Firmware ACPI Control Structure == + It is unlikely that this table will be terribly useful. If it is + provided, the Global Lock will NOT be used since it is not part of + the hardware reduced profile, and only 64-bit address fields will + be considered valid. + +FADT Section 5.2.9 (signature == "FACP") + == Fixed ACPI Description Table == + Required for arm64. + + The HW_REDUCED_ACPI flag must be set. All of the fields that are + to be ignored when HW_REDUCED_ACPI is set are expected to be set to + zero. + + If an FACS table is provided, the X_FIRMWARE_CTRL field is to be + used, not FIRMWARE_CTRL. + + If PSCI is used (as is recommended), make sure that ARM_BOOT_ARCH is + filled in properly -- that the PSCI_COMPLIANT flag is set and that + PSCI_USE_HVC is set or unset as needed (see table 5-37). + + For the DSDT that is also required, the X_DSDT field is to be used, + not the DSDT field. + +FPDT Section 5.2.23 (signature == "FPDT") + == Firmware Performance Data Table == + Optional, not currently supported. + +GTDT Section 5.2.24 (signature == "GTDT") + == Generic Timer Description Table == + Required for arm64. + +HEST Section 18.3.2 (signature == "HEST") + == Hardware Error Source Table == + Until further error source types are defined, use only types 6 (AER + Root Port), 7 (AER Endpoint), 8 (AER Bridge), or 9 (Generic Hardware + Error Source). Firmware first error handling is possible if and only + if Trusted Firmware is being used on arm64. + + Must be supplied if RAS support is provided by the platform. It + is recommended this table be supplied. + +HPET Signature Reserved (signature == "HPET") + == High Precision Event timer Table == + x86 only table, will not be supported. + +IBFT Signature Reserved (signature == "IBFT") + == iSCSI Boot Firmware Table == + Microsoft defined table, support TBD. + +IVRS Signature Reserved (signature == "IVRS") + == I/O Virtualization Reporting Structure == + x86_64 (AMD) only table, will not be supported. + +LPIT Signature Reserved (signature == "LPIT") + == Low Power Idle Table == + x86 only table as of ACPI 5.1; future versions have been adapted for + use with ARM and will be recommended in order to support ACPI power + management. + +MADT Section 5.2.12 (signature == "APIC") + == Multiple APIC Description Table == + Required for arm64. Only the GIC interrupt controller structures + should be used (types 0xA - 0xE). + +MCFG Signature Reserved (signature == "MCFG") + == Memory-mapped ConFiGuration space == + If the platform supports PCI/PCIe, an MCFG table is required. + +MCHI Signature Reserved (signature == "MCHI") + == Management Controller Host Interface table == + Optional, not currently supported. + +MPST Section 5.2.21 (signature == "MPST") + == Memory Power State Table == + Optional, not currently supported. + +MSDM Signature Reserved (signature == "MSDM") + == Microsoft Data Management table == + Microsoft only table, will not be supported. + +MSCT Section 5.2.19 (signature == "MSCT") + == Maximum System Characteristic Table == + Optional, not currently supported. + +RASF Section 5.2.20 (signature == "RASF") + == RAS Feature table == + Optional, not currently supported. + +RSDP Section 5.2.5 (signature == "RSD PTR") + == Root System Description PoinTeR == + Required for arm64. + +RSDT Section 5.2.7 (signature == "RSDT") + == Root System Description Table == + Since this table can only provide 32-bit addresses, it is deprecated + on arm64, and will not be used. + +SBST Section 5.2.14 (signature == "SBST") + == Smart Battery Subsystem Table == + Optional, not currently supported. + +SLIC Signature Reserved (signature == "SLIC") + == Software LIcensing table == + Microsoft only table, will not be supported. + +SLIT Section 5.2.17 (signature == "SLIT") + == System Locality distance Information Table == + Optional in general, but required for NUMA systems. + +SPCR Signature Reserved (signature == "SPCR") + == Serial Port Console Redirection table == + Required for arm64. + +SPMI Signature Reserved (signature == "SPMI") + == Server Platform Management Interface table == + Optional, not currently supported. + +SRAT Section 5.2.16 (signature == "SRAT") + == System Resource Affinity Table == + Optional, but if used, only the GICC Affinity structures are read. + To support NUMA, this table is required. + +SSDT Section 5.2.11.2 (signature == "SSDT") + == Secondary System Description Table == + These tables are a continuation of the DSDT; these are recommended + for use with devices that can be added to a running system, but can + also serve the purpose of dividing up device descriptions into more + manageable pieces. + + An SSDT can only ADD to the ACPI namespace. It cannot modify or + replace existing device descriptions already in the namespace. + + These tables are optional, however. ACPI tables should contain only + one DSDT but can contain many SSDTs. + +TCPA Signature Reserved (signature == "TCPA") + == Trusted Computing Platform Alliance table == + Optional, not currently supported, and may need changes to fully + interoperate with arm64. + +TPM2 Signature Reserved (signature == "TPM2") + == Trusted Platform Module 2 table == + Optional, not currently supported, and may need changes to fully + interoperate with arm64. + +UEFI Signature Reserved (signature == "UEFI") + == UEFI ACPI data table == + Optional, not currently supported. No known use case for arm64, + at present. + +WAET Signature Reserved (signature == "WAET") + == Windows ACPI Emulated devices Table == + Microsoft only table, will not be supported. + +WDAT Signature Reserved (signature == "WDAT") + == Watch Dog Action Table == + Microsoft only table, will not be supported. + +WDRT Signature Reserved (signature == "WDRT") + == Watch Dog Resource Table == + Microsoft only table, will not be supported. + +WPBT Signature Reserved (signature == "WPBT") + == Windows Platform Binary Table == + Microsoft only table, will not be supported. + +XSDT Section 5.2.8 (signature == "XSDT") + == eXtended System Description Table == + Required for arm64. + + +ACPI Objects +------------ +The expectations on individual ACPI objects are discussed in the list that +follows: + +Name Section Usage for ARMv8 Linux +---- ------------ ------------------------------------------------- +_ADR 6.1.1 Use as needed. + +_BBN 6.5.5 Use as needed; PCI-specific. + +_BDN 6.5.3 Optional; not likely to be used on arm64. + +_CCA 6.2.17 This method should be defined for all bus masters + on arm64. While cache coherency is assumed, making + it explicit ensures the kernel will set up DMA as + it should. + +_CDM 6.2.1 Optional, to be used only for processor devices. + +_CID 6.1.2 Use as needed. + +_CLS 6.1.3 Use as needed. + +_CRS 6.2.2 Required on arm64. + +_DCK 6.5.2 Optional; not likely to be used on arm64. + +_DDN 6.1.4 This field can be used for a device name. However, + it is meant for DOS device names (e.g., COM1), so be + careful of its use across OSes. + +_DEP 6.5.8 Use as needed. + +_DIS 6.2.3 Optional, for power management use. + +_DLM 5.7.5 Optional. + +_DMA 6.2.4 Optional. + +_DSD 6.2.5 To be used with caution. If this object is used, try + to use it within the constraints already defined by the + Device Properties UUID. Only in rare circumstances + should it be necessary to create a new _DSD UUID. + + In either case, submit the _DSD definition along with + any driver patches for discussion, especially when + device properties are used. A driver will not be + considered complete without a corresponding _DSD + description. Once approved by kernel maintainers, + the UUID or device properties must then be registered + with the UEFI Forum; this may cause some iteration as + more than one OS will be registering entries. + +_DSM Do not use this method. It is not standardized, the + return values are not well documented, and it is + currently a frequent source of error. + +_DSW 7.2.1 Use as needed; power management specific. + +_EDL 6.3.1 Optional. + +_EJD 6.3.2 Optional. + +_EJx 6.3.3 Optional. + +_FIX 6.2.7 x86 specific, not used on arm64. + +\_GL 5.7.1 This object is not to be used in hardware reduced + mode, and therefore should not be used on arm64. + +_GLK 6.5.7 This object requires a global lock be defined; there + is no global lock on arm64 since it runs in hardware + reduced mode. Hence, do not use this object on arm64. + +\_GPE 5.3.1 This namespace is for x86 use only. Do not use it + on arm64. + +_GSB 6.2.7 Optional. + +_HID 6.1.5 Use as needed. This is the primary object to use in + device probing, though _CID and _CLS may also be used. + +_HPP 6.2.8 Optional, PCI specific. + +_HPX 6.2.9 Optional, PCI specific. + +_HRV 6.1.6 Optional, use as needed to clarify device behavior; in + some cases, this may be easier to use than _DSD. + +_INI 6.5.1 Not required, but can be useful in setting up devices + when UEFI leaves them in a state that may not be what + the driver expects before it starts probing. + +_IRC 7.2.15 Use as needed; power management specific. + +_LCK 6.3.4 Optional. + +_MAT 6.2.10 Optional; see also the MADT. + +_MLS 6.1.7 Optional, but highly recommended for use in + internationalization. + +_OFF 7.1.2 It is recommended to define this method for any device + that can be turned on or off. + +_ON 7.1.3 It is recommended to define this method for any device + that can be turned on or off. + +\_OS 5.7.3 This method will return "Linux" by default (this is + the value of the macro ACPI_OS_NAME on Linux). The + command line parameter acpi_os= can be used + to set it to some other value. + +_OSC 6.2.11 This method can be a global method in ACPI (i.e., + \_SB._OSC), or it may be associated with a specific + device (e.g., \_SB.DEV0._OSC), or both. When used + as a global method, only capabilities published in + the ACPI specification are allowed. When used as + a device-specific method, the process described for + using _DSD MUST be used to create an _OSC definition; + out-of-process use of _OSC is not allowed. That is, + submit the device-specific _OSC usage description as + part of the kernel driver submission, get it approved + by the kernel community, then register it with the + UEFI Forum. + +\_OSI 5.7.2 Deprecated on ARM64. Any invocation of this method + will print a warning on the console and return false. + That is, as far as ACPI firmware is concerned, _OSI + cannot be used to determine what sort of system is + being used or what functionality is provided. The + _OSC method is to be used instead. + +_OST 6.3.5 Optional. + +_PDC 8.4.1 Deprecated, do not use on arm64. + +\_PIC 5.8.1 The method should not be used. On arm64, the only + interrupt model available is GIC. + +_PLD 6.1.8 Optional. + +\_PR 5.3.1 This namespace is for x86 use only on legacy systems. + Do not use it on arm64. + +_PRS 6.2.12 Optional. + +_PRT 6.2.13 Required as part of the definition of all PCI root + devices. + +_PRW 7.2.13 Use as needed; power management specific. + +_PRx 7.2.8-11 Use as needed; power management specific. If _PR0 is + defined, _PR3 must also be defined. + +_PSC 7.2.6 Use as needed; power management specific. + +_PSE 7.2.7 Use as needed; power management specific. + +_PSW 7.2.14 Use as needed; power management specific. + +_PSx 7.2.2-5 Use as needed; power management specific. If _PS0 is + defined, _PS3 must also be defined. If clocks or + regulators need adjusting to be consistent with power + usage, change them in these methods. + +\_PTS 7.3.1 Use as needed; power management specific. + +_PXM 6.2.14 Optional. + +_REG 6.5.4 Use as needed. + +\_REV 5.7.4 Always returns the latest version of ACPI supported. + +_RMV 6.3.6 Optional. + +\_SB 5.3.1 Required on arm64; all devices must be defined in this + namespace. + +_SEG 6.5.6 Use as needed; PCI-specific. + +\_SI 5.3.1, Optional. + 9.1 + +_SLI 6.2.15 Optional; recommended when SLIT table is in use. + +_STA 6.3.7, It is recommended to define this method for any device + 7.1.4 that can be turned on or off. + +_SRS 6.2.16 Optional; see also _PRS. + +_STR 6.1.10 Recommended for conveying device names to end users; + this is preferred over using _DDN. + +_SUB 6.1.9 Use as needed; _HID or _CID are preferred. + +_SUN 6.1.11 Optional. + +\_Sx 7.3.2 Use as needed; power management specific. + +_SxD 7.2.16-19 Use as needed; power management specific. + +_SxW 7.2.20-24 Use as needed; power management specific. + +_SWS 7.3.3 Use as needed; power management specific; this may + require specification changes for use on arm64. + +\_TTS 7.3.4 Use as needed; power management specific. + +\_TZ 5.3.1 Optional. + +_UID 6.1.12 Recommended for distinguishing devices of the same + class; define it if at all possible. + +\_WAK 7.3.5 Use as needed; power management specific. + + +ACPI Event Model +---------------- +Do not use GPE block devices; these are not supported in the hardware reduced +profile used by arm64. Since there are no GPE blocks defined for use on ARM +platforms, GPIO-signaled interrupts should be used for creating system events. + + +ACPI Processor Control +---------------------- +Section 8 of the ACPI specification is currently undergoing change that +should be completed in the 6.0 version of the specification. Processor +performance control will be handled differently for arm64 at that point +in time. Processor aggregator devices (section 8.5) will not be used, +for example, but another similar mechanism instead. + +While UEFI constrains what we can say until the release of 6.0, it is +recommended that CPPC (8.4.5) be used as the primary model. This will +still be useful into the future. C-states and P-states will still be +provided, but most of the current design work appears to favor CPPC. + +Further, it is essential that the ARMv8 SoC provide a fully functional +implementation of PSCI; this will be the only mechanism supported by ACPI +to control CPU power state (including secondary CPU booting). + +More details will be provided on the release of the ACPI 6.0 specification. + + +ACPI System Address Map Interfaces +---------------------------------- +In Section 15 of the ACPI specification, several methods are mentioned as +possible mechanisms for conveying memory resource information to the kernel. +For arm64, we will only support UEFI for booting with ACPI, hence the UEFI +GetMemoryMap() boot service is the only mechanism that will be used. + + +ACPI Platform Error Interfaces (APEI) +------------------------------------- +The APEI tables supported are described above. + +APEI requires the equivalent of an SCI and an NMI on ARMv8. The SCI is used +to notify the OSPM of errors that have occurred but can be corrected and the +system can continue correct operation, even if possibly degraded. The NMI is +used to indicate fatal errors that cannot be corrected, and require immediate +attention. + +Since there is no direct equivalent of the x86 SCI or NMI, arm64 handles +these slightly differently. The SCI is handled as a normal GPIO-signaled +interrupt; given that these are corrected (or correctable) errors being +reported, this is sufficient. The NMI is emulated as the highest priority +GPIO-signaled interrupt possible. This implies some caution must be used +since there could be interrupts at higher privilege levels or even interrupts +at the same priority as the emulated NMI. In Linux, this should not be the +case but one should be aware it could happen. + + +ACPI Objects Not Supported on ARM64 +----------------------------------- +While this may change in the future, there are several classes of objects +that can be defined, but are not currently of general interest to ARM servers. + +These are not supported: + + -- Section 9.2: ambient light sensor devices + + -- Section 9.3: battery devices + + -- Section 9.4: lids (e.g., laptop lids) + + -- Section 9.8.2: IDE controllers + + -- Section 9.9: floppy controllers + + -- Section 9.10: GPE block devices + + -- Section 9.15: PC/AT RTC/CMOS devices + + -- Section 9.16: user presence detection devices + + -- Section 9.17: I/O APIC devices; all GICs must be enumerable via MADT + + -- Section 9.18: time and alarm devices (see 9.15) + + +ACPI Objects Not Yet Implemented +-------------------------------- +While these objects have x86 equivalents, and they do make some sense in ARM +servers, there is either no hardware available at present, or in some cases +there may not yet be a non-ARM implementation. Hence, they are currently not +implemented though that may change in the future. + +Not yet implemented are: + + -- Section 10: power source and power meter devices + + -- Section 11: thermal management + + -- Section 12: embedded controllers interface + + -- Section 13: SMBus interfaces + + -- Section 17: NUMA support (prototypes have been submitted for + review) diff --git a/Documentation/arm64/arm-acpi.txt b/Documentation/arm64/arm-acpi.txt new file mode 100644 index 0000000000000000000000000000000000000000..570a4f8e1a010ab7ec91f1ec9abb2aafc0a56e52 --- /dev/null +++ b/Documentation/arm64/arm-acpi.txt @@ -0,0 +1,505 @@ +ACPI on ARMv8 Servers +--------------------- +ACPI can be used for ARMv8 general purpose servers designed to follow +the ARM SBSA (Server Base System Architecture) [0] and SBBR (Server +Base Boot Requirements) [1] specifications. Please note that the SBBR +can be retrieved simply by visiting [1], but the SBSA is currently only +available to those with an ARM login due to ARM IP licensing concerns. + +The ARMv8 kernel implements the reduced hardware model of ACPI version +5.1 or later. Links to the specification and all external documents +it refers to are managed by the UEFI Forum. The specification is +available at http://www.uefi.org/specifications and documents referenced +by the specification can be found via http://www.uefi.org/acpi. + +If an ARMv8 system does not meet the requirements of the SBSA and SBBR, +or cannot be described using the mechanisms defined in the required ACPI +specifications, then ACPI may not be a good fit for the hardware. + +While the documents mentioned above set out the requirements for building +industry-standard ARMv8 servers, they also apply to more than one operating +system. The purpose of this document is to describe the interaction between +ACPI and Linux only, on an ARMv8 system -- that is, what Linux expects of +ACPI and what ACPI can expect of Linux. + + +Why ACPI on ARM? +---------------- +Before examining the details of the interface between ACPI and Linux, it is +useful to understand why ACPI is being used. Several technologies already +exist in Linux for describing non-enumerable hardware, after all. In this +section we summarize a blog post [2] from Grant Likely that outlines the +reasoning behind ACPI on ARMv8 servers. Actually, we snitch a good portion +of the summary text almost directly, to be honest. + +The short form of the rationale for ACPI on ARM is: + +-- ACPI’s bytecode (AML) allows the platform to encode hardware behavior, + while DT explicitly does not support this. For hardware vendors, being + able to encode behavior is a key tool used in supporting operating + system releases on new hardware. + +-- ACPI’s OSPM defines a power management model that constrains what the + platform is allowed to do into a specific model, while still providing + flexibility in hardware design. + +-- In the enterprise server environment, ACPI has established bindings (such + as for RAS) which are currently used in production systems. DT does not. + Such bindings could be defined in DT at some point, but doing so means ARM + and x86 would end up using completely different code paths in both firmware + and the kernel. + +-- Choosing a single interface to describe the abstraction between a platform + and an OS is important. Hardware vendors would not be required to implement + both DT and ACPI if they want to support multiple operating systems. And, + agreeing on a single interface instead of being fragmented into per OS + interfaces makes for better interoperability overall. + +-- The new ACPI governance process works well and Linux is now at the same + table as hardware vendors and other OS vendors. In fact, there is no + longer any reason to feel that ACPI is only belongs to Windows or that + Linux is in any way secondary to Microsoft in this arena. The move of + ACPI governance into the UEFI forum has significantly opened up the + specification development process, and currently, a large portion of the + changes being made to ACPI is being driven by Linux. + +Key to the use of ACPI is the support model. For servers in general, the +responsibility for hardware behaviour cannot solely be the domain of the +kernel, but rather must be split between the platform and the kernel, in +order to allow for orderly change over time. ACPI frees the OS from needing +to understand all the minute details of the hardware so that the OS doesn’t +need to be ported to each and every device individually. It allows the +hardware vendors to take responsibility for power management behaviour without +depending on an OS release cycle which is not under their control. + +ACPI is also important because hardware and OS vendors have already worked +out the mechanisms for supporting a general purpose computing ecosystem. The +infrastructure is in place, the bindings are in place, and the processes are +in place. DT does exactly what Linux needs it to when working with vertically +integrated devices, but there are no good processes for supporting what the +server vendors need. Linux could potentially get there with DT, but doing so +really just duplicates something that already works. ACPI already does what +the hardware vendors need, Microsoft won’t collaborate on DT, and hardware +vendors would still end up providing two completely separate firmware +interfaces -- one for Linux and one for Windows. + + +Kernel Compatibility +-------------------- +One of the primary motivations for ACPI is standardization, and using that +to provide backward compatibility for Linux kernels. In the server market, +software and hardware are often used for long periods. ACPI allows the +kernel and firmware to agree on a consistent abstraction that can be +maintained over time, even as hardware or software change. As long as the +abstraction is supported, systems can be updated without necessarily having +to replace the kernel. + +When a Linux driver or subsystem is first implemented using ACPI, it by +definition ends up requiring a specific version of the ACPI specification +-- it's baseline. ACPI firmware must continue to work, even though it may +not be optimal, with the earliest kernel version that first provides support +for that baseline version of ACPI. There may be a need for additional drivers, +but adding new functionality (e.g., CPU power management) should not break +older kernel versions. Further, ACPI firmware must also work with the most +recent version of the kernel. + + +Relationship with Device Tree +----------------------------- +ACPI support in drivers and subsystems for ARMv8 should never be mutually +exclusive with DT support at compile time. + +At boot time the kernel will only use one description method depending on +parameters passed from the bootloader (including kernel bootargs). + +Regardless of whether DT or ACPI is used, the kernel must always be capable +of booting with either scheme (in kernels with both schemes enabled at compile +time). + + +Booting using ACPI tables +------------------------- +The only defined method for passing ACPI tables to the kernel on ARMv8 +is via the UEFI system configuration table. Just so it is explicit, this +means that ACPI is only supported on platforms that boot via UEFI. + +When an ARMv8 system boots, it can either have DT information, ACPI tables, +or in some very unusual cases, both. If no command line parameters are used, +the kernel will try to use DT for device enumeration; if there is no DT +present, the kernel will try to use ACPI tables, but only if they are present. +In neither is available, the kernel will not boot. If acpi=force is used +on the command line, the kernel will attempt to use ACPI tables first, but +fall back to DT if there are no ACPI tables present. The basic idea is that +the kernel will not fail to boot unless it absolutely has no other choice. + +Processing of ACPI tables may be disabled by passing acpi=off on the kernel +command line; this is the default behavior. + +In order for the kernel to load and use ACPI tables, the UEFI implementation +MUST set the ACPI_20_TABLE_GUID to point to the RSDP table (the table with +the ACPI signature "RSD PTR "). If this pointer is incorrect and acpi=force +is used, the kernel will disable ACPI and try to use DT to boot instead; the +kernel has, in effect, determined that ACPI tables are not present at that +point. + +If the pointer to the RSDP table is correct, the table will be mapped into +the kernel by the ACPI core, using the address provided by UEFI. + +The ACPI core will then locate and map in all other ACPI tables provided by +using the addresses in the RSDP table to find the XSDT (eXtended System +Description Table). The XSDT in turn provides the addresses to all other +ACPI tables provided by the system firmware; the ACPI core will then traverse +this table and map in the tables listed. + +The ACPI core will ignore any provided RSDT (Root System Description Table). +RSDTs have been deprecated and are ignored on arm64 since they only allow +for 32-bit addresses. + +Further, the ACPI core will only use the 64-bit address fields in the FADT +(Fixed ACPI Description Table). Any 32-bit address fields in the FADT will +be ignored on arm64. + +Hardware reduced mode (see Section 4.1 of the ACPI 5.1 specification) will +be enforced by the ACPI core on arm64. Doing so allows the ACPI core to +run less complex code since it no longer has to provide support for legacy +hardware from other architectures. Any fields that are not to be used for +hardware reduced mode must be set to zero. + +For the ACPI core to operate properly, and in turn provide the information +the kernel needs to configure devices, it expects to find the following +tables (all section numbers refer to the ACPI 5.1 specfication): + + -- RSDP (Root System Description Pointer), section 5.2.5 + + -- XSDT (eXtended System Description Table), section 5.2.8 + + -- FADT (Fixed ACPI Description Table), section 5.2.9 + + -- DSDT (Differentiated System Description Table), section + 5.2.11.1 + + -- MADT (Multiple APIC Description Table), section 5.2.12 + + -- GTDT (Generic Timer Description Table), section 5.2.24 + + -- If PCI is supported, the MCFG (Memory mapped ConFiGuration + Table), section 5.2.6, specifically Table 5-31. + +If the above tables are not all present, the kernel may or may not be +able to boot properly since it may not be able to configure all of the +devices available. + + +ACPI Detection +-------------- +Drivers should determine their probe() type by checking for a null +value for ACPI_HANDLE, or checking .of_node, or other information in +the device structure. This is detailed further in the "Driver +Recommendations" section. + +In non-driver code, if the presence of ACPI needs to be detected at +runtime, then check the value of acpi_disabled. If CONFIG_ACPI is not +set, acpi_disabled will always be 1. + + +Device Enumeration +------------------ +Device descriptions in ACPI should use standard recognized ACPI interfaces. +These may contain less information than is typically provided via a Device +Tree description for the same device. This is also one of the reasons that +ACPI can be useful -- the driver takes into account that it may have less +detailed information about the device and uses sensible defaults instead. +If done properly in the driver, the hardware can change and improve over +time without the driver having to change at all. + +Clocks provide an excellent example. In DT, clocks need to be specified +and the drivers need to take them into account. In ACPI, the assumption +is that UEFI will leave the device in a reasonable default state, including +any clock settings. If for some reason the driver needs to change a clock +value, this can be done in an ACPI method; all the driver needs to do is +invoke the method and not concern itself with what the method needs to do +to change the clock. Changing the hardware can then take place over time +by changing what the ACPI method does, and not the driver. + +In DT, the parameters needed by the driver to set up clocks as in the example +above are known as "bindings"; in ACPI, these are known as "Device Properties" +and provided to a driver via the _DSD object. + +ACPI tables are described with a formal language called ASL, the ACPI +Source Language (section 19 of the specification). This means that there +are always multiple ways to describe the same thing -- including device +properties. For example, device properties could use an ASL construct +that looks like this: Name(KEY0, "value0"). An ACPI device driver would +then retrieve the value of the property by evaluating the KEY0 object. +However, using Name() this way has multiple problems: (1) ACPI limits +names ("KEY0") to four characters unlike DT; (2) there is no industry +wide registry that maintains a list of names, minimzing re-use; (3) +there is also no registry for the definition of property values ("value0"), +again making re-use difficult; and (4) how does one maintain backward +compatibility as new hardware comes out? The _DSD method was created +to solve precisely these sorts of problems; Linux drivers should ALWAYS +use the _DSD method for device properties and nothing else. + +The _DSM object (ACPI Section 9.14.1) could also be used for conveying +device properties to a driver. Linux drivers should only expect it to +be used if _DSD cannot represent the data required, and there is no way +to create a new UUID for the _DSD object. Note that there is even less +regulation of the use of _DSM than there is of _DSD. Drivers that depend +on the contents of _DSM objects will be more difficult to maintain over +time because of this; as of this writing, the use of _DSM is the cause +of quite a few firmware problems and is not recommended. + +Drivers should look for device properties in the _DSD object ONLY; the _DSD +object is described in the ACPI specification section 6.2.5, but this only +describes how to define the structure of an object returned via _DSD, and +how specific data structures are defined by specific UUIDs. Linux should +only use the _DSD Device Properties UUID [5]: + + -- UUID: daffd814-6eba-4d8c-8a91-bc9bbf4aa301 + + -- http://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf + +The UEFI Forum provides a mechanism for registering device properties [4] +so that they may be used across all operating systems supporting ACPI. +Device properties that have not been registered with the UEFI Forum should +not be used. + +Before creating new device properties, check to be sure that they have not +been defined before and either registered in the Linux kernel documentation +as DT bindings, or the UEFI Forum as device properties. While we do not want +to simply move all DT bindings into ACPI device properties, we can learn from +what has been previously defined. + +If it is necessary to define a new device property, or if it makes sense to +synthesize the definition of a binding so it can be used in any firmware, +both DT bindings and ACPI device properties for device drivers have review +processes. Use them both. When the driver itself is submitted for review +to the Linux mailing lists, the device property definitions needed must be +submitted at the same time. A driver that supports ACPI and uses device +properties will not be considered complete without their definitions. Once +the device property has been accepted by the Linux community, it must be +registered with the UEFI Forum [4], which will review it again for consistency +within the registry. This may require iteration. The UEFI Forum, though, +will always be the canonical site for device property definitions. + +It may make sense to provide notice to the UEFI Forum that there is the +intent to register a previously unused device property name as a means of +reserving the name for later use. Other operating system vendors will +also be submitting registration requests and this may help smooth the +process. + +Once registration and review have been completed, the kernel provides an +interface for looking up device properties in a manner independent of +whether DT or ACPI is being used. This API should be used [6]; it can +eliminate some duplication of code paths in driver probing functions and +discourage divergence between DT bindings and ACPI device properties. + + +Programmable Power Control Resources +------------------------------------ +Programmable power control resources include such resources as voltage/current +providers (regulators) and clock sources. + +With ACPI, the kernel clock and regulator framework is not expected to be used +at all. + +The kernel assumes that power control of these resources is represented with +Power Resource Objects (ACPI section 7.1). The ACPI core will then handle +correctly enabling and disabling resources as they are needed. In order to +get that to work, ACPI assumes each device has defined D-states and that these +can be controlled through the optional ACPI methods _PS0, _PS1, _PS2, and _PS3; +in ACPI, _PS0 is the method to invoke to turn a device full on, and _PS3 is for +turning a device full off. + +There are two options for using those Power Resources. They can: + + -- be managed in a _PSx method which gets called on entry to power + state Dx. + + -- be declared separately as power resources with their own _ON and _OFF + methods. They are then tied back to D-states for a particular device + via _PRx which specifies which power resources a device needs to be on + while in Dx. Kernel then tracks number of devices using a power resource + and calls _ON/_OFF as needed. + +The kernel ACPI code will also assume that the _PSx methods follow the normal +ACPI rules for such methods: + + -- If either _PS0 or _PS3 is implemented, then the other method must also + be implemented. + + -- If a device requires usage or setup of a power resource when on, the ASL + should organize that it is allocated/enabled using the _PS0 method. + + -- Resources allocated or enabled in the _PS0 method should be disabled + or de-allocated in the _PS3 method. + + -- Firmware will leave the resources in a reasonable state before handing + over control to the kernel. + +Such code in _PSx methods will of course be very platform specific. But, +this allows the driver to abstract out the interface for operating the device +and avoid having to read special non-standard values from ACPI tables. Further, +abstracting the use of these resources allows the hardware to change over time +without requiring updates to the driver. + + +Clocks +------ +ACPI makes the assumption that clocks are initialized by the firmware -- +UEFI, in this case -- to some working value before control is handed over +to the kernel. This has implications for devices such as UARTs, or SoC-driven +LCD displays, for example. + +When the kernel boots, the clocks are assumed to be set to reasonable +working values. If for some reason the frequency needs to change -- e.g., +throttling for power management -- the device driver should expect that +process to be abstracted out into some ACPI method that can be invoked +(please see the ACPI specification for further recommendations on standard +methods to be expected). The only exceptions to this are CPU clocks where +CPPC provides a much richer interface than ACPI methods. If the clocks +are not set, there is no direct way for Linux to control them. + +If an SoC vendor wants to provide fine-grained control of the system clocks, +they could do so by providing ACPI methods that could be invoked by Linux +drivers. However, this is NOT recommended and Linux drivers should NOT use +such methods, even if they are provided. Such methods are not currently +standardized in the ACPI specification, and using them could tie a kernel +to a very specific SoC, or tie an SoC to a very specific version of the +kernel, both of which we are trying to avoid. + + +Driver Recommendations +---------------------- +DO NOT remove any DT handling when adding ACPI support for a driver. The +same device may be used on many different systems. + +DO try to structure the driver so that it is data-driven. That is, set up +a struct containing internal per-device state based on defaults and whatever +else must be discovered by the driver probe function. Then, have the rest +of the driver operate off of the contents of that struct. Doing so should +allow most divergence between ACPI and DT functionality to be kept local to +the probe function instead of being scattered throughout the driver. For +example: + +static int device_probe_dt(struct platform_device *pdev) +{ + /* DT specific functionality */ + ... +} + +static int device_probe_acpi(struct platform_device *pdev) +{ + /* ACPI specific functionality */ + ... +} + +static int device_probe(struct platform_device *pdev) +{ + ... + struct device_node node = pdev->dev.of_node; + ... + + if (node) + ret = device_probe_dt(pdev); + else if (ACPI_HANDLE(&pdev->dev)) + ret = device_probe_acpi(pdev); + else + /* other initialization */ + ... + /* Continue with any generic probe operations */ + ... +} + +DO keep the MODULE_DEVICE_TABLE entries together in the driver to make it +clear the different names the driver is probed for, both from DT and from +ACPI: + +static struct of_device_id virtio_mmio_match[] = { + { .compatible = "virtio,mmio", }, + { } +}; +MODULE_DEVICE_TABLE(of, virtio_mmio_match); + +static const struct acpi_device_id virtio_mmio_acpi_match[] = { + { "LNRO0005", }, + { } +}; +MODULE_DEVICE_TABLE(acpi, virtio_mmio_acpi_match); + + +ASWG +---- +The ACPI specification changes regularly. During the year 2014, for instance, +version 5.1 was released and version 6.0 substantially completed, with most of +the changes being driven by ARM-specific requirements. Proposed changes are +presented and discussed in the ASWG (ACPI Specification Working Group) which +is a part of the UEFI Forum. + +Participation in this group is open to all UEFI members. Please see +http://www.uefi.org/workinggroup for details on group membership. + +It is the intent of the ARMv8 ACPI kernel code to follow the ACPI specification +as closely as possible, and to only implement functionality that complies with +the released standards from UEFI ASWG. As a practical matter, there will be +vendors that provide bad ACPI tables or violate the standards in some way. +If this is because of errors, quirks and fixups may be necessary, but will +be avoided if possible. If there are features missing from ACPI that preclude +it from being used on a platform, ECRs (Engineering Change Requests) should be +submitted to ASWG and go through the normal approval process; for those that +are not UEFI members, many other members of the Linux community are and would +likely be willing to assist in submitting ECRs. + + +Linux Code +---------- +Individual items specific to Linux on ARM, contained in the the Linux +source code, are in the list that follows: + +ACPI_OS_NAME This macro defines the string to be returned when + an ACPI method invokes the _OS method. On ARM64 + systems, this macro will be "Linux" by default. + The command line parameter acpi_os= + can be used to set it to some other value. The + default value for other architectures is "Microsoft + Windows NT", for example. + +ACPI Objects +------------ +Detailed expectations for ACPI tables and object are listed in the file +Documentation/arm64/acpi_object_usage.txt. + + +References +---------- +[0] http://silver.arm.com -- document ARM-DEN-0029, or newer + "Server Base System Architecture", version 2.3, dated 27 Mar 2014 + +[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0044a/Server_Base_Boot_Requirements.pdf + Document ARM-DEN-0044A, or newer: "Server Base Boot Requirements, System + Software on ARM Platforms", dated 16 Aug 2014 + +[2] http://www.secretlab.ca/archives/151, 10 Jan 2015, Copyright (c) 2015, + Linaro Ltd., written by Grant Likely. A copy of the verbatim text (apart + from formatting) is also in Documentation/arm64/why_use_acpi.txt. + +[3] AMD ACPI for Seattle platform documentation: + http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/Seattle_ACPI_Guide.pdf + +[4] http://www.uefi.org/acpi -- please see the link for the "ACPI _DSD Device + Property Registry Instructions" + +[5] http://www.uefi.org/acpi -- please see the link for the "_DSD (Device + Specific Data) Implementation Guide" + +[6] Kernel code for the unified device property interface can be found in + include/linux/property.h and drivers/base/property.c. + + +Authors +------- +Al Stone +Graeme Gregory +Hanjun Guo + +Grant Likely , for the "Why ACPI on ARM?" section diff --git a/Documentation/blackfin/Makefile b/Documentation/blackfin/Makefile index 03f78059d6f5849b7914d50a2983fb6f9d678eb9..6782c58fbc297d830fdf5a1a034b7b28ce0bce02 100644 --- a/Documentation/blackfin/Makefile +++ b/Documentation/blackfin/Makefile @@ -1,5 +1,5 @@ ifneq ($(CONFIG_BLACKFIN),) -ifneq ($(CONFIG_BFIN_GPTIMERS,) +ifneq ($(CONFIG_BFIN_GPTIMERS),) obj-m := gptimers-example.o endif endif diff --git a/Documentation/block/biodoc.txt b/Documentation/block/biodoc.txt index 5aabc08de811d49ba898d550a0c2ff98ab3964a5..fd12c0d835fd1eca07f9c3bf8ef28eb7e877d3f2 100644 --- a/Documentation/block/biodoc.txt +++ b/Documentation/block/biodoc.txt @@ -48,8 +48,7 @@ Description of Contents: - Highmem I/O support - I/O scheduler modularization 1.2 Tuning based on high level requirements/capabilities - 1.2.1 I/O Barriers - 1.2.2 Request Priority/Latency + 1.2.1 Request Priority/Latency 1.3 Direct access/bypass to lower layers for diagnostics and special device operations 1.3.1 Pre-built commands @@ -255,29 +254,12 @@ some control over i/o ordering. What kind of support exists at the generic block layer for this ? The flags and rw fields in the bio structure can be used for some tuning -from above e.g indicating that an i/o is just a readahead request, or for -marking barrier requests (discussed next), or priority settings (currently -unused). As far as user applications are concerned they would need an -additional mechanism either via open flags or ioctls, or some other upper -level mechanism to communicate such settings to block. - -1.2.1 I/O Barriers - -There is a way to enforce strict ordering for i/os through barriers. -All requests before a barrier point must be serviced before the barrier -request and any other requests arriving after the barrier will not be -serviced until after the barrier has completed. This is useful for higher -level control on write ordering, e.g flushing a log of committed updates -to disk before the corresponding updates themselves. - -A flag in the bio structure, BIO_BARRIER is used to identify a barrier i/o. -The generic i/o scheduler would make sure that it places the barrier request and -all other requests coming after it after all the previous requests in the -queue. Barriers may be implemented in different ways depending on the -driver. For more details regarding I/O barriers, please read barrier.txt -in this directory. - -1.2.2 Request Priority/Latency +from above e.g indicating that an i/o is just a readahead request, or priority +settings (currently unused). As far as user applications are concerned they +would need an additional mechanism either via open flags or ioctls, or some +other upper level mechanism to communicate such settings to block. + +1.2.1 Request Priority/Latency Todo/Under discussion: Arjan's proposed request priority scheme allows higher levels some broad @@ -906,8 +888,8 @@ queue and specific I/O schedulers. Unless stated otherwise, elevator is used to refer to both parts and I/O scheduler to specific I/O schedulers. Block layer implements generic dispatch queue in block/*.c. -The generic dispatch queue is responsible for properly ordering barrier -requests, requeueing, handling non-fs requests and all other subtleties. +The generic dispatch queue is responsible for requeueing, handling non-fs +requests and all other subtleties. Specific I/O schedulers are responsible for ordering normal filesystem requests. They can also choose to delay certain requests to improve diff --git a/Documentation/cgroups/memory.txt b/Documentation/cgroups/memory.txt index a22df3ad35fff8a43d78517f790a9822aa5d8d55..f456b4315e86d80abe8d4d0b4fbb68eeca5b4e4a 100644 --- a/Documentation/cgroups/memory.txt +++ b/Documentation/cgroups/memory.txt @@ -275,11 +275,6 @@ When oom event notifier is registered, event will be delivered. 2.7 Kernel Memory Extension (CONFIG_MEMCG_KMEM) -WARNING: Current implementation lacks reclaim support. That means allocation - attempts will fail when close to the limit even if there are plenty of - kmem available for reclaim. That makes this option unusable in real - life so DO NOT SELECT IT unless for development purposes. - With the Kernel memory extension, the Memory Controller is able to limit the amount of kernel memory used by the system. Kernel memory is fundamentally different than user memory, since it can't be swapped out, which makes it @@ -345,6 +340,9 @@ set: In this case, the admin could set up K so that the sum of all groups is never greater than the total memory, and freely set U at the cost of his QoS. + WARNING: In the current implementation, memory reclaim will NOT be + triggered for a cgroup when it hits K while staying below U, which makes + this setup impractical. U != 0, K >= U: Since kmem charges will also be fed to the user counter and reclaim will be diff --git a/Documentation/cpu-hotplug.txt b/Documentation/cpu-hotplug.txt index a0b005d2bd95ce8d0251679adc90002a6e3b4809..f9ad5e048b111297549df37cc6a6fc8bff1fc75a 100644 --- a/Documentation/cpu-hotplug.txt +++ b/Documentation/cpu-hotplug.txt @@ -108,7 +108,7 @@ Never use anything other than cpumask_t to represent bitmap of CPUs. for_each_possible_cpu - Iterate over cpu_possible_mask for_each_online_cpu - Iterate over cpu_online_mask for_each_present_cpu - Iterate over cpu_present_mask - for_each_cpu_mask(x,mask) - Iterate over some random collection of cpu mask. + for_each_cpu(x,mask) - Iterate over some random collection of cpu mask. #include get_online_cpus() and put_online_cpus(): diff --git a/Documentation/device-mapper/dm-crypt.txt b/Documentation/device-mapper/dm-crypt.txt index ad697781f9ac478477cfed76978b047685eda2b6..692171fe9da0307732b96327e10848e1d12e2e26 100644 --- a/Documentation/device-mapper/dm-crypt.txt +++ b/Documentation/device-mapper/dm-crypt.txt @@ -5,7 +5,7 @@ Device-Mapper's "crypt" target provides transparent encryption of block devices using the kernel crypto API. For a more detailed description of supported parameters see: -http://code.google.com/p/cryptsetup/wiki/DMCrypt +https://gitlab.com/cryptsetup/cryptsetup/wikis/DMCrypt Parameters: \ [<#opt_params> ] @@ -80,7 +80,7 @@ Example scripts =============== LUKS (Linux Unified Key Setup) is now the preferred way to set up disk encryption with dm-crypt using the 'cryptsetup' utility, see -http://code.google.com/p/cryptsetup/ +https://gitlab.com/cryptsetup/cryptsetup [[ #!/bin/sh diff --git a/Documentation/device-mapper/log-writes.txt b/Documentation/device-mapper/log-writes.txt new file mode 100644 index 0000000000000000000000000000000000000000..c10f30c9b534ef7eb1c8a5c838c914148a6cd105 --- /dev/null +++ b/Documentation/device-mapper/log-writes.txt @@ -0,0 +1,140 @@ +dm-log-writes +============= + +This target takes 2 devices, one to pass all IO to normally, and one to log all +of the write operations to. This is intended for file system developers wishing +to verify the integrity of metadata or data as the file system is written to. +There is a log_write_entry written for every WRITE request and the target is +able to take arbitrary data from userspace to insert into the log. The data +that is in the WRITE requests is copied into the log to make the replay happen +exactly as it happened originally. + +Log Ordering +============ + +We log things in order of completion once we are sure the write is no longer in +cache. This means that normal WRITE requests are not actually logged until the +next REQ_FLUSH request. This is to make it easier for userspace to replay the +log in a way that correlates to what is on disk and not what is in cache, to +make it easier to detect improper waiting/flushing. + +This works by attaching all WRITE requests to a list once the write completes. +Once we see a REQ_FLUSH request we splice this list onto the request and once +the FLUSH request completes we log all of the WRITEs and then the FLUSH. Only +completed WRITEs, at the time the REQ_FLUSH is issued, are added in order to +simulate the worst case scenario with regard to power failures. Consider the +following example (W means write, C means complete): + +W1,W2,W3,C3,C2,Wflush,C1,Cflush + +The log would show the following + +W3,W2,flush,W1.... + +Again this is to simulate what is actually on disk, this allows us to detect +cases where a power failure at a particular point in time would create an +inconsistent file system. + +Any REQ_FUA requests bypass this flushing mechanism and are logged as soon as +they complete as those requests will obviously bypass the device cache. + +Any REQ_DISCARD requests are treated like WRITE requests. Otherwise we would +have all the DISCARD requests, and then the WRITE requests and then the FLUSH +request. Consider the following example: + +WRITE block 1, DISCARD block 1, FLUSH + +If we logged DISCARD when it completed, the replay would look like this + +DISCARD 1, WRITE 1, FLUSH + +which isn't quite what happened and wouldn't be caught during the log replay. + +Target interface +================ + +i) Constructor + + log-writes + + dev_path : Device that all of the IO will go to normally. + log_dev_path : Device where the log entries are written to. + +ii) Status + + <#logged entries> + + #logged entries : Number of logged entries + highest allocated sector : Highest allocated sector + +iii) Messages + + mark + + You can use a dmsetup message to set an arbitrary mark in a log. + For example say you want to fsck a file system after every + write, but first you need to replay up to the mkfs to make sure + we're fsck'ing something reasonable, you would do something like + this: + + mkfs.btrfs -f /dev/mapper/log + dmsetup message log 0 mark mkfs + + + This would allow you to replay the log up to the mkfs mark and + then replay from that point on doing the fsck check in the + interval that you want. + + Every log has a mark at the end labeled "dm-log-writes-end". + +Userspace component +=================== + +There is a userspace tool that will replay the log for you in various ways. +It can be found here: https://github.com/josefbacik/log-writes + +Example usage +============= + +Say you want to test fsync on your file system. You would do something like +this: + +TABLE="0 $(blockdev --getsz /dev/sdb) log-writes /dev/sdb /dev/sdc" +dmsetup create log --table "$TABLE" +mkfs.btrfs -f /dev/mapper/log +dmsetup message log 0 mark mkfs + +mount /dev/mapper/log /mnt/btrfs-test + +dmsetup message log 0 mark fsync +md5sum /mnt/btrfs-test/foo +umount /mnt/btrfs-test + +dmsetup remove log +replay-log --log /dev/sdc --replay /dev/sdb --end-mark fsync +mount /dev/sdb /mnt/btrfs-test +md5sum /mnt/btrfs-test/foo + + +Another option is to do a complicated file system operation and verify the file +system is consistent during the entire operation. You could do this with: + +TABLE="0 $(blockdev --getsz /dev/sdb) log-writes /dev/sdb /dev/sdc" +dmsetup create log --table "$TABLE" +mkfs.btrfs -f /dev/mapper/log +dmsetup message log 0 mark mkfs + +mount /dev/mapper/log /mnt/btrfs-test + +btrfs filesystem balance /mnt/btrfs-test +umount /mnt/btrfs-test +dmsetup remove log + +replay-log --log /dev/sdc --replay /dev/sdb --end-mark mkfs +btrfsck /dev/sdb +replay-log --log /dev/sdc --replay /dev/sdb --start-mark mkfs \ + --fsck "btrfsck /dev/sdb" --check fua + +And that will replay the log until it sees a FUA request, run the fsck command +and if the fsck passes it will replay to the next FUA, until it is completed or +the fsck command exists abnormally. diff --git a/Documentation/device-mapper/switch.txt b/Documentation/device-mapper/switch.txt index 8897d04948384289b3fca54801be9676c15ce0e5..424835e57f2713df8e349883c02bce0771aa7012 100644 --- a/Documentation/device-mapper/switch.txt +++ b/Documentation/device-mapper/switch.txt @@ -47,8 +47,8 @@ consume far too much memory. Using this device-mapper switch target we can now build a two-layer device hierarchy: - Upper Tier – Determine which array member the I/O should be sent to. - Lower Tier – Load balance amongst paths to a particular member. + Upper Tier - Determine which array member the I/O should be sent to. + Lower Tier - Load balance amongst paths to a particular member. The lower tier consists of a single dm multipath device for each member. Each of these multipath devices contains the set of paths directly to diff --git a/Documentation/device-mapper/thin-provisioning.txt b/Documentation/device-mapper/thin-provisioning.txt index 2f5173500bd953b32e55134012af50ac93e46ad8..4f67578b295483bcc14d48f069c6ded3581e3f94 100644 --- a/Documentation/device-mapper/thin-provisioning.txt +++ b/Documentation/device-mapper/thin-provisioning.txt @@ -380,9 +380,6 @@ then you'll have no access to blocks mapped beyond the end. If you load a target that is bigger than before, then extra blocks will be provisioned as and when needed. -If you wish to reduce the size of your thin device and potentially -regain some space then send the 'trim' message to the pool. - ii) Status diff --git a/Documentation/device-mapper/verity.txt b/Documentation/device-mapper/verity.txt index 9884681535ee36bf03a7d7baaa54abb36360d53d..e15bc1a0fb98ab23563681210cc6ed1865234816 100644 --- a/Documentation/device-mapper/verity.txt +++ b/Documentation/device-mapper/verity.txt @@ -11,6 +11,7 @@ Construction Parameters + [<#opt_params> ] This is the type of the on-disk hash format. @@ -62,6 +63,22 @@ Construction Parameters The hexadecimal encoding of the salt value. +<#opt_params> + Number of optional parameters. If there are no optional parameters, + the optional paramaters section can be skipped or #opt_params can be zero. + Otherwise #opt_params is the number of following arguments. + + Example of optional parameters section: + 1 ignore_corruption + +ignore_corruption + Log corrupted blocks, but allow read operations to proceed normally. + +restart_on_corruption + Restart the system when a corrupted block is discovered. This option is + not compatible with ignore_corruption and requires user space support to + avoid restart loops. + Theory of operation =================== @@ -125,7 +142,7 @@ block boundary) are the hash blocks which are stored a depth at a time The full specification of kernel parameters and on-disk metadata format is available at the cryptsetup project's wiki page - http://code.google.com/p/cryptsetup/wiki/DMVerity + https://gitlab.com/cryptsetup/cryptsetup/wikis/DMVerity Status ====== @@ -142,7 +159,7 @@ Set up a device: A command line tool veritysetup is available to compute or verify the hash tree or activate the kernel device. This is available from -the cryptsetup upstream repository http://code.google.com/p/cryptsetup/ +the cryptsetup upstream repository https://gitlab.com/cryptsetup/cryptsetup/ (as a libcryptsetup extension). Create hash on the device: diff --git a/Documentation/devicetree/bindings/arc/pct.txt b/Documentation/devicetree/bindings/arc/pct.txt new file mode 100644 index 0000000000000000000000000000000000000000..7b9588444f20b7a15cf9e317f243ae616f4631d8 --- /dev/null +++ b/Documentation/devicetree/bindings/arc/pct.txt @@ -0,0 +1,20 @@ +* ARC Performance Counters + +The ARC700 can be configured with a pipeline performance monitor for counting +CPU and cache events like cache misses and hits. Like conventional PCT there +are 100+ hardware conditions dynamically mapped to upto 32 counters + +Note that: + * The ARC 700 PCT does not support interrupts; although HW events may be + counted, the HW events themselves cannot serve as a trigger for a sample. + +Required properties: + +- compatible : should contain + "snps,arc700-pct" + +Example: + +pmu { + compatible = "snps,arc700-pct"; +}; diff --git a/Documentation/devicetree/bindings/arc/pmu.txt b/Documentation/devicetree/bindings/arc/pmu.txt deleted file mode 100644 index 49d517340de353fb19e51754a33797381ad090d3..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/arc/pmu.txt +++ /dev/null @@ -1,24 +0,0 @@ -* ARC Performance Monitor Unit - -The ARC 700 can be configured with a pipeline performance monitor for counting -CPU and cache events like cache misses and hits. - -Note that: - * ARC 700 refers to a family of ARC processor cores; - - There is only one type of PMU available for the whole family; - - The PMU may support different sets of events; supported events are probed - at boot time, as required by the reference manual. - - * The ARC 700 PMU does not support interrupts; although HW events may be - counted, the HW events themselves cannot serve as a trigger for a sample. - -Required properties: - -- compatible : should contain - "snps,arc700-pmu" - -Example: - -pmu { - compatible = "snps,arc700-pmu"; -}; diff --git a/Documentation/devicetree/bindings/arm/al,alpine.txt b/Documentation/devicetree/bindings/arm/al,alpine.txt new file mode 100644 index 0000000000000000000000000000000000000000..f404a4f9b165592b62562aea0c45b52ba19e477a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/al,alpine.txt @@ -0,0 +1,88 @@ +Annapurna Labs Alpine Platform Device Tree Bindings +--------------------------------------------------------------- + +Boards in the Alpine family shall have the following properties: + +* Required root node properties: +compatible: must contain "al,alpine" + +* Example: + +/ { + model = "Annapurna Labs Alpine Dev Board"; + compatible = "al,alpine"; + + ... +} + +* CPU node: + +The Alpine platform includes cortex-a15 cores. +enable-method: must be "al,alpine-smp" to allow smp [1] + +Example: + +cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "al,alpine-smp"; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; +}; + + +* Alpine CPU resume registers + +The CPU resume register are used to define required resume address after +reset. + +Properties: +- compatible : Should contain "al,alpine-cpu-resume". +- reg : Offset and length of the register set for the device + +Example: + +cpu_resume { + compatible = "al,alpine-cpu-resume"; + reg = <0xfbff5ed0 0x30>; +}; + +* Alpine System-Fabric Service Registers + +The System-Fabric Service Registers allow various operation on CPU and +system fabric, like powering CPUs off. + +Properties: +- compatible : Should contain "al,alpine-sysfabric-service" and "syscon". +- reg : Offset and length of the register set for the device + +Example: + +nb_service { + compatible = "al,alpine-sysfabric-service", "syscon"; + reg = <0xfb070000 0x10000>; +}; + +[1] arm/cpu-enable-method/al,alpine-smp diff --git a/Documentation/devicetree/bindings/arm/altera.txt b/Documentation/devicetree/bindings/arm/altera.txt new file mode 100644 index 0000000000000000000000000000000000000000..558735aacca8981d0392fb1f3e0df3f3d50cf28b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera.txt @@ -0,0 +1,14 @@ +Altera's SoCFPGA platform device tree bindings +--------------------------------------------- + +Boards with Cyclone 5 SoC: +Required root node properties: +compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + +Boards with Arria 5 SoC: +Required root node properties: +compatible = "altr,socfpga-arria5", "altr,socfpga"; + +Boards with Arria 10 SoC: +Required root node properties: +compatible = "altr,socfpga-arria10", "altr,socfpga"; diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 8fe815046140becdbc594545d6677b8800b6a541..973884a1bacff8b9619b07f708367bf664fe7673 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -8,3 +8,7 @@ Boards with the Amlogic Meson6 SoC shall have the following properties: Boards with the Amlogic Meson8 SoC shall have the following properties: Required root node property: compatible: "amlogic,meson8"; + +Board compatible values: + - "geniatech,atv1200" + - "minix,neo-x8" diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index 256b4d8bab7b93d49330c7db5334eb05e8979904..e774128935d5c37ec88b8130ed667c5b4ff133df 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -17,7 +17,10 @@ to deliver its interrupts via SPIs. - interrupts : Interrupt list for secure, non-secure, virtual and hypervisor timers, in that order. -- clock-frequency : The frequency of the main counter, in Hz. Optional. +- clock-frequency : The frequency of the main counter, in Hz. Should be present + only where necessary to work around broken firmware which does not configure + CNTFRQ on all CPUs to a uniform correct value. Use of this property is + strongly discouraged; fix your firmware unless absolutely impossible. - always-on : a boolean property. If present, the timer is powered through an always-on power domain, therefore it never loses context. @@ -46,7 +49,8 @@ Example: - compatible : Should at least contain "arm,armv7-timer-mem". -- clock-frequency : The frequency of the main counter, in Hz. Optional. +- clock-frequency : The frequency of the main counter, in Hz. Should be present + only when firmware has not configured the MMIO CNTFRQ registers. - reg : The control frame base address. diff --git a/Documentation/devicetree/bindings/arm/armada-39x.txt b/Documentation/devicetree/bindings/arm/armada-39x.txt new file mode 100644 index 0000000000000000000000000000000000000000..53d4ff9ea8ad452705b6623cf63291af947318ce --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-39x.txt @@ -0,0 +1,20 @@ +Marvell Armada 39x Platforms Device Tree Bindings +------------------------------------------------- + +Boards with a SoC of the Marvell Armada 39x family shall have the +following property: + +Required root node property: + + - compatible: must contain "marvell,armada390" + +In addition, boards using the Marvell Armada 398 SoC shall have the +following property before the previous one: + +Required root node property: + +compatible: must contain "marvell,armada398" + +Example: + +compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt index ad319f84f56018ba1297676c2a69586864a6b4e0..2e99b5b57350d06a43f4fbed97cde970116b595f 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt @@ -46,10 +46,12 @@ PIT Timer required properties: shared across all System Controller members. System Timer (ST) required properties: -- compatible: Should be "atmel,at91rm9200-st" +- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" - reg: Should contain registers location and length - interrupts: Should contain interrupt for the ST which is the IRQ line shared across all System Controller members. +Its subnodes can be: +- watchdog: compatible should be "atmel,at91rm9200-wdt" TC/TCLIB Timer required properties: - compatible: Should be "atmel,-tcb". diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method rename to Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm/bcm11351.txt rename to Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.txt diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm21664.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm/bcm21664.txt rename to Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.txt diff --git a/Documentation/devicetree/bindings/arm/bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm2835.txt rename to Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt diff --git a/Documentation/devicetree/bindings/arm/bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm4708.txt rename to Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm/bcm63138.txt rename to Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt diff --git a/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/brcm-brcmstb.txt rename to Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm/cygnus.txt rename to Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.txt diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt index f28d82bbbc56b3f3dff7716ede2f200f315d8e70..3c5c631328d3b6cbb4d7c9edefddf936347a545e 100644 --- a/Documentation/devicetree/bindings/arm/cci.txt +++ b/Documentation/devicetree/bindings/arm/cci.txt @@ -94,8 +94,11 @@ specific to ARM. - compatible Usage: required Value type: - Definition: must be "arm,cci-400-pmu" - + Definition: Must contain one of: + "arm,cci-400-pmu,r0" + "arm,cci-400-pmu,r1" + "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has + secure acces to CCI registers - reg: Usage: required Value type: Integer cells. A register entry, expressed diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index a3089359aaa6e58dfdf9588995d72b53ff2d1938..88602b75418e841a66d568d59652707eeb41bb4a 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -61,7 +61,6 @@ Example: compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; - coresight-default-sink; clocks = <&oscclk6a>; clock-names = "apb_pclk"; port { diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp new file mode 100644 index 0000000000000000000000000000000000000000..c2e0cc5e4cfdd39e08d4e34f06cf9c4a6d04e8f6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp @@ -0,0 +1,52 @@ +======================================================== +Secondary CPU enable-method "al,alpine-smp" binding +======================================================== + +This document describes the "al,alpine-smp" method for +enabling secondary CPUs. To apply to all CPUs, a single +"al,alpine-smp" enable method should be defined in the +"cpus" node. + +Enable method name: "al,alpine-smp" +Compatible machines: "al,alpine" +Compatible CPUs: "arm,cortex-a15" +Related properties: (none) + +Note: +This enable method requires valid nodes compatible with +"al,alpine-cpu-resume" and "al,alpine-nb-service"[1]. + +Example: + +cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "al,alpine-smp"; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; +}; + +-- +[1] arm/al,alpine.txt diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 8b9e0a95de317e5369932d612ac131be8ac0a641..6aa331d11c5e3e042ff2e0ec495d39e26fe0681c 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -192,6 +192,7 @@ nodes to be present and contain the properties described below. "brcm,brahma-b15" "marvell,armada-375-smp" "marvell,armada-380-smp" + "marvell,armada-390-smp" "marvell,armada-xp-smp" "qcom,gcc-msm8660" "qcom,kpss-acc-v1" diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index 1e097037349c326a22e3f07abb3e3aca9d78d0ce..5da38c5ed476ee2248432314c0bf886305f6cc13 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -22,6 +22,9 @@ Optional Properties: - pclkN, clkN: Pairs of parent of input clock and input clock to the devices in this power domain. Maximum of 4 pairs (N = 0 to 3) are supported currently. + - asbN: Clocks required by asynchronous bridges (ASB) present in + the power domain. These clock should be enabled during power + domain on/off operations. - power-domains: phandle pointing to the parent power domain, for more details see Documentation/devicetree/bindings/power/power_domain.txt diff --git a/Documentation/devicetree/bindings/arm/geniatech.txt b/Documentation/devicetree/bindings/arm/geniatech.txt deleted file mode 100644 index 74ccba40b73bdf131fdeed51bb3671ab40ead78f..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/arm/geniatech.txt +++ /dev/null @@ -1,5 +0,0 @@ -Geniatech platforms device tree bindings -------------------------------------------- - -Geniatech ATV1200 - - compatible = "geniatech,atv1200" diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt index 1e0d21201d3aa7a02390fac92013bc3905d88b12..2da059a4790cb3c62365bedae458c5565589b225 100644 --- a/Documentation/devicetree/bindings/arm/gic.txt +++ b/Documentation/devicetree/bindings/arm/gic.txt @@ -18,6 +18,8 @@ Main node required properties: "arm,arm11mp-gic" "brcm,brahma-b15-gic" "arm,arm1176jzf-devchip-gic" + "qcom,msm-8660-qgic" + "qcom,msm-qgic2" - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The type shall be a and the value shall be 3. diff --git a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt index 925ecbf6e7b7af23681aca4a413553265b41fb0e..4f40ff3fee4b102aa6b4ec460a2b7e0e4bc1a09f 100644 --- a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt +++ b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt @@ -42,6 +42,7 @@ board. Currently known boards are: "lacie,cloudbox" "lacie,inetspace_v2" "lacie,laplug" +"lacie,nas2big" "lacie,netspace_lite_v2" "lacie,netspace_max_v2" "lacie,netspace_mini_v2" diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt new file mode 100644 index 0000000000000000000000000000000000000000..06df04cc827a5eaba364f86f6800d1c0a84773d5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt @@ -0,0 +1,84 @@ +QCOM Idle States for cpuidle driver + +ARM provides idle-state node to define the cpuidle states, as defined in [1]. +cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle +states. Idle states have different enter/exit latency and residency values. +The idle states supported by the QCOM SoC are defined as - + + * Standby + * Retention + * Standalone Power Collapse (Standalone PC or SPC) + * Power Collapse (PC) + +Standby: Standby does a little more in addition to architectural clock gating. +When the WFI instruction is executed the ARM core would gate its internal +clocks. In addition to gating the clocks, QCOM cpus use this instruction as a +trigger to execute the SPM state machine. The SPM state machine waits for the +interrupt to trigger the core back in to active. This triggers the cache +hierarchy to enter standby states, when all cpus are idle. An interrupt brings +the SPM state machine out of its wait, the next step is to ensure that the +cache hierarchy is also out of standby, and then the cpu is allowed to resume +execution. This state is defined as a generic ARM WFI state by the ARM cpuidle +driver and is not defined in the DT. The SPM state machine should be +configured to execute this state by default and after executing every other +state below. + +Retention: Retention is a low power state where the core is clock gated and +the memory and the registers associated with the core are retained. The +voltage may be reduced to the minimum value needed to keep the processor +registers active. The SPM should be configured to execute the retention +sequence and would wait for interrupt, before restoring the cpu to execution +state. Retention may have a slightly higher latency than Standby. + +Standalone PC: A cpu can power down and warmboot if there is a sufficient time +between the time it enters idle and the next known wake up. SPC mode is used +to indicate a core entering a power down state without consulting any other +cpu or the system resources. This helps save power only on that core. The SPM +sequence for this idle state is programmed to power down the supply to the +core, wait for the interrupt, restore power to the core, and ensure the +system state including cache hierarchy is ready before allowing core to +resume. Applying power and resetting the core causes the core to warmboot +back into Elevation Level (EL) which trampolines the control back to the +kernel. Entering a power down state for the cpu, needs to be done by trapping +into a EL. Failing to do so, would result in a crash enforced by the warm boot +code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to +be flushed in s/w, before powering down the core. + +Power Collapse: This state is similar to the SPC mode, but distinguishes +itself in that the cpu acknowledges and permits the SoC to enter deeper sleep +modes. In a hierarchical power domain SoC, this means L2 and other caches can +be flushed, system bus, clocks - lowered, and SoC main XO clock gated and +voltages reduced, provided all cpus enter this state. Since the span of low +power modes possible at this state is vast, the exit latency and the residency +of this low power mode would be considered high even though at a cpu level, +this essentially is cpu power down. The SPM in this state also may handshake +with the Resource power manager (RPM) processor in the SoC to indicate a +complete application processor subsystem shut down. + +The idle-state for QCOM SoCs are distinguished by the compatible property of +the idle-states device node. + +The devicetree representation of the idle state should be - + +Required properties: + +- compatible: Must be one of - + "qcom,idle-state-ret", + "qcom,idle-state-spc", + "qcom,idle-state-pc", + and "arm,idle-state". + +Other required and optional properties are specified in [1]. + +Example: + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; + +[1]. Documentation/devicetree/bindings/arm/idle-states.txt diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt index 1505fb8e131a889e4a62111c808cad57466f34bb..ae4afc6dcfe0a851a6264f50d633584f4f3a6cca 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt @@ -2,22 +2,31 @@ SPM AVS Wrapper 2 (SAW2) The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -micro-controller that transitions a piece of hardware (like a processor or +power-controller that transitions a piece of hardware (like a processor or subsystem) into and out of low power modes via a direct connection to the PMIC. It can also be wired up to interact with other processors in the system, notifying them when a low power state is entered or exited. +Multiple revisions of the SAW hardware are supported using these Device Nodes. +SAW2 revisions differ in the register offset and configuration data. Also, the +same revision of the SAW in different SoCs may have different configuration +data due the the differences in hardware capabilities. Hence the SoC name, the +version of the SAW hardware in that SoC and the distinction between cpu (big +or Little) or cache, may be needed to uniquely identify the SAW register +configuration and initialization data. The compatible string is used to +indicate this parameter. + PROPERTIES - compatible: Usage: required Value type: - Definition: shall contain "qcom,saw2". A more specific value should be - one of: - "qcom,saw2-v1" - "qcom,saw2-v1.1" - "qcom,saw2-v2" - "qcom,saw2-v2.1" + Definition: Must have + "qcom,saw2" + A more specific value could be one of: + "qcom,apq8064-saw2-v1.1-cpu" + "qcom,msm8974-saw2-v2.1-cpu" + "qcom,apq8084-saw2-v2.1-cpu" - reg: Usage: required @@ -26,10 +35,23 @@ PROPERTIES the register region. An optional second element specifies the base address and size of the alias register region. +- regulator: + Usage: optional + Value type: boolean + Definition: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached + to. -Example: +Example 1: - regulator@2099000 { + power-controller@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + +Example 2: + saw0: power-controller@f9089000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; }; diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt index 74607b6c111763cd4e3174da9bb62817f59fe79f..5e10c345548f56b18422c9995b6fe0bdaa33d7b0 100644 --- a/Documentation/devicetree/bindings/arm/msm/timer.txt +++ b/Documentation/devicetree/bindings/arm/msm/timer.txt @@ -9,11 +9,17 @@ Properties: "qcom,scss-timer" - scorpion subsystem - interrupts : Interrupts for the debug timer, the first general purpose - timer, and optionally a second general purpose timer in that - order. + timer, and optionally a second general purpose timer, and + optionally as well, 2 watchdog interrupts, in that order. - reg : Specifies the base address of the timer registers. +- clocks: Reference to the parent clocks, one per output clock. The parents + must appear in the same order as the clock names. + +- clock-names: The name of the clocks as free-form strings. They should be in + the same order as the clocks. + - clock-frequency : The frequency of the debug timer and the general purpose timer(s) in Hz in that order. @@ -29,9 +35,13 @@ Example: compatible = "qcom,scss-timer", "qcom,msm-timer"; interrupts = <1 1 0x301>, <1 2 0x301>, - <1 3 0x301>; + <1 3 0x301>, + <1 4 0x301>, + <1 5 0x301>; reg = <0x0200a000 0x100>; clock-frequency = <19200000>, <32768>; + clocks = <&sleep_clk>; + clock-names = "sleep"; cpu-offset = <0x40000>; }; diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt new file mode 100644 index 0000000000000000000000000000000000000000..3a4e5901ce31b0b8f12324f05951876fb4311c7d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -0,0 +1,79 @@ +OMAP Control Module bindings + +Control Module contains miscellaneous features under it based on SoC type. +Pincontrol is one common feature, and it has a specialized support +described in [1]. Typically some clock nodes are also under control module. +Syscon is used to share register level access to drivers external to +control module driver itself. + +See [2] for documentation about clock/clockdomain nodes. + +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +[2] Documentation/devicetree/bindings/clock/ti/* + +Required properties: +- compatible: Must be one of: + "ti,am3-scm" + "ti,am4-scm" + "ti,dm814-scrm" + "ti,dm816-scrm" + "ti,omap2-scm" + "ti,omap3-scm" + "ti,omap4-scm-core" + "ti,omap4-scm-padconf-core" + "ti,omap5-scm-core" + "ti,omap5-scm-padconf-core" + "ti,dra7-scm-core" +- reg: Contains Control Module register address range + (base address and length) + +Optional properties: +- clocks: clocks for this module +- clockdomains: clockdomains for this module + +Examples: + +scm: scm@2000 { + compatible = "ti,omap3-scm", "simple-bus"; + reg = <0x2000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + omap3_pmx_core: pinmux@30 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0x30 0x230>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x330>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; +} + +&scm_clocks { + mcbsp5_mux_fck: mcbsp5_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x02d8>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt index 974624ea68f67d3f16df404bccb57f587ac8a82e..161448da959d26edeb19de7db2561564c4c473dc 100644 --- a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt +++ b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt @@ -6,6 +6,7 @@ provided by Arteris. Required properties: - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family Should be "ti,omap4-l3-noc" for OMAP4 family + Should be "ti,omap5-l3-noc" for OMAP5 family Should be "ti,dra7-l3-noc" for DRA7 family Should be "ti,am4372-l3-noc" for AM43 family - reg: Contains L3 register address range for each noc domain. diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt new file mode 100644 index 0000000000000000000000000000000000000000..b4f8a16e7e3b35a746894fc12633893b7741da3c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/l4.txt @@ -0,0 +1,26 @@ +L4 interconnect bindings + +These bindings describe the OMAP SoCs L4 interconnect bus. + +Required properties: +- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus + Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus + Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus + Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus + Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus + Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus + Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus + Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus + Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus + Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus + Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus +- ranges : contains the IO map range for the bus + +Examples: + +l4: l4@48000000 { + compatible "ti,omap2-l4", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x100000>; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index 79074dac684abfd6eec2239ef2a128955cd1641f..3eb6d7afff14395229b36e349f13c52e87a96be8 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -10,14 +10,10 @@ documentation about the individual clock/clockdomain nodes. Required properties: - compatible: Must be one of: "ti,am3-prcm" - "ti,am3-scrm" "ti,am4-prcm" - "ti,am4-scrm" "ti,omap2-prcm" - "ti,omap2-scrm" "ti,omap3-prm" "ti,omap3-cm" - "ti,omap3-scrm" "ti,omap4-cm1" "ti,omap4-prm" "ti,omap4-cm2" @@ -29,6 +25,8 @@ Required properties: "ti,dra7-prm" "ti,dra7-cm-core-aon" "ti,dra7-cm-core" + "ti,dm814-prcm" + "ti,dm816-prcm" - reg: Contains PRCM module register address range (base address and length) - clocks: clocks for this module diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 6809e4e51ed29bc6eda1a772b91d576aeb0cfeb0..60d4a1e0a9b589011b956ad674bb7955dbf2f19b 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -22,3 +22,7 @@ Rockchip platforms device tree bindings - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; or - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; + +- ChipSPARK PopMetal-RK3288 board: + Required root node properties: + - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 51147cb5c036599a0741a5cc2172f0f21d07ad39..c4f19b2e7dd95c1022a43ebe2b764a6c58f26062 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -7,8 +7,6 @@ SoCs: compatible = "renesas,emev2" - RZ/A1H (R7S72100) compatible = "renesas,r7s72100" - - SH-Mobile AP4 (R8A73720/SH7372) - compatible = "renesas,sh7372" - SH-Mobile AG5 (R8A73A00/SH73A0) compatible = "renesas,sh73a0" - R-Mobile APE6 (R8A73A40) @@ -37,8 +35,6 @@ Boards: compatible = "renesas,alt", "renesas,r8a7794" - APE6-EVM compatible = "renesas,ape6evm", "renesas,r8a73a4" - - APE6-EVM - Reference Device Tree Implementation - compatible = "renesas,ape6evm-reference", "renesas,r8a73a4" - Atmark Techno Armadillo-800 EVA compatible = "renesas,armadillo800eva" - BOCK-W @@ -57,12 +53,8 @@ Boards: compatible = "renesas,kzm9d", "renesas,emev2" - Kyoto Microcomputer Co. KZM-A9-GT compatible = "renesas,kzm9g", "renesas,sh73a0" - - Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation - compatible = "renesas,kzm9g-reference", "renesas,sh73a0" - Lager (RTP0RC7790SEB00010S) compatible = "renesas,lager", "renesas,r8a7790" - - Mackerel (R0P7372LC0016RL, AP4 EVM 2nd) - compatible = "renesas,mackerel" - Marzen compatible = "renesas,marzen", "renesas,r8a7779" diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt new file mode 100644 index 0000000000000000000000000000000000000000..ea670a5d7ee3e8cd67af0987695e830187ed3b65 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt @@ -0,0 +1,32 @@ +NVIDIA Tegra Activity Monitor + +The activity monitor block collects statistics about the behaviour of other +components in the system. This information can be used to derive the rate at +which the external memory needs to be clocked in order to serve all requests +from the monitored clients. + +Required properties: +- compatible: should be "nvidia,tegra-actmon" +- reg: offset and length of the register set for the device +- interrupts: standard interrupt property +- clocks: Must contain a phandle and clock specifier pair for each entry in +clock-names. See ../../clock/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - actmon + - emc +- resets: Must contain an entry for each entry in reset-names. See +../../reset/reset.txt for details. +- reset-names: Must include the following entries: + - actmon + +Example: + actmon@6000c800 { + compatible = "nvidia,tegra124-actmon"; + reg = <0x0 0x6000c800 0x0 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_ACTMON>, + <&tegra_car TEGRA124_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car 119>; + reset-names = "actmon"; + }; diff --git a/Documentation/devicetree/bindings/bus/bcma.txt b/Documentation/devicetree/bindings/bus/brcm,bus-axi.txt similarity index 100% rename from Documentation/devicetree/bindings/bus/bcma.txt rename to Documentation/devicetree/bindings/bus/brcm,bus-axi.txt diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt index 63dd8051521c32d3674db1044ab75d01535ee074..18729f6fe1e5fbc5dea3e36c98715b4c22e4315f 100644 --- a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt +++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt @@ -1,7 +1,8 @@ * OMAP OCP2SCP - ocp interface to scp interface properties: -- compatible : Should be "ti,omap-ocp2scp" +- compatible : Should be "ti,am437x-ocp2scp" for AM437x processor + Should be "ti,omap-ocp2scp" for all others - reg : Address and length of the register set for the device - #address-cells, #size-cells : Must be present if the device has sub-nodes - ranges : the child address space are mapped 1:1 onto the parent address space diff --git a/Documentation/devicetree/bindings/bus/renesas,bsc.txt b/Documentation/devicetree/bindings/bus/renesas,bsc.txt new file mode 100644 index 0000000000000000000000000000000000000000..90e94726943772c495942e39ebe86decf1d4d7f1 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/renesas,bsc.txt @@ -0,0 +1,46 @@ +Renesas Bus State Controller (BSC) +================================== + +The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus +Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs. +It provides an external bus for connecting multiple external devices to the +SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB. + +While the BSC is a fairly simple memory-mapped bus, it may be part of a PM +domain, and may have a gateable functional clock. +Before a device connected to the BSC can be accessed, the PM domain +containing the BSC must be powered on, and the functional clock +driving the BSC must be enabled. + +The bindings for the BSC extend the bindings for "simple-pm-bus". + + +Required properties + - compatible: Must contain an SoC-specific value, and "renesas,bsc" and + "simple-pm-bus" as fallbacks. + SoC-specific values can be: + "renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4) + "renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0) + - #address-cells, #size-cells, ranges: Must describe the mapping between + parent address and child address spaces. + - reg: Must contain the base address and length to access the bus controller. + +Optional properties: + - interrupts: Must contain a reference to the BSC interrupt, if available. + - clocks: Must contain a reference to the functional clock, if available. + - power-domains: Must contain a reference to the PM domain, if available. + + +Example: + + bsc: bus@fec10000 { + compatible = "renesas,bsc-sh73a0", "renesas,bsc", + "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20000000>; + reg = <0xfec10000 0x400>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&zb_clk>; + power-domains = <&pd_a4s>; + }; diff --git a/Documentation/devicetree/bindings/bus/simple-pm-bus.txt b/Documentation/devicetree/bindings/bus/simple-pm-bus.txt new file mode 100644 index 0000000000000000000000000000000000000000..d032237512c271f29da4d321d64605d6806e5c13 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/simple-pm-bus.txt @@ -0,0 +1,44 @@ +Simple Power-Managed Bus +======================== + +A Simple Power-Managed Bus is a transparent bus that doesn't need a real +driver, as it's typically initialized by the boot loader. + +However, its bus controller is part of a PM domain, or under the control of a +functional clock. Hence, the bus controller's PM domain and/or clock must be +enabled for child devices connected to the bus (either on-SoC or externally) +to function. + +While "simple-pm-bus" follows the "simple-bus" set of properties, as specified +in ePAPR, it is not an extension of "simple-bus". + + +Required properties: + - compatible: Must contain at least "simple-pm-bus". + Must not contain "simple-bus". + It's recommended to let this be preceded by one or more + vendor-specific compatible values. + - #address-cells, #size-cells, ranges: Must describe the mapping between + parent address and child address spaces. + +Optional platform-specific properties for clock or PM domain control (at least +one of them is required): + - clocks: Must contain a reference to the functional clock(s), + - power-domains: Must contain a reference to the PM domain. +Please refer to the binding documentation for the clock and/or PM domain +providers for more details. + + +Example: + + bsc: bus@fec10000 { + compatible = "renesas,bsc-sh73a0", "renesas,bsc", + "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20000000>; + reg = <0xfec10000 0x400>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&zb_clk>; + power-domains = <&pd_a4s>; + }; diff --git a/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt b/Documentation/devicetree/bindings/clock/brcm,kona-ccu.txt similarity index 100% rename from Documentation/devicetree/bindings/clock/bcm-kona-clock.txt rename to Documentation/devicetree/bindings/clock/brcm,kona-ccu.txt diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt index f57d9dd9ea8530ae9c8d02723b1bc15d38002497..f1738b88c22596afe1a49edb114bcdc31e3f9475 100644 --- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt @@ -9,6 +9,8 @@ Required Properties: - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC. - "samsung,exynos3250-cmu-dmc" - controller compatible with Exynos3250 SoC for Dynamic Memory Controller domain. + - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible + with Exynos3250 SOC - reg: physical base address of the controller and length of memory mapped region. @@ -36,6 +38,12 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; + cmu_isp: clock-controller@10048000 { + compatible = "samsung,exynos3250-cmu-isp"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + }; + Example 2: UART controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt new file mode 100644 index 0000000000000000000000000000000000000000..63379b04e05224331cf7abf4d7948c8848287e41 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt @@ -0,0 +1,462 @@ +* Samsung Exynos5433 CMU (Clock Management Units) + +The Exynos5433 clock controller generates and supplies clock to various +controllers within the Exynos5433 SoC. + +Required Properties: + +- compatible: should be one of the following. + - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP + which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS + domains and bus clocks. + - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF + which generates clocks for LLI (Low Latency Interface) IP. + - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF + which generates clocks for DRAM Memory Controller domain. + - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC + which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. + - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS + which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. + - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS + which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. + - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D + which generates clocks for G2D/MDMA IPs. + - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP + which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. + - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD + which generates clocks for Cortex-A5/BUS/AUDIO clocks. + - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" + and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS + which generates global data buses clock and global peripheral buses clock. + - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D + which generates clocks for 3D Graphics Engine IP. + - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL + which generates clocks for GSCALER IPs. + - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO + which generates clocks for Cortex-A53 Quad-core processor. + - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS + which generates clocks for Cortex-A57 Quad-core processor, CoreSight and + L2 cache controller. + - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL + which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. + - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC + which generates clocks for MFC(Multi-Format Codec) IP. + - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC + which generates clocks for HEVC(High Efficiency Video Codec) decoder IP. + - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP + which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. + - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0 + which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} + IPs. + - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1 + which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +- clocks: list of the clock controller input clock identifiers, + from common clock bindings. Please refer the next section + to find the input clocks for a given controller. + +- clock-names: list of the clock controller input clock names, + as described in clock-bindings.txt. + + Input clocks for top clock controller: + - oscclk + - sclk_mphy_pll + - sclk_mfc_pll + - sclk_bus_pll + + Input clocks for cpif clock controller: + - oscclk + + Input clocks for mif clock controller: + - oscclk + - sclk_mphy_pll + + Input clocks for fsys clock controller: + - oscclk + - sclk_ufs_mphy + - div_aclk_fsys_200 + - sclk_pcie_100_fsys + - sclk_ufsunipro_fsys + - sclk_mmc2_fsys + - sclk_mmc1_fsys + - sclk_mmc0_fsys + - sclk_usbhost30_fsys + - sclk_usbdrd30_fsys + + Input clocks for g2d clock controller: + - oscclk + - aclk_g2d_266 + - aclk_g2d_400 + + Input clocks for disp clock controller: + - oscclk + - sclk_dsim1_disp + - sclk_dsim0_disp + - sclk_dsd_disp + - sclk_decon_tv_eclk_disp + - sclk_decon_vclk_disp + - sclk_decon_eclk_disp + - sclk_decon_tv_vclk_disp + - aclk_disp_333 + + Input clocks for bus0 clock controller: + - aclk_bus0_400 + + Input clocks for bus1 clock controller: + - aclk_bus1_400 + + Input clocks for bus2 clock controller: + - oscclk + - aclk_bus2_400 + + Input clocks for g3d clock controller: + - oscclk + - aclk_g3d_400 + + Input clocks for gscl clock controller: + - oscclk + - aclk_gscl_111 + - aclk_gscl_333 + + Input clocks for apollo clock controller: + - oscclk + - sclk_bus_pll_apollo + + Input clocks for atlas clock controller: + - oscclk + - sclk_bus_pll_atlas + + Input clocks for mscl clock controller: + - oscclk + - sclk_jpeg_mscl + - aclk_mscl_400 + + Input clocks for mfc clock controller: + - oscclk + - aclk_mfc_400 + + Input clocks for hevc clock controller: + - oscclk + - aclk_hevc_400 + + Input clocks for isp clock controller: + - oscclk + - aclk_isp_dis_400 + - aclk_isp_400 + + Input clocks for cam0 clock controller: + - oscclk + - aclk_cam0_333 + - aclk_cam0_400 + - aclk_cam0_552 + + Input clocks for cam1 clock controller: + - oscclk + - sclk_isp_uart_cam1 + - sclk_isp_spi1_cam1 + - sclk_isp_spi0_cam1 + - aclk_cam1_333 + - aclk_cam1_400 + - aclk_cam1_552 + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5433.h header and can be used in device +tree sources. + +Example 1: Examples of 'oscclk' source clock node are listed below. + + xxti: xxti { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + }; + +Example 2: Examples of clock controller nodes are listed below. + + cmu_top: clock-controller@10030000 { + compatible = "samsung,exynos5433-cmu-top"; + reg = <0x10030000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll", + "sclk_mfc_pll", + "sclk_bus_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>, + <&cmu_mif CLK_SCLK_MFC_PLL>, + <&cmu_mif CLK_SCLK_BUS_PLL>; + }; + + cmu_cpif: clock-controller@10fc0000 { + compatible = "samsung,exynos5433-cmu-cpif"; + reg = <0x10fc0000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk"; + clocks = <&xxti>; + }; + + cmu_mif: clock-controller@105b0000 { + compatible = "samsung,exynos5433-cmu-mif"; + reg = <0x105b0000 0x100c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>; + }; + + cmu_peric: clock-controller@14c80000 { + compatible = "samsung,exynos5433-cmu-peric"; + reg = <0x14c80000 0x0b08>; + #clock-cells = <1>; + }; + + cmu_peris: clock-controller@10040000 { + compatible = "samsung,exynos5433-cmu-peris"; + reg = <0x10040000 0x0b20>; + #clock-cells = <1>; + }; + + cmu_fsys: clock-controller@156e0000 { + compatible = "samsung,exynos5433-cmu-fsys"; + reg = <0x156e0000 0x0b04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_ufs_mphy", + "div_aclk_fsys_200", + "sclk_pcie_100_fsys", + "sclk_ufsunipro_fsys", + "sclk_mmc2_fsys", + "sclk_mmc1_fsys", + "sclk_mmc0_fsys", + "sclk_usbhost30_fsys", + "sclk_usbdrd30_fsys"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_UFS_MPHY>, + <&cmu_top CLK_DIV_ACLK_FSYS_200>, + <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, + <&cmu_top CLK_SCLK_MMC2_FSYS>, + <&cmu_top CLK_SCLK_MMC1_FSYS>, + <&cmu_top CLK_SCLK_MMC0_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>; + }; + + cmu_g2d: clock-controller@12460000 { + compatible = "samsung,exynos5433-cmu-g2d"; + reg = <0x12460000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_g2d_266", + "aclk_g2d_400"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_G2D_266>, + <&cmu_top CLK_ACLK_G2D_400>; + }; + + cmu_disp: clock-controller@13b90000 { + compatible = "samsung,exynos5433-cmu-disp"; + reg = <0x13b90000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_dsim1_disp", + "sclk_dsim0_disp", + "sclk_dsd_disp", + "sclk_decon_tv_eclk_disp", + "sclk_decon_vclk_disp", + "sclk_decon_eclk_disp", + "sclk_decon_tv_vclk_disp", + "aclk_disp_333"; + clocks = <&xxti>, + <&cmu_mif CLK_SCLK_DSIM1_DISP>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_mif CLK_SCLK_DSD_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, + <&cmu_mif CLK_ACLK_DISP_333>; + }; + + cmu_aud: clock-controller@114c0000 { + compatible = "samsung,exynos5433-cmu-aud"; + reg = <0x114c0000 0x0b04>; + #clock-cells = <1>; + }; + + cmu_bus0: clock-controller@13600000 { + compatible = "samsung,exynos5433-cmu-bus0"; + reg = <0x13600000 0x0b04>; + #clock-cells = <1>; + + clock-names = "aclk_bus0_400"; + clocks = <&cmu_top CLK_ACLK_BUS0_400>; + }; + + cmu_bus1: clock-controller@14800000 { + compatible = "samsung,exynos5433-cmu-bus1"; + reg = <0x14800000 0x0b04>; + #clock-cells = <1>; + + clock-names = "aclk_bus1_400"; + clocks = <&cmu_top CLK_ACLK_BUS1_400>; + }; + + cmu_bus2: clock-controller@13400000 { + compatible = "samsung,exynos5433-cmu-bus2"; + reg = <0x13400000 0x0b04>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_bus2_400"; + clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; + }; + + cmu_g3d: clock-controller@14aa0000 { + compatible = "samsung,exynos5433-cmu-g3d"; + reg = <0x14aa0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_g3d_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; + }; + + cmu_gscl: clock-controller@13cf0000 { + compatible = "samsung,exynos5433-cmu-gscl"; + reg = <0x13cf0000 0x0b10>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_gscl_111", + "aclk_gscl_333"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_GSCL_111>, + <&cmu_top CLK_ACLK_GSCL_333>; + }; + + cmu_apollo: clock-controller@11900000 { + compatible = "samsung,exynos5433-cmu-apollo"; + reg = <0x11900000 0x1088>; + #clock-cells = <1>; + + clock-names = "oscclk", "sclk_bus_pll_apollo"; + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; + }; + + cmu_atlas: clock-controller@11800000 { + compatible = "samsung,exynos5433-cmu-atlas"; + reg = <0x11800000 0x1088>; + #clock-cells = <1>; + + clock-names = "oscclk", "sclk_bus_pll_atlas"; + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; + }; + + cmu_mscl: clock-controller@105d0000 { + compatible = "samsung,exynos5433-cmu-mscl"; + reg = <0x105d0000 0x0b10>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_jpeg_mscl", + "aclk_mscl_400"; + clocks = <&xxti>, + <&cmu_top CLK_SCLK_JPEG_MSCL>, + <&cmu_top CLK_ACLK_MSCL_400>; + }; + + cmu_mfc: clock-controller@15280000 { + compatible = "samsung,exynos5433-cmu-mfc"; + reg = <0x15280000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_mfc_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; + }; + + cmu_hevc: clock-controller@14f80000 { + compatible = "samsung,exynos5433-cmu-hevc"; + reg = <0x14f80000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_hevc_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; + }; + + cmu_isp: clock-controller@146d0000 { + compatible = "samsung,exynos5433-cmu-isp"; + reg = <0x146d0000 0x0b0c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_isp_dis_400", + "aclk_isp_400"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_ISP_DIS_400>, + <&cmu_top CLK_ACLK_ISP_400>; + }; + + cmu_cam0: clock-controller@120d0000 { + compatible = "samsung,exynos5433-cmu-cam0"; + reg = <0x120d0000 0x0b0c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_cam0_333", + "aclk_cam0_400", + "aclk_cam0_552"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_CAM0_333>, + <&cmu_top CLK_ACLK_CAM0_400>, + <&cmu_top CLK_ACLK_CAM0_552>; + }; + + cmu_cam1: clock-controller@145d0000 { + compatible = "samsung,exynos5433-cmu-cam1"; + reg = <0x145d0000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_isp_uart_cam1", + "sclk_isp_spi1_cam1", + "sclk_isp_spi0_cam1", + "aclk_cam1_333", + "aclk_cam1_400", + "aclk_cam1_552"; + clocks = <&xxti>, + <&cmu_top CLK_SCLK_ISP_UART_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, + <&cmu_top CLK_ACLK_CAM1_333>, + <&cmu_top CLK_ACLK_CAM1_400>, + <&cmu_top CLK_ACLK_CAM1_552>; + }; + +Example 3: UART controller node that consumes the clock generated by the clock + controller. + + serial_0: serial@14C10000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14C10000 0x100>; + interrupts = <0 421 0>; + clocks = <&cmu_peric CLK_PCLK_UART0>, + <&cmu_peric CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt new file mode 100644 index 0000000000000000000000000000000000000000..33239626568920bb92f10efd6754fd4c3d7b7675 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt @@ -0,0 +1,26 @@ +Fujitsu CRG11 clock driver bindings +----------------------------------- + +Required properties : +- compatible : Shall contain "fujitsu,mb86s70-crg11" +- #clock-cells : Shall be 3 {cntrlr domain port} + +The consumer specifies the desired clock pointing to its phandle. + +Example: + + clock: crg11 { + compatible = "fujitsu,mb86s70-crg11"; + #clock-cells = <3>; + }; + + mhu: mhu0@2b1f0000 { + #mbox-cells = <1>; + compatible = "arm,mhu"; + reg = <0 0x2B1F0000 0x1000>; + interrupts = <0 36 4>, /* LP Non-Sec */ + <0 35 4>, /* HP Non-Sec */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */ + clock-names = "clk"; + }; diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt index dc5ea5b22da90dbf43f0d5e15b28141d3c7e0e4d..670c2af3e931a779adbe3bbdd06674181e82cf8d 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt @@ -23,6 +23,14 @@ The following is a list of provided IDs and clock names on Armada 380/385: 2 = l2clk (L2 Cache clock) 3 = ddrclk (DDR clock) +The following is a list of provided IDs and clock names on Armada 39x: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU clock) + 2 = nbclk (Coherent Fabric clock) + 3 = hclk (SDRAM Controller Internal Clock) + 4 = dclk (SDRAM Interface Clock) + 5 = refclk (Reference Clock) + The following is a list of provided IDs and clock names on Kirkwood and Dove: 0 = tclk (Internal Bus clock) 1 = cpuclk (CPU0 clock) @@ -39,6 +47,7 @@ Required properties: "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks + "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks "marvell,dove-core-clock" - for Dove SoC core clocks "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt index 76477be742b21c016e06d59f2a67c28b9ffdabf0..31c7c0c1ce8f6b47a625f8b6f41eafc6a35d402a 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt @@ -1,6 +1,6 @@ * Gated Clock bindings for Marvell EBU SoCs -Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some +Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some peripheral clocks to be gated to save some power. The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to the @@ -77,6 +77,18 @@ ID Clock Peripheral 28 xor1 XOR 1 30 sata1 SATA 1 +The following is a list of provided IDs for Armada 39x: +ID Clock Peripheral +----------------------------------- +5 pex1 PCIe 1 +6 pex2 PCIe 2 +7 pex3 PCIe 3 +8 pex0 PCIe 0 +9 usb3h0 USB3 Host 0 +17 sdio SDIO +22 xor0 XOR 0 +28 xor1 XOR 1 + The following is a list of provided IDs for Armada XP: ID Clock Peripheral ----------------------------------- @@ -152,6 +164,7 @@ Required properties: "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating + "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating "marvell,dove-gating-clock" - for Dove SoC clock gating "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating diff --git a/Documentation/devicetree/bindings/clock/pwm-clock.txt b/Documentation/devicetree/bindings/clock/pwm-clock.txt new file mode 100644 index 0000000000000000000000000000000000000000..83db876b3b9071a30faa981ec3ffb8c50b5867d0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/pwm-clock.txt @@ -0,0 +1,26 @@ +Binding for an external clock signal driven by a PWM pin. + +This binding uses the common clock binding[1] and the common PWM binding[2]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/pwm/pwm.txt + +Required properties: +- compatible : shall be "pwm-clock". +- #clock-cells : from common clock binding; shall be set to 0. +- pwms : from common PWM binding; this determines the clock frequency + via the period given in the PWM specifier. + +Optional properties: +- clock-output-names : From common clock binding. +- clock-frequency : Exact output frequency, in case the PWM period + is not exact but was rounded to nanoseconds. + +Example: + clock { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "mipi_mclk"; + pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */ + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index aba3d254e037902b540e0801c2294656a08d22b6..54c23f34f194608c34c01f1ecb6ae9be58e11704 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -8,6 +8,7 @@ Required properties : "qcom,gcc-apq8084" "qcom,gcc-ipq8064" "qcom,gcc-msm8660" + "qcom,gcc-msm8916" "qcom,gcc-msm8960" "qcom,gcc-msm8974" "qcom,gcc-msm8974pro" diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt new file mode 100644 index 0000000000000000000000000000000000000000..2f3747fdcf1c53057be743af116a35d0f91833d6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt @@ -0,0 +1,25 @@ +* Renesas R8A7778 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the R8A7778. It includes two PLLs and +several fixed ratio dividers + +Required Properties: + + - compatible: Must be "renesas,r8a7778-cpg-clocks" + - reg: Base address and length of the memory resource used by the CPG + - #clock-cells: Must be 1 + - clock-output-names: The names of the clocks. Supported clocks are + "plla", "pllb", "b", "out", "p", "s", and "s1". + + +Example +------- + + cpg_clocks: cpg_clocks@ffc80000 { + compatible = "renesas,r8a7778-cpg-clocks"; + reg = <0xffc80000 0x80>; + #clock-cells = <1>; + clocks = <&extal_clk>; + clock-output-names = "plla", "pllb", "b", + "out", "p", "s", "s1"; + }; diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt index c40711e8e8f7df7c27f74d1dcf418909a96bedf2..28b28309f53575e91752cba6453e5594ea985de3 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.txt @@ -17,7 +17,8 @@ Required properties: - #clock-cells: from common clock binding; shall be set to 1. - clocks: from common clock binding; list of parent clock handles, shall be xtal reference clock or xtal and clkin for - si5351c only. + si5351c only. Corresponding clock input names are "xtal" and + "clkin" respectively. - #address-cells: shall be set to 1. - #size-cells: shall be set to 0. @@ -71,6 +72,7 @@ i2c-master-node { /* connect xtal input to 25MHz reference */ clocks = <&ref25>; + clock-names = "xtal"; /* connect xtal input as source of pll0 and pll1 */ silabs,pll-source = <0 0>, <1 0>; diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 60b44285250d3b3e9e580f9d71e51239df3b1c76..4fa11af3d378ef281e43717490c012263b901122 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -20,6 +20,7 @@ Required properties: "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates "allwinner,sun4i-a10-ahb-clk" - for the AHB clock + "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13 "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 @@ -66,6 +67,8 @@ Required properties: "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 + "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 + "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 Required properties for all clocks: - reg : shall be the control register address for the clock. diff --git a/Documentation/devicetree/bindings/common-properties.txt b/Documentation/devicetree/bindings/common-properties.txt new file mode 100644 index 0000000000000000000000000000000000000000..3193979b1d05002fcf2bc4700efcd4bbfeb65d88 --- /dev/null +++ b/Documentation/devicetree/bindings/common-properties.txt @@ -0,0 +1,60 @@ +Common properties + +The ePAPR specification does not define any properties related to hardware +byteswapping, but endianness issues show up frequently in porting Linux to +different machine types. This document attempts to provide a consistent +way of handling byteswapping across drivers. + +Optional properties: + - big-endian: Boolean; force big endian register accesses + unconditionally (e.g. ioread32be/iowrite32be). Use this if you + know the peripheral always needs to be accessed in BE mode. + - little-endian: Boolean; force little endian register accesses + unconditionally (e.g. readl/writel). Use this if you know the + peripheral always needs to be accessed in LE mode. + - native-endian: Boolean; always use register accesses matched to the + endianness of the kernel binary (e.g. LE vmlinux -> readl/writel, + BE vmlinux -> ioread32be/iowrite32be). In this case no byteswaps + will ever be performed. Use this if the hardware "self-adjusts" + register endianness based on the CPU's configured endianness. + +If a binding supports these properties, then the binding should also +specify the default behavior if none of these properties are present. +In such cases, little-endian is the preferred default, but it is not +a requirement. The of_device_is_big_endian() and of_fdt_is_big_endian() +helper functions do assume that little-endian is the default, because +most existing (PCI-based) drivers implicitly default to LE by using +readl/writel for MMIO accesses. + +Examples: +Scenario 1 : CPU in LE mode & device in LE mode. +dev: dev@40031000 { + compatible = "name"; + reg = <0x40031000 0x1000>; + ... + native-endian; +}; + +Scenario 2 : CPU in LE mode & device in BE mode. +dev: dev@40031000 { + compatible = "name"; + reg = <0x40031000 0x1000>; + ... + big-endian; +}; + +Scenario 3 : CPU in BE mode & device in BE mode. +dev: dev@40031000 { + compatible = "name"; + reg = <0x40031000 0x1000>; + ... + native-endian; +}; + +Scenario 4 : CPU in BE mode & device in LE mode. +dev: dev@40031000 { + compatible = "name"; + reg = <0x40031000 0x1000>; + ... + little-endian; +}; diff --git a/Documentation/devicetree/bindings/cris/axis.txt b/Documentation/devicetree/bindings/cris/axis.txt new file mode 100644 index 0000000000000000000000000000000000000000..d209ca2a47c06606b20caf438426c9d7a7321bc7 --- /dev/null +++ b/Documentation/devicetree/bindings/cris/axis.txt @@ -0,0 +1,9 @@ +Axis Communications AB +ARTPEC series SoC Device Tree Bindings + + +CRISv32 based SoCs are ETRAX FS and ARTPEC-3: + + - compatible = "axis,crisv32"; + + diff --git a/Documentation/devicetree/bindings/cris/boards.txt b/Documentation/devicetree/bindings/cris/boards.txt new file mode 100644 index 0000000000000000000000000000000000000000..533dd273ccf7285e8669834317fc9ad9cdeaea96 --- /dev/null +++ b/Documentation/devicetree/bindings/cris/boards.txt @@ -0,0 +1,8 @@ +Boards based on the CRIS SoCs: + +Required root node properties: + - compatible = should be one or more of the following: + - "axis,dev88" - for Axis devboard 88 with ETRAX FS + +Optional: + diff --git a/Documentation/devicetree/bindings/cris/interrupts.txt b/Documentation/devicetree/bindings/cris/interrupts.txt new file mode 100644 index 0000000000000000000000000000000000000000..e8b123b0a5e6c7928723b9729e4d628d3dc74f9d --- /dev/null +++ b/Documentation/devicetree/bindings/cris/interrupts.txt @@ -0,0 +1,23 @@ +* CRISv32 Interrupt Controller + +Interrupt controller for the CRISv32 SoCs. + +Main node required properties: + +- compatible : should be: + "axis,crisv32-intc" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 1. +- reg: physical base address and size of the intc registers map. + +Example: + + intc: interrupt-controller { + compatible = "axis,crisv32-intc"; + reg = <0xb001c000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt new file mode 100644 index 0000000000000000000000000000000000000000..d3058768b23de17e4c9916c2552b1266b9263d56 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt @@ -0,0 +1,47 @@ +Applied Micro X-Gene SoC DMA nodes + +DMA nodes are defined to describe on-chip DMA interfaces in +APM X-Gene SoC. + +Required properties for DMA interfaces: +- compatible: Should be "apm,xgene-dma". +- device_type: set to "dma". +- reg: Address and length of the register set for the device. + It contains the information of registers in the following order: + 1st - DMA control and status register address space. + 2nd - Descriptor ring control and status register address space. + 3rd - Descriptor ring command register address space. + 4th - Soc efuse register address space. +- interrupts: DMA has 5 interrupts sources. 1st interrupt is + DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts + are completion interrupts for each DMA channels. +- clocks: Reference to the clock entry. + +Optional properties: +- dma-coherent : Present if dma operations are coherent + +Example: + dmaclk: dmaclk@1f27c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f27c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "dmaclk"; + }; + + dma: dma@1f270000 { + compatible = "apm,xgene-storm-dma"; + device_type = "dma"; + reg = <0x0 0x1f270000 0x0 0x10000>, + <0x0 0x1f200000 0x0 0x10000>, + <0x0 0x1b008000 0x0 0x2000>, + <0x0 0x1054a000 0x0 0x100>; + interrupts = <0x0 0x82 0x4>, + <0x0 0xb8 0x4>, + <0x0 0xb9 0x4>, + <0x0 0xba 0x4>, + <0x0 0xbb 0x4>; + dma-coherent; + clocks = <&dmaclk 0>; + }; diff --git a/Documentation/devicetree/bindings/dma/bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt similarity index 100% rename from Documentation/devicetree/bindings/dma/bcm2835-dma.txt rename to Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt diff --git a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt index a4873e5e3e36de172c49f59108360e32aca9fefd..e30e184f50c727aa84d2284914581ce9927dba1c 100644 --- a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt @@ -38,7 +38,7 @@ dma_apbx: dma-apbx@80024000 { 80 81 68 69 70 71 72 73 74 75 76 77>; - interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", + interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", "saif0", "saif1", "i2c0", "i2c1", "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt new file mode 100644 index 0000000000000000000000000000000000000000..f25feee62b158a1833c04bf230d57937ca8cc828 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt @@ -0,0 +1,56 @@ +* Ingenic JZ4780 DMA Controller + +Required properties: + +- compatible: Should be "ingenic,jz4780-dma" +- reg: Should contain the DMA controller registers location and length. +- interrupts: Should contain the interrupt specifier of the DMA controller. +- interrupt-parent: Should be the phandle of the interrupt controller that +- clocks: Should contain a clock specifier for the JZ4780 PDMA clock. +- #dma-cells: Must be <2>. Number of integer cells in the dmas property of + DMA clients (see below). + +Optional properties: + +- ingenic,reserved-channels: Bitmask of channels to reserve for devices that + need a specific channel. These channels will only be assigned when explicitly + requested by a client. The primary use for this is channels 0 and 1, which + can be configured to have special behaviour for NAND/BCH when using + programmable firmware. + +Example: + +dma: dma@13420000 { + compatible = "ingenic,jz4780-dma"; + reg = <0x13420000 0x10000>; + + interrupt-parent = <&intc>; + interrupts = <10>; + + clocks = <&cgu JZ4780_CLK_PDMA>; + + #dma-cells = <2>; + + ingenic,reserved-channels = <0x3>; +}; + +DMA clients must use the format described in dma.txt, giving a phandle to the +DMA controller plus the following 2 integer cells: + +1. Request type: The DMA request type for transfers to/from the device on + the allocated channel, as defined in the SoC documentation. + +2. Channel: If set to 0xffffffff, any available channel will be allocated for + the client. Otherwise, the exact channel specified will be used. The channel + should be reserved on the DMA controller using the ingenic,reserved-channels + property. + +Example: + +uart0: serial@10030000 { + ... + dmas = <&dma 0x14 0xffffffff + &dma 0x15 0xffffffff>; + dma-names = "tx", "rx"; + ... +}; diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt index f8c3311b7153e76619e8e5e47434b07898705ec6..1c9d48ea49148c20d8f3eae564e45a06d6c9c2f2 100644 --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt @@ -4,6 +4,7 @@ Required properties: - compatible: must be one of the following: * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084 * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960 + * "qcom,bam-v1.7.0" for MSM8916 - reg: Address range for DMA registers - interrupts: Should contain the one interrupt shared by all channels - #dma-cells: must be <1>, the cell in the dmas property of the client device diff --git a/Documentation/devicetree/bindings/dma/rcar-audmapp.txt b/Documentation/devicetree/bindings/dma/rcar-audmapp.txt deleted file mode 100644 index 61bca509d7b99f734d1c7f054587aaa29dff8261..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/dma/rcar-audmapp.txt +++ /dev/null @@ -1,29 +0,0 @@ -* R-Car Audio DMAC peri peri Device Tree bindings - -Required properties: -- compatible: should be "renesas,rcar-audmapp" -- #dma-cells: should be <1>, see "dmas" property below - -Example: - audmapp: audio-dma-pp@0xec740000 { - compatible = "renesas,rcar-audmapp"; - #dma-cells = <1>; - - reg = <0 0xec740000 0 0x200>; - }; - - -* DMA client - -Required properties: -- dmas: a list of <[DMA multiplexer phandle] [SRS << 8 | DRS]> pairs. - where SRS/DRS are specified in the SoC manual. - It will be written into PDMACHCR as high 16-bit parts. -- dma-names: a list of DMA channel names, one per "dmas" entry - -Example: - - dmas = <&audmapp 0x2d00 - &audmapp 0x3700>; - dma-names = "src0_ssiu0", - "dvc0_ssiu0"; diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt new file mode 100644 index 0000000000000000000000000000000000000000..040f365954cc4d105c64a3a204b9fc342fc22ce2 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt @@ -0,0 +1,37 @@ +* Renesas USB DMA Controller Device Tree bindings + +Required Properties: +- compatible: must contain "renesas,usb-dmac" +- reg: base address and length of the registers block for the DMAC +- interrupts: interrupt specifiers for the DMAC, one for each entry in + interrupt-names. +- interrupt-names: one entry per channel, named "ch%u", where %u is the + channel number ranging from zero to the number of channels minus one. +- clocks: a list of phandle + clock-specifier pairs. +- #dma-cells: must be <1>, the cell specifies the channel number of the DMAC + port connected to the DMA client. +- dma-channels: number of DMA channels + +Example: R8A7790 (R-Car H2) USB-DMACs + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH + 0 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH + 0 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; + #dma-cells = <1>; + dma-channels = <2>; + }; diff --git a/Documentation/devicetree/bindings/drm/imx/ldb.txt b/Documentation/devicetree/bindings/drm/imx/ldb.txt index 443bcb6134d53ca6afc8587b611a82ec30e89d22..9a21366436f6de14f862bed9ee71bb054e7b03d4 100644 --- a/Documentation/devicetree/bindings/drm/imx/ldb.txt +++ b/Documentation/devicetree/bindings/drm/imx/ldb.txt @@ -44,23 +44,30 @@ Optional properties: LVDS Channel ============ -Each LVDS Channel has to contain a display-timings node that describes the -video timings for the connected LVDS display. For detailed information, also -have a look at Documentation/devicetree/bindings/video/display-timing.txt. +Each LVDS Channel has to contain either an of graph link to a panel device node +or a display-timings node that describes the video timings for the connected +LVDS display as well as the fsl,data-mapping and fsl,data-width properties. Required properties: - reg : should be <0> or <1> + - port: Input and output port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/graph.txt. + On i.MX5, the internal two-input-multiplexer is used. Due to hardware + limitations, only one input port (port@[0,1]) can be used for each channel + (lvds-channel@[0,1], respectively). + On i.MX6, there should be four input ports (port@[0-3]) that correspond + to the four LVDS multiplexer inputs. + A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected + to a panel input port. Optionally, the output port can be left out if + display-timings are used instead. + +Optional properties (required if display-timings are used): + - display-timings : A node that describes the display timings as defined in + Documentation/devicetree/bindings/video/display-timing.txt. - fsl,data-mapping : should be "spwg" or "jeida" This describes how the color bits are laid out in the serialized LVDS signal. - fsl,data-width : should be <18> or <24> - - port: A port node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - On i.MX5, the internal two-input-multiplexer is used. - Due to hardware limitations, only one port (port@[0,1]) - can be used for each channel (lvds-channel@[0,1], respectively) - On i.MX6, there should be four ports (port@[0-3]) that correspond - to the four LVDS multiplexer inputs. example: @@ -73,23 +80,21 @@ ldb: ldb@53fa8008 { #size-cells = <0>; compatible = "fsl,imx53-ldb"; gpr = <&gpr>; - clocks = <&clks 122>, <&clks 120>, - <&clks 115>, <&clks 116>, - <&clks 123>, <&clks 85>; + clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, + <&clks IMX5_CLK_LDB_DI1_SEL>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>, + <&clks IMX5_CLK_LDB_DI0_GATE>, + <&clks IMX5_CLK_LDB_DI1_GATE>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di0", "di1"; + /* Using an of-graph endpoint link to connect the panel */ lvds-channel@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - - display-timings { - /* ... */ - }; port@0 { reg = <0>; @@ -98,8 +103,17 @@ ldb: ldb@53fa8008 { remote-endpoint = <&ipu_di0_lvds0>; }; }; + + port@2 { + reg = <2>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; }; + /* Using display-timings and fsl,data-mapping/width instead */ lvds-channel@1 { #address-cells = <1>; #size-cells = <0>; @@ -120,3 +134,13 @@ ldb: ldb@53fa8008 { }; }; }; + +panel: lvds-panel { + /* ... */ + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt b/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt new file mode 100644 index 0000000000000000000000000000000000000000..af0b903de293a061167aea7b07c203d3fafa5527 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt @@ -0,0 +1,18 @@ +USB GPIO Extcon device + +This is a virtual device used to generate USB cable states from the USB ID pin +connected to a GPIO pin. + +Required properties: +- compatible: Should be "linux,extcon-usb-gpio" +- id-gpio: gpio for USB ID pin. See gpio binding. + +Example: Examples of extcon-usb-gpio node in dra7-evm.dts as listed below: + extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>; + } + + &omap_dwc3_1 { + extcon = <&extcon_usb1>; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-bcm-kona.txt b/Documentation/devicetree/bindings/gpio/brcm,kona-gpio.txt similarity index 100% rename from Documentation/devicetree/bindings/gpio/gpio-bcm-kona.txt rename to Documentation/devicetree/bindings/gpio/brcm,kona-gpio.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio-altera.txt b/Documentation/devicetree/bindings/gpio/gpio-altera.txt new file mode 100644 index 0000000000000000000000000000000000000000..12f50149e1ed376398d127663b386bf082f9ffd3 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-altera.txt @@ -0,0 +1,43 @@ +Altera GPIO controller bindings + +Required properties: +- compatible: + - "altr,pio-1.0" +- reg: Physical base address and length of the controller's registers. +- #gpio-cells : Should be 2 + - The first cell is the gpio offset number. + - The second cell is reserved and is currently unused. +- gpio-controller : Marks the device node as a GPIO controller. +- interrupt-controller: Mark the device node as an interrupt controller +- #interrupt-cells : Should be 1. The interrupt type is fixed in the hardware. + - The first cell is the GPIO offset number within the GPIO controller. +- interrupts: Specify the interrupt. +- altr,interrupt-trigger: Specifies the interrupt trigger type the GPIO + hardware is synthesized. This field is required if the Altera GPIO controller + used has IRQ enabled as the interrupt type is not software controlled, + but hardware synthesized. Required if GPIO is used as an interrupt + controller. The value is defined in + Only the following flags are supported: + IRQ_TYPE_EDGE_RISING + IRQ_TYPE_EDGE_FALLING + IRQ_TYPE_EDGE_BOTH + IRQ_TYPE_LEVEL_HIGH + +Optional properties: +- altr,ngpio: Width of the GPIO bank. This defines how many pins the + GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not + specified. + +Example: + +gpio_altr: gpio@0xff200000 { + compatible = "altr,pio-1.0"; + reg = <0xff200000 0x10>; + interrupts = <0 45 4>; + altr,ngpio = <32>; + altr,interrupt-trigger = ; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <1>; + interrupt-controller; +}; diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index f7a158d858620f73133aded14765f042742a3fb4..5788d5cf12524b95c556ec0451204c3b735f6d43 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -116,6 +116,29 @@ Every GPIO controller node must contain both an empty "gpio-controller" property, and a #gpio-cells integer property, which indicates the number of cells in a gpio-specifier. +The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism +providing automatic GPIO request and configuration as part of the +gpio-controller's driver probe function. + +Each GPIO hog definition is represented as a child node of the GPIO controller. +Required properties: +- gpio-hog: A property specifying that this child node represent a GPIO hog. +- gpios: Store the GPIO information (id, flags, ...). Shall contain the + number of cells specified in its parent node (GPIO controller + node). +Only one of the following properties scanned in the order shown below. +This means that when multiple properties are present they will be searched +in the order presented below and the first match is taken as the intended +configuration. +- input: A property specifying to set the GPIO direction as input. +- output-low A property specifying to set the GPIO direction as output with + the value low. +- output-high A property specifying to set the GPIO direction as output with + the value high. + +Optional properties: +- line-name: The GPIO label name. If not present the node name is used. + Example of two SOC GPIO banks defined as gpio-controller nodes: qe_pio_a: gpio-controller@1400 { @@ -123,6 +146,13 @@ Example of two SOC GPIO banks defined as gpio-controller nodes: reg = <0x1400 0x18>; gpio-controller; #gpio-cells = <2>; + + line_b { + gpio-hog; + gpios = <6 0>; + output-low; + line-name = "foo-bar-gpio"; + }; }; qe_pio_e: gpio-controller@1460 { diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt index 67a2e4e414a5eb93409807b9e837cda236abd977..98d1983969566a0278b4544a5a24cef3c14fe85c 100644 --- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt @@ -12,7 +12,7 @@ Required properties: gpio_mux. - interrupt-names : Should be the names of irq resources. Each interrupt uses its own interrupt name, so there should be as many interrupt names - as referenced interrups. + as referenced interrupts. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells: Specifies the number of cells needed to encode an interrupt source. diff --git a/Documentation/devicetree/bindings/i2c/i2c-bcm-kona.txt b/Documentation/devicetree/bindings/i2c/brcm,kona-i2c.txt similarity index 100% rename from Documentation/devicetree/bindings/i2c/i2c-bcm-kona.txt rename to Documentation/devicetree/bindings/i2c/brcm,kona-i2c.txt diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 003bd77b4595f515bd35a5ad6f9419f50abf8579..ad0c4ac916dd75ed0b7eb07e28b3c62e60f3d725 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -77,6 +77,7 @@ nxp,pca9556 Octal SMBus and I2C registered interface nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset nxp,pcf8563 Real-time clock/calendar nxp,pcf85063 Tiny Real-Time Clock +oki,ml86v7667 OKI ML86V7667 video decoder ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus pericom,pt7c4338 Real-time Clock Module plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch diff --git a/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt b/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt index 4b641c7bf1c252a3465aa7e028e18042cb7ad61b..09089a6d69ed8d1c9b29115e6abce75a6d1a2fcd 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt @@ -32,8 +32,8 @@ Example: touchscreen-fuzz-x = <4>; touchscreen-fuzz-y = <7>; touchscreen-fuzz-pressure = <2>; - touchscreen-max-x = <4096>; - touchscreen-max-y = <4096>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; touchscreen-max-pressure = <2048>; ti,x-plate-ohms = <280>; diff --git a/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt b/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt index bf52ed4a5067de5c9d825f77865321112ec5a651..4ef45636ebdedd538bef484a94705b720aceda66 100644 --- a/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt +++ b/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt @@ -4,7 +4,7 @@ Required properties: - compatible : should be one of: "samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg", - "samsung,exynos3250-jpeg"; + "samsung,exynos3250-jpeg", "samsung,exynos5420-jpeg"; - reg : address and length of the JPEG codec IP register set; - interrupts : specifies the JPEG codec IP interrupt; - clock-names : should contain: diff --git a/Documentation/devicetree/bindings/media/i2c/mt9v032.txt b/Documentation/devicetree/bindings/media/i2c/mt9v032.txt new file mode 100644 index 0000000000000000000000000000000000000000..202565313e825fe897e03a05849fa54765efe2fe --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/mt9v032.txt @@ -0,0 +1,39 @@ +* Aptina 1/3-Inch WVGA CMOS Digital Image Sensor + +The Aptina MT9V032 is a 1/3-inch CMOS active pixel digital image sensor with +an active array size of 752H x 480V. It is programmable through a simple +two-wire serial interface. + +Required Properties: + +- compatible: value should be either one among the following + (a) "aptina,mt9v022" for MT9V022 color sensor + (b) "aptina,mt9v022m" for MT9V022 monochrome sensor + (c) "aptina,mt9v024" for MT9V024 color sensor + (d) "aptina,mt9v024m" for MT9V024 monochrome sensor + (e) "aptina,mt9v032" for MT9V032 color sensor + (f) "aptina,mt9v032m" for MT9V032 monochrome sensor + (g) "aptina,mt9v034" for MT9V034 color sensor + (h) "aptina,mt9v034m" for MT9V034 monochrome sensor + +Optional Properties: + +- link-frequencies: List of allowed link frequencies in Hz. Each frequency is + expressed as a 64-bit big-endian integer. + +For further reading on port node refer to +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + + mt9v032@5c { + compatible = "aptina,mt9v032"; + reg = <0x5c>; + + port { + mt9v032_out: endpoint { + link-frequencies = /bits/ 64 + <13000000 26600000 27000000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/ov2640.txt b/Documentation/devicetree/bindings/media/i2c/ov2640.txt new file mode 100644 index 0000000000000000000000000000000000000000..c429b5bdcaa05ef7486965814b5e55820f9d2dc3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ov2640.txt @@ -0,0 +1,46 @@ +* Omnivision OV2640 CMOS sensor + +The Omnivision OV2640 sensor support multiple resolutions output, such as +CIF, SVGA, UXGA. It also can support YUV422/420, RGB565/555 or raw RGB +output format. + +Required Properties: +- compatible: should be "ovti,ov2640" +- clocks: reference to the xvclk input clock. +- clock-names: should be "xvclk". + +Optional Properties: +- resetb-gpios: reference to the GPIO connected to the resetb pin, if any. +- pwdn-gpios: reference to the GPIO connected to the pwdn pin, if any. + +The device node must contain one 'port' child node for its digital output +video port, in accordance with the video interface bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + + i2c1: i2c@f0018000 { + ov2640: camera@0x30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck1 &pinctrl_ov2640_pwdn &pinctrl_ov2640_resetb>; + + resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; + + clocks = <&pck1>; + clock-names = "xvclk"; + + assigned-clocks = <&pck1>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/ov2659.txt b/Documentation/devicetree/bindings/media/i2c/ov2659.txt new file mode 100644 index 0000000000000000000000000000000000000000..cabc7d827dfbc3a08f5c03e55c2228b584995f43 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ov2659.txt @@ -0,0 +1,38 @@ +* OV2659 1/5-Inch 2Mp SOC Camera + +The Omnivision OV2659 is a 1/5-inch SOC camera, with an active array size of +1632H x 1212V. It is programmable through a SCCB. The OV2659 sensor supports +multiple resolutions output, such as UXGA, SVGA, 720p. It also can support +YUV422, RGB565/555 or raw RGB output formats. + +Required Properties: +- compatible: Must be "ovti,ov2659" +- reg: I2C slave address +- clocks: reference to the xvclk input clock. +- clock-names: should be "xvclk". +- link-frequencies: target pixel clock frequency. + +For further reading on port node refer to +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + + i2c0@1c22000 { + ... + ... + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&clk_ov2659 0>; + clock-names = "xvclk"; + + port { + ov2659_0: endpoint { + remote-endpoint = <&vpfe_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; + ... + }; diff --git a/Documentation/devicetree/bindings/media/ti,omap3isp.txt b/Documentation/devicetree/bindings/media/ti,omap3isp.txt new file mode 100644 index 0000000000000000000000000000000000000000..ac23de8556412c52710f46c3ea015d2976c96dad --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,omap3isp.txt @@ -0,0 +1,71 @@ +OMAP 3 ISP Device Tree bindings +=============================== + +The DT definitions can be found in include/dt-bindings/media/omap3-isp.h. + +Required properties +=================== + +compatible : must contain "ti,omap3-isp" + +reg : the two registers sets (physical address and length) for the + ISP. The first set contains the core ISP registers up to + the end of the SBL block. The second set contains the + CSI PHYs and receivers registers. +interrupts : the ISP interrupt specifier +iommus : phandle and IOMMU specifier for the IOMMU that serves the ISP +syscon : the phandle and register offset to the Complex I/O or CSI-PHY + register +ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430) + 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630) +#clock-cells : Must be 1 --- the ISP provides two external clocks, + cam_xclka and cam_xclkb, at indices 0 and 1, + respectively. Please find more information on common + clock bindings in ../clock/clock-bindings.txt. + +Port nodes (optional) +--------------------- + +More documentation on these bindings is available in +video-interfaces.txt in the same directory. + +reg : The interface: + 0 - parallel (CCDC) + 1 - CSIPHY1 -- CSI2C / CCP2B on 3630; + CSI1 -- CSIb on 3430 + 2 - CSIPHY2 -- CSI2A / CCP2B on 3630; + CSI2 -- CSIa on 3430 + +Optional properties +=================== + +vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1 +vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2 + +Endpoint nodes +-------------- + +lane-polarities : lane polarity (required on CSI-2) + 0 -- not inverted; 1 -- inverted +data-lanes : an array of data lanes from 1 to 3. The length can + be either 1 or 2. (required on CSI-2) +clock-lanes : the clock lane (from 1 to 3). (required on CSI-2) + + +Example +======= + + isp@480bc000 { + compatible = "ti,omap3-isp"; + reg = <0x480bc000 0x12fc + 0x480bd800 0x0600>; + interrupts = <24>; + iommus = <&mmu_isp>; + syscon = <&scm_conf 0x2f0>; + ti,phy-type = ; + #clock-cells = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt index 571b4c60665f72939aa7ef956e301ee49c13facc..9cd2a369125d440cb393582c1b7d0f253ef25d06 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -106,6 +106,12 @@ Optional endpoint properties - link-frequencies: Allowed data bus frequencies. For MIPI CSI-2, for instance, this is the actual frequency of the bus, not bits per clock per lane value. An array of 64-bit unsigned integers. +- lane-polarities: an array of polarities of the lanes starting from the clock + lane and followed by the data lanes in the same order as in data-lanes. + Valid values are 0 (normal) and 1 (inverted). The length of the array + should be the combined length of data-lanes and clock-lanes properties. + If the lane-polarities property is omitted, the value must be interpreted + as 0 (normal). This property is valid for serial busses only. Example diff --git a/Documentation/devicetree/bindings/media/xilinx/video.txt b/Documentation/devicetree/bindings/media/xilinx/video.txt new file mode 100644 index 0000000000000000000000000000000000000000..cbd46fa0988fe10274b62bbfa537febe805c236b --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/video.txt @@ -0,0 +1,35 @@ +DT bindings for Xilinx video IP cores +------------------------------------- + +Xilinx video IP cores process video streams by acting as video sinks and/or +sources. They are connected by links through their input and output ports, +creating a video pipeline. + +Each video IP core is represented by an AMBA bus child node in the device +tree using bindings documented in this directory. Connections between the IP +cores are represented as defined in ../video-interfaces.txt. + +The whole pipeline is represented by an AMBA bus child node in the device +tree using bindings documented in ./xlnx,video.txt. + +Common properties +----------------- + +The following properties are common to all Xilinx video IP cores. + +- xlnx,video-format: This property represents a video format transmitted on an + AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream + Video IP and System Design Guide" [UG934]. How the format relates to the IP + core is decribed in the IP core bindings documentation. + +- xlnx,video-width: This property qualifies the video format with the sample + width expressed as a number of bits per pixel component. All components must + use the same width. + +- xlnx,cfa-pattern: When the video format is set to Mono/Sensor, this property + describes the sensor's color filter array pattern. Supported values are + "bggr", "gbrg", "grbg", "rggb" and "mono". If not specified, the pattern + defaults to "mono". + + +[UG934] http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tc.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tc.txt new file mode 100644 index 0000000000000000000000000000000000000000..2aed3b4a6cf1ac8a73cc81e861b8ec5c1d7fe74d --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tc.txt @@ -0,0 +1,33 @@ +Xilinx Video Timing Controller (VTC) +------------------------------------ + +The Video Timing Controller is a general purpose video timing generator and +detector. + +Required properties: + + - compatible: Must be "xlnx,v-tc-6.1". + + - reg: Physical base address and length of the registers set for the device. + + - clocks: Must contain a clock specifier for the VTC core and timing + interfaces clock. + +Optional properties: + + - xlnx,detector: The VTC has a timing detector + - xlnx,generator: The VTC has a timing generator + + At least one of the xlnx,detector and xlnx,generator properties must be + specified. + + +Example: + + vtc: vtc@43c40000 { + compatible = "xlnx,v-tc-6.1"; + reg = <0x43c40000 0x10000>; + + clocks = <&clkc 15>; + xlnx,generator; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt new file mode 100644 index 0000000000000000000000000000000000000000..9dd86b3db937720899aacfd5fb65fef8eb5be194 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt @@ -0,0 +1,71 @@ +Xilinx Video Test Pattern Generator (TPG) +----------------------------------------- + +Required properties: + +- compatible: Must contain at least one of + + "xlnx,v-tpg-5.0" (TPG version 5.0) + "xlnx,v-tpg-6.0" (TPG version 6.0) + + TPG versions backward-compatible with previous versions should list all + compatible versions in the newer to older order. + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the video core clock. + +- xlnx,video-format, xlnx,video-width: Video format and width, as defined in + video.txt. + +- port: Video port, using the DT bindings defined in ../video-interfaces.txt. + The TPG has a single output port numbered 0. + +Optional properties: + +- xlnx,vtc: A phandle referencing the Video Timing Controller that generates + video timings for the TPG test patterns. + +- timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG + input. The GPIO active level corresponds to the selection of VTC-generated + video timings. + +The xlnx,vtc and timing-gpios properties are mandatory when the TPG is +synthesized with two ports and forbidden when synthesized with one port. + +Example: + + tpg_0: tpg@40050000 { + compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0"; + reg = <0x40050000 0x10000>; + clocks = <&clkc 15>; + + xlnx,vtc = <&vtc_3>; + timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = ; + xlnx,video-width = <8>; + + tpg_in: endpoint { + remote-endpoint = <&adv7611_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = ; + xlnx,video-width = <8>; + + tpg1_out: endpoint { + remote-endpoint = <&switch_in0>; + }; + }: + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,video.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,video.txt new file mode 100644 index 0000000000000000000000000000000000000000..5a022702360857d371240d59d0decbfc80861eda --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,video.txt @@ -0,0 +1,55 @@ +Xilinx Video IP Pipeline (VIPP) +------------------------------- + +General concept +--------------- + +Xilinx video IP pipeline processes video streams through one or more Xilinx +video IP cores. Each video IP core is represented as documented in video.txt +and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT +node of the VIPP represents as a top level node of the pipeline and defines +mappings between DMAs and the video IP cores. + +Required properties: + +- compatible: Must be "xlnx,video". + +- dmas, dma-names: List of one DMA specifier and identifier string (as defined + in Documentation/devicetree/bindings/dma/dma.txt) per port. Each port + requires a DMA channel with the identifier string set to "port" followed by + the port index. + +- ports: Video port, using the DT bindings defined in ../video-interfaces.txt. + +Required port properties: + +- direction: should be either "input" or "output" depending on the direction + of stream. + +Example: + + video_cap { + compatible = "xlnx,video"; + dmas = <&vdma_1 1>, <&vdma_3 1>; + dma-names = "port0", "port1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + direction = "input"; + vcap0_in0: endpoint { + remote-endpoint = <&scaler0_out>; + }; + }; + port@1 { + reg = <1>; + direction = "input"; + vcap0_in1: endpoint { + remote-endpoint = <&switch_out1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt b/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt new file mode 100644 index 0000000000000000000000000000000000000000..f936b5589b1953030adc2563c88555398a49e839 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt @@ -0,0 +1,75 @@ +* Ingenic JZ4780 NAND/external memory controller (NEMC) + +This file documents the device tree bindings for the NEMC external memory +controller in Ingenic JZ4780 + +Required properties: +- compatible: Should be set to one of: + "ingenic,jz4780-nemc" (JZ4780) +- reg: Should specify the NEMC controller registers location and length. +- clocks: Clock for the NEMC controller. +- #address-cells: Must be set to 2. +- #size-cells: Must be set to 1. +- ranges: A set of ranges for each bank describing the physical memory layout. + Each should specify the following 4 integer values: + + 0 + +Each child of the NEMC node describes a device connected to the NEMC. + +Required child node properties: +- reg: Should contain at least one register specifier, given in the following + format: + + + + Multiple registers can be specified across multiple banks. This is needed, + for example, for packaged NAND devices with multiple dies. Such devices + should be grouped into a single node. + +Optional child node properties: +- ingenic,nemc-bus-width: Specifies the bus width in bits. Defaults to 8 bits. +- ingenic,nemc-tAS: Address setup time in nanoseconds. +- ingenic,nemc-tAH: Address hold time in nanoseconds. +- ingenic,nemc-tBP: Burst pitch time in nanoseconds. +- ingenic,nemc-tAW: Access wait time in nanoseconds. +- ingenic,nemc-tSTRV: Static memory recovery time in nanoseconds. + +If a child node references multiple banks in its "reg" property, the same value +for all optional parameters will be configured for all banks. If any optional +parameters are omitted, they will be left unchanged from whatever they are +configured to when the NEMC device is probed (which may be the reset value as +given in the hardware reference manual, or a value configured by the boot +loader). + +Example (NEMC node with a NAND child device attached at CS1): + +nemc: nemc@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + + #address-cells = <2>; + #size-cells = <1>; + + ranges = <1 0 0x1b000000 0x1000000 + 2 0 0x1a000000 0x1000000 + 3 0 0x19000000 0x1000000 + 4 0 0x18000000 0x1000000 + 5 0 0x17000000 0x1000000 + 6 0 0x16000000 0x1000000>; + + clocks = <&cgu JZ4780_CLK_NEMC>; + + nand: nand@1 { + compatible = "ingenic,jz4780-nand"; + reg = <1 0 0x1000000>; + + ingenic,nemc-tAS = <10>; + ingenic,nemc-tAH = <5>; + ingenic,nemc-tBP = <10>; + ingenic,nemc-tAW = <15>; + ingenic,nemc-tSTRV = <100>; + + ... + }; +}; diff --git a/Documentation/devicetree/bindings/mfd/bcm590xx.txt b/Documentation/devicetree/bindings/mfd/brcm,bcm59056.txt similarity index 100% rename from Documentation/devicetree/bindings/mfd/bcm590xx.txt rename to Documentation/devicetree/bindings/mfd/brcm,bcm59056.txt diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt new file mode 100644 index 0000000000000000000000000000000000000000..e90519d566a30a1a3ca2c003f15660d84b32a792 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt @@ -0,0 +1,22 @@ +QCOM Top Control and Status Register + +Qualcomm devices have a set of registers that provide various control and status +functions for their peripherals. This node is intended to allow access to these +registers via syscon. + +Required properties: +- compatible: Should contain: + "qcom,tcsr-ipq8064", "syscon" for IPQ8064 + "qcom,tcsr-apq8064", "syscon" for APQ8064 + "qcom,tcsr-msm8660", "syscon" for MSM8660 + "qcom,tcsr-msm8960", "syscon" for MSM8960 + "qcom,tcsr-msm8974", "syscon" for MSM8974 + "qcom,tcsr-apq8084", "syscon" for APQ8084 + "qcom,tcsr-msm8916", "syscon" for MSM8916 +- reg: Address range for TCSR registers + +Example: + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8960", "syscon"; + reg = <0x1a400000 0x100>; + }; diff --git a/Documentation/devicetree/bindings/mips/brcm/bmips.txt b/Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt similarity index 100% rename from Documentation/devicetree/bindings/mips/brcm/bmips.txt rename to Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt diff --git a/Documentation/devicetree/bindings/misc/smc.txt b/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt similarity index 100% rename from Documentation/devicetree/bindings/misc/smc.txt rename to Documentation/devicetree/bindings/misc/brcm,kona-smc.txt diff --git a/Documentation/devicetree/bindings/misc/lis302.txt b/Documentation/devicetree/bindings/misc/lis302.txt index 6def86f6b053bea992004509bd812c4e56627aed..2a19bff9693fc55a7b61bb45dcf32963bc7f224a 100644 --- a/Documentation/devicetree/bindings/misc/lis302.txt +++ b/Documentation/devicetree/bindings/misc/lis302.txt @@ -46,11 +46,18 @@ Optional properties for all bus drivers: interrupt 2 - st,wakeup-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for upper/lower limit + - st,wakeup-threshold: set wakeup threshold + - st,wakeup2-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for + upper/lower limit for second wakeup + engine. + - st,wakeup2-threshold: set wakeup threshold for second wakeup + engine. - st,highpass-cutoff-hz=: 1, 2, 4 or 8 for 1Hz, 2Hz, 4Hz or 8Hz of highpass cut-off frequency - st,hipass{1,2}-disable: disable highpass 1/2. - st,default-rate=: set the default rate - - st,axis-{x,y,z}=: set the axis to map to the three coordinates + - st,axis-{x,y,z}=: set the axis to map to the three coordinates. + Negative values can be used for inverted axis. - st,{min,max}-limit-{x,y,z} set the min/max limits for x/y/z axis (used by self-test) diff --git a/Documentation/devicetree/bindings/mmc/kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt similarity index 100% rename from Documentation/devicetree/bindings/mmc/kona-sdhci.txt rename to Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt similarity index 61% rename from Documentation/devicetree/bindings/mtd/m25p80.txt rename to Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt index 4611aa83531b9f6834797baec0dfa7c961c74d0e..2bee68103b0112ecc106edc25a74a33f69462cc8 100644 --- a/Documentation/devicetree/bindings/mtd/m25p80.txt +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt @@ -3,10 +3,13 @@ Required properties: - #address-cells, #size-cells : Must be present if the device has sub-nodes representing partitions. -- compatible : Should be the manufacturer and the name of the chip. Bear in mind - the DT binding is not Linux-only, but in case of Linux, see the - "spi_nor_ids" table in drivers/mtd/spi-nor/spi-nor.c for the list - of supported chips. +- compatible : May include a device-specific string consisting of the + manufacturer and name of the chip. Bear in mind the DT binding + is not Linux-only, but in case of Linux, see the "m25p_ids" + table in drivers/mtd/devices/m25p80.c for the list of supported + chips. + Must also include "jedec,spi-nor" for any SPI NOR flash that can + be identified by the JEDEC READ ID opcode (0x9F). - reg : Chip-Select number - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at @@ -22,7 +25,7 @@ Example: flash: m25p80@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spansion,m25p80"; + compatible = "spansion,m25p80", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; m25p,fast-read; diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt index de8b517a5521914c6c37df4dc6d250abf2ffb742..4f833e3c4f516e90747865fefb7de633e240f6c3 100644 --- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt +++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt @@ -14,7 +14,7 @@ Optional properties: - marvell,nand-enable-arbiter: Set to enable the bus arbiter - marvell,nand-keep-config: Set to keep the NAND controller config as set by the bootloader - - num-cs: Number of chipselect lines to usw + - num-cs: Number of chipselect lines to use - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false - nand-ecc-strength: number of bits to correct per ECC step diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt index 0273adb8638ca507af4261b922a42ff5344fbc40..086d6f44c4b976b73b364d491fc290a97b00bf61 100644 --- a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt +++ b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt @@ -21,7 +21,7 @@ Optional properties: - nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft", "soft_bch" or "none") -see Documentation/devicetree/mtd/nand.txt for generic bindings. +see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. Examples: diff --git a/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt b/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt deleted file mode 100644 index 8db32384a4866e56094aa96e86ac8765ccdf519c..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt +++ /dev/null @@ -1,48 +0,0 @@ -* AMD 10GbE PHY driver (amd-xgbe-phy) - -Required properties: -- compatible: Should be "amd,xgbe-phy-seattle-v1a" and - "ethernet-phy-ieee802.3-c45" -- reg: Address and length of the register sets for the device - - SerDes Rx/Tx registers - - SerDes integration registers (1/2) - - SerDes integration registers (2/2) -- interrupt-parent: Should be the phandle for the interrupt controller - that services interrupts for this device -- interrupts: Should contain the amd-xgbe-phy interrupt. - -Optional properties: -- amd,speed-set: Speed capabilities of the device - 0 - 1GbE and 10GbE (default) - 1 - 2.5GbE and 10GbE - -The following optional properties are represented by an array with each -value corresponding to a particular speed. The first array value represents -the setting for the 1GbE speed, the second value for the 2.5GbE speed and -the third value for the 10GbE speed. All three values are required if the -property is used. -- amd,serdes-blwc: Baseline wandering correction enablement - 0 - Off - 1 - On -- amd,serdes-cdr-rate: CDR rate speed selection -- amd,serdes-pq-skew: PQ (data sampling) skew -- amd,serdes-tx-amp: TX amplitude boost -- amd,serdes-dfe-tap-config: DFE taps available to run -- amd,serdes-dfe-tap-enable: DFE taps to enable - -Example: - xgbe_phy@e1240800 { - compatible = "amd,xgbe-phy-seattle-v1a", "ethernet-phy-ieee802.3-c45"; - reg = <0 0xe1240800 0 0x00400>, - <0 0xe1250000 0 0x00060>, - <0 0xe1250080 0 0x00004>; - interrupt-parent = <&gic>; - interrupts = <0 323 4>; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <30>; - amd,serdes-tx-amp = <15>, <15>, <10>; - amd,serdes-dfe-tap-config = <3>, <3>, <1>; - amd,serdes-dfe-tap-enable = <0>, <0>, <127>; - }; diff --git a/Documentation/devicetree/bindings/net/amd-xgbe.txt b/Documentation/devicetree/bindings/net/amd-xgbe.txt index 26efd526d16c29cc45de438aef24adb8f34898bd..4bb624a73b5409555c529a0c85e2ee10d69ce3b8 100644 --- a/Documentation/devicetree/bindings/net/amd-xgbe.txt +++ b/Documentation/devicetree/bindings/net/amd-xgbe.txt @@ -5,12 +5,16 @@ Required properties: - reg: Address and length of the register sets for the device - MAC registers - PCS registers + - SerDes Rx/Tx registers + - SerDes integration registers (1/2) + - SerDes integration registers (2/2) - interrupt-parent: Should be the phandle for the interrupt controller that services interrupts for this device - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt listed is required and is the general device interrupt. If the optional amd,per-channel-interrupt property is specified, then one additional - interrupt for each DMA channel supported by the device should be specified + interrupt for each DMA channel supported by the device should be specified. + The last interrupt listed should be the PCS auto-negotiation interrupt. - clocks: - DMA clock for the amd-xgbe device (used for calculating the correct Rx interrupt watchdog timer value on a DMA channel @@ -19,7 +23,6 @@ Required properties: - clock-names: Should be the names of the clocks - "dma_clk" for the DMA clock - "ptp_clk" for the PTP clock -- phy-handle: See ethernet.txt file in the same directory - phy-mode: See ethernet.txt file in the same directory Optional properties: @@ -29,19 +32,46 @@ Optional properties: - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate a unique interrupt for each DMA channel - this requires an additional interrupt be configured for each DMA channel +- amd,speed-set: Speed capabilities of the device + 0 - 1GbE and 10GbE (default) + 1 - 2.5GbE and 10GbE + +The following optional properties are represented by an array with each +value corresponding to a particular speed. The first array value represents +the setting for the 1GbE speed, the second value for the 2.5GbE speed and +the third value for the 10GbE speed. All three values are required if the +property is used. +- amd,serdes-blwc: Baseline wandering correction enablement + 0 - Off + 1 - On +- amd,serdes-cdr-rate: CDR rate speed selection +- amd,serdes-pq-skew: PQ (data sampling) skew +- amd,serdes-tx-amp: TX amplitude boost +- amd,serdes-dfe-tap-config: DFE taps available to run +- amd,serdes-dfe-tap-enable: DFE taps to enable Example: xgbe@e0700000 { compatible = "amd,xgbe-seattle-v1a"; reg = <0 0xe0700000 0 0x80000>, - <0 0xe0780000 0 0x80000>; + <0 0xe0780000 0 0x80000>, + <0 0xe1240800 0 0x00400>, + <0 0xe1250000 0 0x00060>, + <0 0xe1250080 0 0x00004>; interrupt-parent = <&gic>; interrupts = <0 325 4>, - <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>; + <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, + <0 323 4>; amd,per-channel-interrupt; clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; clock-names = "dma_clk", "ptp_clk"; - phy-handle = <&phy>; phy-mode = "xgmii"; mac-address = [ 02 a1 a2 a3 a4 a5 ]; + amd,speed-set = <0>; + amd,serdes-blwc = <1>, <1>, <0>; + amd,serdes-cdr-rate = <2>, <2>, <7>; + amd,serdes-pq-skew = <10>, <10>, <30>; + amd,serdes-tx-amp = <15>, <15>, <10>; + amd,serdes-dfe-tap-config = <3>, <3>, <1>; + amd,serdes-dfe-tap-enable = <0>, <0>, <127>; }; diff --git a/Documentation/devicetree/bindings/net/broadcom-sf2.txt b/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt similarity index 100% rename from Documentation/devicetree/bindings/net/broadcom-sf2.txt rename to Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt diff --git a/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt b/Documentation/devicetree/bindings/net/brcm,bcmgenet.txt similarity index 100% rename from Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt rename to Documentation/devicetree/bindings/net/brcm,bcmgenet.txt diff --git a/Documentation/devicetree/bindings/net/broadcom-systemport.txt b/Documentation/devicetree/bindings/net/brcm,systemport.txt similarity index 100% rename from Documentation/devicetree/bindings/net/broadcom-systemport.txt rename to Documentation/devicetree/bindings/net/brcm,systemport.txt diff --git a/Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt b/Documentation/devicetree/bindings/net/brcm,unimac-mdio.txt similarity index 100% rename from Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt rename to Documentation/devicetree/bindings/net/brcm,unimac-mdio.txt diff --git a/Documentation/devicetree/bindings/net/cdns-emac.txt b/Documentation/devicetree/bindings/net/cdns-emac.txt index abd67c13d3442228834e7df36a53a71454132160..4451ee9732239b50d8329339eb57662e639c24b4 100644 --- a/Documentation/devicetree/bindings/net/cdns-emac.txt +++ b/Documentation/devicetree/bindings/net/cdns-emac.txt @@ -3,7 +3,8 @@ Required properties: - compatible: Should be "cdns,[-]{emac}" Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC. - or the generic form: "cdns,emac". + Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. + Or the generic form: "cdns,emac". - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt - phy-mode: see ethernet.txt file in the same directory. diff --git a/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt new file mode 100644 index 0000000000000000000000000000000000000000..6d7ab4e524d45b9abdecf5e686dc2bf2512eaacb --- /dev/null +++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt @@ -0,0 +1,35 @@ +* IPQ806x DWMAC Ethernet controller + +The device inherits all the properties of the dwmac/stmmac devices +described in the file net/stmmac.txt with the following changes. + +Required properties: + +- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac" + and any applicable more detailed version number + described in net/stmmac.txt + +- qcom,nss-common: should contain a phandle to a syscon device mapping the + nss-common registers. + +- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the + qsgmii-csr registers. + +Example: + + gmac: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37000000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE1_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE1_RESET>; + reset-names = "stmmaceth"; + }; diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index ba19d671e8081148529368442fa39be451294608..8ec5fdf444e99e7b48a786fc8ead23d2150c0926 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -9,6 +9,7 @@ Required properties: the Cadence GEM, or the generic form: "cdns,gem". Use "cdns,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. Use "cdns,sama5d4-gem" for the Gigabit IP available on Atmel sama5d4 SoCs. + Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt - phy-mode: See ethernet.txt file in the same directory. diff --git a/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.txt b/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.txt new file mode 100644 index 0000000000000000000000000000000000000000..7edba1264f6f2bf194b6e261a4ce50e4d2622c22 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.txt @@ -0,0 +1,20 @@ +* NXP LPC1850 GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: + - compatible: Should contain "nxp,lpc1850-dwmac" + +Examples: + +mac: ethernet@40010000 { + compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; + reg = <0x40010000 0x2000>; + interrupts = <5>; + interrupt-names = "macirq"; + clocks = <&ccu1 CLK_CPU_ETHERNET>; + clock-names = "stmmaceth"; + resets = <&rgu 22>; + reset-names = "stmmaceth"; +} diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt index 40831fbaff72102d6ff608ae06c1ddf4bedcdbae..525e1658f2da5ca9ed22594fda97a25646ac2e20 100644 --- a/Documentation/devicetree/bindings/net/phy.txt +++ b/Documentation/devicetree/bindings/net/phy.txt @@ -30,6 +30,9 @@ Optional Properties: - max-speed: Maximum PHY supported speed (10, 100, 1000...) +- broken-turn-around: If set, indicates the PHY device does not correctly + release the turn around line low at the end of a MDIO transaction. + Example: ethernet-phy@0 { diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt new file mode 100644 index 0000000000000000000000000000000000000000..58d935b58598102f4fab0b132ca0fbfadf544fab --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt @@ -0,0 +1,25 @@ +* Texas Instruments - dp83867 Giga bit ethernet phy + +Required properties: + - reg - The ID number for the phy, usually a small integer + - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h + for applicable values + +Default child nodes are standard Ethernet PHY device +nodes as described in Documentation/devicetree/bindings/net/phy.txt + +Example: + + ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + }; + +Datasheet can be found: +http://www.ti.com/product/DP83867IR/datasheet diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt new file mode 100644 index 0000000000000000000000000000000000000000..2a3d90de18eeaa763f41280d6570fa3c217c9e63 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt @@ -0,0 +1,47 @@ +TI Wilink 6/7/8 (wl12xx/wl18xx) SDIO devices + +This node provides properties for controlling the wilink wireless device. The +node is expected to be specified as a child node to the SDIO controller that +connects the device to the system. + +Required properties: + - compatible: should be one of the following: + * "ti,wl1271" + * "ti,wl1273" + * "ti,wl1281" + * "ti,wl1283" + * "ti,wl1801" + * "ti,wl1805" + * "ti,wl1807" + * "ti,wl1831" + * "ti,wl1835" + * "ti,wl1837" + - interrupts : specifies attributes for the out-of-band interrupt. + +Optional properties: + - interrupt-parent : the phandle for the interrupt controller to which the + device interrupts are connected. + - ref-clock-frequency : ref clock frequency in Hz + - tcxo-clock-frequency : tcxo clock frequency in Hz + +Note: the *-clock-frequency properties assume internal clocks. In case of external +clock, new bindings (for parsing the clock nodes) have to be added. + +Example: + +&mmc3 { + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/Documentation/devicetree/bindings/panel/ampire,am800480r3tmqwa1h.txt b/Documentation/devicetree/bindings/panel/ampire,am800480r3tmqwa1h.txt new file mode 100644 index 0000000000000000000000000000000000000000..83e2cae1cc1b48eb7830e923322fa38f043537d5 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/ampire,am800480r3tmqwa1h.txt @@ -0,0 +1,7 @@ +Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel + +Required properties: +- compatible: should be "ampire,am800480r3tmqwa1h" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/panel/auo,b101ean01.txt b/Documentation/devicetree/bindings/panel/auo,b101ean01.txt new file mode 100644 index 0000000000000000000000000000000000000000..3590b0741619cec0ff7d31b2a6d4b1ff2210cd00 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/auo,b101ean01.txt @@ -0,0 +1,7 @@ +AU Optronics Corporation 10.1" WSVGA TFT LCD panel + +Required properties: +- compatible: should be "auo,b101ean01" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/panel/innolux,at043tn24.txt b/Documentation/devicetree/bindings/panel/innolux,at043tn24.txt new file mode 100644 index 0000000000000000000000000000000000000000..4104226b61bc7a4a08401d34aa27044ff02dd9ad --- /dev/null +++ b/Documentation/devicetree/bindings/panel/innolux,at043tn24.txt @@ -0,0 +1,7 @@ +Innolux AT043TN24 4.3" WQVGA TFT LCD panel + +Required properties: +- compatible: should be "innolux,at043tn24" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/panel/innolux,zj070na-01p.txt b/Documentation/devicetree/bindings/panel/innolux,zj070na-01p.txt new file mode 100644 index 0000000000000000000000000000000000000000..824f87f1526ded4a68ed5bb779d5dd7c15e16f72 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/innolux,zj070na-01p.txt @@ -0,0 +1,7 @@ +Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel + +Required properties: +- compatible: should be "innolux,zj070na-01p" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/panel/ortustech,com43h4m85ulc.txt b/Documentation/devicetree/bindings/panel/ortustech,com43h4m85ulc.txt new file mode 100644 index 0000000000000000000000000000000000000000..de19e9398618b70c5f27adf1debb54927675ffcd --- /dev/null +++ b/Documentation/devicetree/bindings/panel/ortustech,com43h4m85ulc.txt @@ -0,0 +1,7 @@ +OrtusTech COM43H4M85ULC Blanview 3.7" TFT-LCD panel + +Required properties: +- compatible: should be "ortustech,com43h4m85ulc" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/panel/samsung,ltn140at29-301.txt b/Documentation/devicetree/bindings/panel/samsung,ltn140at29-301.txt new file mode 100644 index 0000000000000000000000000000000000000000..e7f969d891cc7c85e97bbe0d5a4b2b4a65687857 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/samsung,ltn140at29-301.txt @@ -0,0 +1,7 @@ +Samsung Electronics 14" WXGA (1366x768) TFT LCD panel + +Required properties: +- compatible: should be "samsung,ltn140at29-301" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/panel/shelly,sca07010-bfn-lnn.txt b/Documentation/devicetree/bindings/panel/shelly,sca07010-bfn-lnn.txt new file mode 100644 index 0000000000000000000000000000000000000000..fc1ea9e26c940a82e4139ad137e2d6729f546b33 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/shelly,sca07010-bfn-lnn.txt @@ -0,0 +1,7 @@ +Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel + +Required properties: +- compatible: should be "shelly,sca07010-bfn-lnn" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/phy/bcm-phy.txt b/Documentation/devicetree/bindings/phy/brcm,kona-usb2-phy.txt similarity index 100% rename from Documentation/devicetree/bindings/phy/bcm-phy.txt rename to Documentation/devicetree/bindings/phy/brcm,kona-usb2-phy.txt diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt new file mode 100644 index 0000000000000000000000000000000000000000..65cc0345747d73f540d6c5a4e8b18acc1618953b --- /dev/null +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt @@ -0,0 +1,59 @@ +Freescale i.MX General Power Controller +======================================= + +The i.MX6Q General Power Control (GPC) block contains DVFS load tracking +counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power +domains. + +Required properties: +- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc" +- reg: should be register base and length as documented in the + datasheet +- interrupts: Should contain GPC interrupt request 1 +- pu-supply: Link to the LDO regulator powering the PU power domain +- clocks: Clock phandles to devices in the PU power domain that need + to be enabled during domain power-up for reset propagation. +- #power-domain-cells: Should be 1, see below: + +The gpc node is a power-controller as documented by the generic power domain +bindings in Documentation/devicetree/bindings/power/power_domain.txt. + +Example: + + gpc: gpc@020dc000 { + compatible = "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, + <0 90 IRQ_TYPE_LEVEL_HIGH>; + pu-supply = <®_pu>; + clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU2D_AXI>, + <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_VPU_AXI>; + #power-domain-cells = <1>; + }; + + +Specifying power domain for IP modules +====================================== + +IP cores belonging to a power domain should contain a 'power-domains' property +that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying +the power domain the device belongs to. + +Example of a device that is part of the PU power domain: + + vpu: vpu@02040000 { + reg = <0x02040000 0x3c000>; + /* ... */ + power-domains = <&gpc 1>; + /* ... */ + }; + +The following DOMAIN_INDEX values are valid for i.MX6Q: +ARM_DOMAIN 0 +PU_DOMAIN 1 +The following additional DOMAIN_INDEX value is valid for i.MX6SL: +DISPLAY_DOMAIN 2 diff --git a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt index cc3b1f0a9b1a2b75125a2f98af131ff107f0258b..beda7d2efc304350aa7dc48f2cc6212bfc6ee795 100644 --- a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt +++ b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt @@ -11,6 +11,7 @@ Required properties: - compatible: Should be "renesas,sysc-", "renesas,sysc-rmobile" as fallback. Examples with soctypes are: + - "renesas,sysc-r8a73a4" (R-Mobile APE6) - "renesas,sysc-r8a7740" (R-Mobile A1) - "renesas,sysc-sh73a0" (SH-Mobile AG5) - reg: Two address start and address range blocks for the device: diff --git a/Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt similarity index 100% rename from Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt rename to Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt index b50d7a6d9d7f88ca00524533981c44726e860d3f..e00c2e9f484dceea28c71df05461f0e61336f6ec 100644 --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt @@ -1,10 +1,17 @@ Freescale i.MX PWM controller Required properties: -- compatible: should be "fsl,-pwm" +- compatible : should be "fsl,-pwm" and one of the following + compatible strings: + - "fsl,imx1-pwm" for PWM compatible with the one integrated on i.MX1 + - "fsl,imx27-pwm" for PWM compatible with the one integrated on i.MX27 - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. See pwm.txt in this directory for a description of the cells format. +- clocks : Clock specifiers for both ipg and per clocks. +- clock-names : Clock names should include both "ipg" and "per" +See the clock consumer binding, + Documentation/devicetree/bindings/clock/clock-bindings.txt - interrupts: The interrupt for the pwm controller Example: @@ -13,5 +20,8 @@ pwm1: pwm@53fb4000 { #pwm-cells = <2>; compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb4000 0x4000>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; + clock-names = "ipg", "per"; interrupts = <61>; }; diff --git a/Documentation/devicetree/bindings/arm/bcm/kona-resetmgr.txt b/Documentation/devicetree/bindings/reset/brcm,bcm21664-resetmgr.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm/kona-resetmgr.txt rename to Documentation/devicetree/bindings/reset/brcm,bcm21664-resetmgr.txt diff --git a/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt b/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt new file mode 100644 index 0000000000000000000000000000000000000000..be789685a1c24256e8b9846121ccb407d9f39e94 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt @@ -0,0 +1,30 @@ +Abracon ABX80X I2C ultra low power RTC/Alarm chip + +The Abracon ABX80X family consist of the ab0801, ab0803, ab0804, ab0805, ab1801, +ab1803, ab1804 and ab1805. The ab0805 is the superset of ab080x and the ab1805 +is the superset of ab180x. + +Required properties: + + - "compatible": should one of: + "abracon,abx80x" + "abracon,ab0801" + "abracon,ab0803" + "abracon,ab0804" + "abracon,ab0805" + "abracon,ab1801" + "abracon,ab1803" + "abracon,ab1804" + "abracon,ab1805" + Using "abracon,abx80x" will enable chip autodetection. + - "reg": I2C bus address of the device + +Optional properties: + +The abx804 and abx805 have a trickle charger that is able to charge the +connected battery or supercap. Both the following properties have to be defined +and valid to enable charging: + + - "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V) + - "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output + resistor, the other values are in ohm. diff --git a/Documentation/devicetree/bindings/serial/atmel-usart.txt b/Documentation/devicetree/bindings/serial/atmel-usart.txt index a6391e70a8fd84086b8982a6e3844f59dfb20949..90787aa2e648c55a91df5a71b9b10d7f4f7ae7c7 100644 --- a/Documentation/devicetree/bindings/serial/atmel-usart.txt +++ b/Documentation/devicetree/bindings/serial/atmel-usart.txt @@ -1,9 +1,10 @@ * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) Required properties: -- compatible: Should be "atmel,-usart" +- compatible: Should be "atmel,-usart" or "atmel,-dbgu" The compatible indicated will be the first SoC to support an additional mode or an USART new feature. + For the dbgu UART, use "atmel,-dbgu", "atmel,-usart" - reg: Should contain registers location and length - interrupts: Should contain interrupt - clock-names: tuple listing input clock names. diff --git a/Documentation/devicetree/bindings/serial/bcm63xx-uart.txt b/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt similarity index 100% rename from Documentation/devicetree/bindings/serial/bcm63xx-uart.txt rename to Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt index 342eedd1005021f28c34696e1f80b96a4c620d5e..54c2a155c78323a70f9dc66eb62457eba1143232 100644 --- a/Documentation/devicetree/bindings/serial/omap_serial.txt +++ b/Documentation/devicetree/bindings/serial/omap_serial.txt @@ -4,7 +4,27 @@ Required properties: - compatible : should be "ti,omap2-uart" for OMAP2 controllers - compatible : should be "ti,omap3-uart" for OMAP3 controllers - compatible : should be "ti,omap4-uart" for OMAP4 controllers +- reg : address and length of the register space +- interrupts or interrupts-extended : Should contain the uart interrupt + specifier or both the interrupt + controller phandle and interrupt + specifier. - ti,hwmods : Must be "uart", n being the instance number (1-based) Optional properties: - clock-frequency : frequency of the clock input to the UART +- dmas : DMA specifier, consisting of a phandle to the DMA controller + node and a DMA channel number. +- dma-names : "rx" for receive channel, "tx" for transmit channel. + +Example: + + uart4: serial@49042000 { + compatible = "ti,omap3-uart"; + reg = <0x49042000 0x400>; + interrupts = <80>; + dmas = <&sdma 81 &sdma 82>; + dma-names = "tx", "rx"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt new file mode 100644 index 0000000000000000000000000000000000000000..ddeb5b6a53c161c37d1cc849404881d06e901a01 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -0,0 +1,58 @@ +MediaTek PMIC Wrapper Driver + +This document describes the binding for the MediaTek PMIC wrapper. + +On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface +is not directly visible to the CPU, but only through the PMIC wrapper +inside the SoC. The communication between the SoC and the PMIC can +optionally be encrypted. Also a non standard Dual IO SPI mode can be +used to increase speed. + +IP Pairing + +on MT8135 the pins of some SoC internal peripherals can be on the PMIC. +The signals of these pins are routed over the SPI bus using the pwrap +bridge. In the binding description below the properties needed for bridging +are marked with "IP Pairing". These are optional on SoCs which do not support +IP Pairing + +Required properties in pwrap device node. +- compatible: + "mediatek,mt8135-pwrap" for MT8135 SoCs + "mediatek,mt8173-pwrap" for MT8173 SoCs +- interrupts: IRQ for pwrap in SOC +- reg-names: Must include the following entries: + "pwrap": Main registers base + "pwrap-bridge": bridge base (IP Pairing) +- reg: Must contain an entry for each entry in reg-names. +- reset-names: Must include the following entries: + "pwrap" + "pwrap-bridge" (IP Pairing) +- resets: Must contain an entry for each entry in reset-names. +- clock-names: Must include the following entries: + "spi": SPI bus clock + "wrap": Main module clock +- clocks: Must contain an entry for each entry in clock-names. + +Optional properities: +- pmic: Mediatek PMIC MFD is the child device of pwrap + See the following for child node definitions: + Documentation/devicetree/bindings/mfd/mt6397.txt + +Example: + pwrap: pwrap@1000f000 { + compatible = "mediatek,mt8135-pwrap"; + reg = <0 0x1000f000 0 0x1000>, + <0 0x11017000 0 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = ; + resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, + <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "wrap"; + + pmic { + compatible = "mediatek,mt6397"; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt index 4ce24d425bf18a42daa14d529165f506e4e3f224..2f5ede39bea2d1d3cffacbcbe0ed103a7d2c708a 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt @@ -6,7 +6,8 @@ configuration settings. The mode setting will govern the input/output mode of the 4 GSBI IOs. Required properties: -- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064 +- compatible: Should contain "qcom,gsbi-v1.0.0" +- cell-index: Should contain the GSBI index - reg: Address range for GSBI registers - clocks: required clock - clock-names: must contain "iface" entry @@ -16,6 +17,8 @@ Required properties: Optional properties: - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values. +- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses + dma. Required properties if child node exists: - #address-cells: Must be 1 @@ -39,6 +42,7 @@ Example for APQ8064: gsbi4@16300000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; reg = <0x16300000 0x100>; clocks = <&gcc GSBI4_H_CLK>; clock-names = "iface"; @@ -48,22 +52,24 @@ Example for APQ8064: qcom,mode = ; qcom,crci = ; + syscon-tcsr = <&tcsr>; + /* child nodes go under here */ i2c_qup4: i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16380000 0x1000>; - interrupts = <0 153 0>; + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16380000 0x1000>; + interrupts = <0 153 0>; - clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; + clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; - clock-frequency = <200000>; + clock-frequency = <200000>; - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - }; + }; uart4: serial@16340000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; @@ -76,3 +82,7 @@ Example for APQ8064: }; }; + tcsr: syscon@1a400000 { + compatible = "qcom,apq8064-tcsr", "syscon"; + reg = <0x1a400000 0x100>; + }; diff --git a/Documentation/devicetree/bindings/sound/bcm2835-i2s.txt b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt similarity index 100% rename from Documentation/devicetree/bindings/sound/bcm2835-i2s.txt rename to Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt index 1ab6bc8404d5bc850dea1fc1533f451b03787e5f..f6a715e4ef43c1e0d7b5402188dbf310795e9caa 100644 --- a/Documentation/devicetree/bindings/sound/omap-twl4030.txt +++ b/Documentation/devicetree/bindings/sound/omap-twl4030.txt @@ -4,9 +4,9 @@ Required properties: - compatible: "ti,omap-twl4030" - ti,model: Name of the sound card (for example "omap3beagle") - ti,mcbsp: phandle for the McBSP node -- ti,codec: phandle for the twl4030 audio node Optional properties: +- ti,codec: phandle for the twl4030 audio node - ti,mcbsp-voice: phandle for the McBSP node connected to the voice port of twl - ti, jack-det-gpio: Jack detect GPIO - ti,audio-routing: List of connections between audio components. @@ -59,5 +59,4 @@ sound { ti,model = "omap3beagle"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt index 715d0998af8e2fbce29e16ea7cbc96e391aa6bf2..e16b9b5afc70a139087dea1ca3a64e9989525112 100644 --- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt +++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt @@ -1,6 +1,6 @@ Qualcomm SPMI Controller (PMIC Arbiter) -The SPMI PMIC Arbiter is found on the Snapdragon 800 Series. It is an SPMI +The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI controller with wrapping arbitration logic to allow for multiple on-chip devices to control a single SPMI master. @@ -19,6 +19,10 @@ Required properties: "core" - core registers "intr" - interrupt controller registers "cnfg" - configuration registers + Registers used only for V2 PMIC Arbiter: + "chnls" - tx-channel per virtual slave registers. + "obsrvr" - rx-channel (called observer) per virtual slave registers. + - reg : address + size pairs describing the PMIC arb register sets; order must correspond with the order of entries in reg-names - #address-cells : must be set to 2 diff --git a/Documentation/devicetree/bindings/arm/bcm/kona-timer.txt b/Documentation/devicetree/bindings/timer/brcm,kona-timer.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm/kona-timer.txt rename to Documentation/devicetree/bindings/timer/brcm,kona-timer.txt diff --git a/Documentation/devicetree/bindings/unittest.txt b/Documentation/devicetree/bindings/unittest.txt index 8933211f32f945c70b568d35372342ab3baca3d3..3bf58c20fe94da71ecae272e7d86256bd42f0683 100644 --- a/Documentation/devicetree/bindings/unittest.txt +++ b/Documentation/devicetree/bindings/unittest.txt @@ -1,60 +1,60 @@ -1) OF selftest platform device +1) OF unittest platform device -** selftest +** unittest Required properties: -- compatible: must be "selftest" +- compatible: must be "unittest" All other properties are optional. Example: - selftest { - compatible = "selftest"; + unittest { + compatible = "unittest"; status = "okay"; }; -2) OF selftest i2c adapter platform device +2) OF unittest i2c adapter platform device ** platform device unittest adapter Required properties: -- compatible: must be selftest-i2c-bus +- compatible: must be unittest-i2c-bus -Children nodes contain selftest i2c devices. +Children nodes contain unittest i2c devices. Example: - selftest-i2c-bus { - compatible = "selftest-i2c-bus"; + unittest-i2c-bus { + compatible = "unittest-i2c-bus"; status = "okay"; }; -3) OF selftest i2c device +3) OF unittest i2c device -** I2C selftest device +** I2C unittest device Required properties: -- compatible: must be selftest-i2c-dev +- compatible: must be unittest-i2c-dev All other properties are optional Example: - selftest-i2c-dev { - compatible = "selftest-i2c-dev"; + unittest-i2c-dev { + compatible = "unittest-i2c-dev"; status = "okay"; }; -4) OF selftest i2c mux device +4) OF unittest i2c mux device -** I2C selftest mux +** I2C unittest mux Required properties: -- compatible: must be selftest-i2c-mux +- compatible: must be unittest-i2c-mux -Children nodes contain selftest i2c bus nodes per channel. +Children nodes contain unittest i2c bus nodes per channel. Example: - selftest-i2c-mux { - compatible = "selftest-i2c-mux"; + unittest-i2c-mux { + compatible = "unittest-i2c-mux"; status = "okay"; #address-cells = <1>; #size-cells = <0>; @@ -64,7 +64,7 @@ Example: #size-cells = <0>; i2c-dev { reg = <8>; - compatible = "selftest-i2c-dev"; + compatible = "unittest-i2c-dev"; status = "okay"; }; }; diff --git a/Documentation/devicetree/bindings/mips/brcm/usb.txt b/Documentation/devicetree/bindings/usb/brcm,bcm3384-usb.txt similarity index 100% rename from Documentation/devicetree/bindings/mips/brcm/usb.txt rename to Documentation/devicetree/bindings/usb/brcm,bcm3384-usb.txt diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt index dc2a18f0b3a10a9e1bd5814fc429fe9246b82ec7..ddbe304beb212238e859640905b83886e5164ac7 100644 --- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt @@ -15,10 +15,8 @@ Optional properties: - phys: phandle + phy specifier pair - phy-names: must be "usb" - dmas: Must contain a list of references to DMA specifiers. - - dma-names : Must contain a list of DMA names: - - tx0 ... tx - - rx0 ... rx - - This means DnFIFO in USBHS module. + - dma-names : named "ch%d", where %d is the channel number ranging from zero + to the number of channels (DnFIFOs) minus one. Example: usbhs: usb@e6590000 { diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b13aa55b7a6f71fdc6d325426ca3ed5bfece7ad2..80339192c93e2626f81eed30fe97ff147c86d746 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -11,18 +11,22 @@ adapteva Adapteva, Inc. adh AD Holdings Plc. adi Analog Devices, Inc. aeroflexgaisler Aeroflex Gaisler AB +al Annapurna Labs allwinner Allwinner Technology Co., Ltd. alphascale AlphaScale Integrated Circuits Systems, Inc. altr Altera Corp. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amd Advanced Micro Devices (AMD), Inc. amlogic Amlogic, Inc. +ampire Ampire Co., Ltd. ams AMS AG amstaos AMS-Taos Inc. apm Applied Micro Circuits Corporation (APM) +aptina Aptina Imaging arasan Arasan Chip Systems arm ARM Ltd. armadeus ARMadeus Systems SARL +artesyn Artesyn Embedded Technologies Inc. asahi-kasei Asahi Kasei Corp. atmel Atmel Corporation auo AU Optronics Corporation @@ -81,6 +85,7 @@ globalscale Globalscale Technologies, Inc. gmt Global Mixed-mode Technology, Inc. goodix Shenzhen Huiding Technology Co., Ltd. google Google, Inc. +grinn Grinn gumstix Gumstix, Inc. gw Gateworks Corporation hannstar HannStar Display Corporation @@ -116,6 +121,7 @@ merrii Merrii Technology Co., Ltd. micrel Micrel Inc. microchip Microchip Technology Inc. micron Micron Technology Inc. +minix MINIX Technology Ltd. mitsubishi Mitsubishi Electric Corporation mosaixtech Mosaix Technologies, Inc. moxa Moxa @@ -135,6 +141,7 @@ nvidia NVIDIA nxp NXP Semiconductors onnn ON Semiconductor Corp. opencores OpenCores.org +ortustech Ortus Technology Co., Ltd. ovti OmniVision Technologies panasonic Panasonic Corporation parade Parade Technologies Inc. diff --git a/Documentation/devicetree/bindings/video/atmel,lcdc.txt b/Documentation/devicetree/bindings/video/atmel,lcdc.txt index f059dd0b3d286c3adc1e2b42571a2d48de4b641b..ecb8da063d07b82350060ff3ce8f3af9df35a549 100644 --- a/Documentation/devicetree/bindings/video/atmel,lcdc.txt +++ b/Documentation/devicetree/bindings/video/atmel,lcdc.txt @@ -10,7 +10,9 @@ Required properties: "atmel,at91sam9g45es-lcdc" , "atmel,at91sam9rl-lcdc" , "atmel,at32ap-lcdc" -- reg : Should contain 1 register ranges(address and length) +- reg : Should contain 1 register ranges(address and length). + Can contain an additional register range(address and length) + for fixed framebuffer memory. Useful for dedicated memories. - interrupts : framebuffer controller interrupt - display: a phandle pointing to the display node @@ -38,6 +40,14 @@ Example: }; +Example for fixed framebuffer memory: + + fb0: fb@0x00500000 { + compatible = "atmel,at91sam9263-lcdc"; + reg = <0x00700000 0x1000 0x70000000 0x200000>; + [...] + }; + Atmel LCDC Display ----------------------------------------------------- Required properties (as per of_videomode_helper): diff --git a/Documentation/devicetree/bindings/video/ti,omap-dss.txt b/Documentation/devicetree/bindings/video/ti,omap-dss.txt index d5f1a3fe31092bdceb7b09199157189e3d8eeb5b..e1ef29569338f32d0934f7d560eb881709e67a2e 100644 --- a/Documentation/devicetree/bindings/video/ti,omap-dss.txt +++ b/Documentation/devicetree/bindings/video/ti,omap-dss.txt @@ -25,8 +25,8 @@ Video Ports ----------- The DSS Core and the encoders have video port outputs. The structure of the -video ports is described in Documentation/devicetree/bindings/video/video- -ports.txt, and the properties for the ports and endpoints for each encoder are +video ports is described in Documentation/devicetree/bindings/graph.txt, +and the properties for the ports and endpoints for each encoder are described in the SoC's DSS binding documentation. The video ports are used to describe the connections to external hardware, like diff --git a/Documentation/devicetree/bindings/arm/bcm/kona-wdt.txt b/Documentation/devicetree/bindings/watchdog/brcm,kona-wdt.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm/kona-wdt.txt rename to Documentation/devicetree/bindings/watchdog/brcm,kona-wdt.txt diff --git a/Documentation/devicetree/of_selftest.txt b/Documentation/devicetree/of_unittest.txt similarity index 90% rename from Documentation/devicetree/of_selftest.txt rename to Documentation/devicetree/of_unittest.txt index 57a808b588bffb40162f4f4061fd323727ef5342..3e4e7d48ae93142bd5a1769ec3a9b4f2ffb0a926 100644 --- a/Documentation/devicetree/of_selftest.txt +++ b/Documentation/devicetree/of_unittest.txt @@ -1,11 +1,11 @@ -Open Firmware Device Tree Selftest +Open Firmware Device Tree Unittest ---------------------------------- Author: Gaurav Minocha 1. Introduction -This document explains how the test data required for executing OF selftest +This document explains how the test data required for executing OF unittest is attached to the live tree dynamically, independent of the machine's architecture. @@ -22,31 +22,31 @@ most of the device drivers in various use cases. 2. Test-data -The Device Tree Source file (drivers/of/testcase-data/testcases.dts) contains +The Device Tree Source file (drivers/of/unittest-data/testcases.dts) contains the test data required for executing the unit tests automated in -drivers/of/selftests.c. Currently, following Device Tree Source Include files -(.dtsi) are included in testcase.dts: +drivers/of/unittest.c. Currently, following Device Tree Source Include files +(.dtsi) are included in testcases.dts: -drivers/of/testcase-data/tests-interrupts.dtsi -drivers/of/testcase-data/tests-platform.dtsi -drivers/of/testcase-data/tests-phandle.dtsi -drivers/of/testcase-data/tests-match.dtsi +drivers/of/unittest-data/tests-interrupts.dtsi +drivers/of/unittest-data/tests-platform.dtsi +drivers/of/unittest-data/tests-phandle.dtsi +drivers/of/unittest-data/tests-match.dtsi When the kernel is build with OF_SELFTEST enabled, then the following make rule $(obj)/%.dtb: $(src)/%.dts FORCE $(call if_changed_dep, dtc) -is used to compile the DT source file (testcase.dts) into a binary blob -(testcase.dtb), also referred as flattened DT. +is used to compile the DT source file (testcases.dts) into a binary blob +(testcases.dtb), also referred as flattened DT. After that, using the following rule the binary blob above is wrapped as an -assembly file (testcase.dtb.S). +assembly file (testcases.dtb.S). $(obj)/%.dtb.S: $(obj)/%.dtb $(call cmd, dt_S_dtb) -The assembly file is compiled into an object file (testcase.dtb.o), and is +The assembly file is compiled into an object file (testcases.dtb.o), and is linked into the kernel image. @@ -98,7 +98,7 @@ child11 -> sibling12 -> sibling13 -> sibling14 -> null Figure 1: Generic structure of un-flattened device tree -Before executing OF selftest, it is required to attach the test data to +Before executing OF unittest, it is required to attach the test data to machine's device tree (if present). So, when selftest_data_add() is called, at first it reads the flattened device tree data linked into the kernel image via the following kernel symbols: diff --git a/Documentation/dma-buf-sharing.txt b/Documentation/dma-buf-sharing.txt index bb9753b635a3a5e8d8f794814a83584878b550e5..480c8de3c2c44786174e112795f61b2381d3b09f 100644 --- a/Documentation/dma-buf-sharing.txt +++ b/Documentation/dma-buf-sharing.txt @@ -49,25 +49,26 @@ The dma_buf buffer sharing API usage contains the following steps: The buffer exporter announces its wish to export a buffer. In this, it connects its own private buffer data, provides implementation for operations that can be performed on the exported dma_buf, and flags for the file - associated with this buffer. + associated with this buffer. All these fields are filled in struct + dma_buf_export_info, defined via the DEFINE_DMA_BUF_EXPORT_INFO macro. Interface: - struct dma_buf *dma_buf_export_named(void *priv, struct dma_buf_ops *ops, - size_t size, int flags, - const char *exp_name) + DEFINE_DMA_BUF_EXPORT_INFO(exp_info) + struct dma_buf *dma_buf_export(struct dma_buf_export_info *exp_info) - If this succeeds, dma_buf_export_named allocates a dma_buf structure, and + If this succeeds, dma_buf_export allocates a dma_buf structure, and returns a pointer to the same. It also associates an anonymous file with this buffer, so it can be exported. On failure to allocate the dma_buf object, it returns NULL. - 'exp_name' is the name of exporter - to facilitate information while - debugging. + 'exp_name' in struct dma_buf_export_info is the name of exporter - to + facilitate information while debugging. It is set to KBUILD_MODNAME by + default, so exporters don't have to provide a specific name, if they don't + wish to. + + DEFINE_DMA_BUF_EXPORT_INFO macro defines the struct dma_buf_export_info, + zeroes it out and pre-populates exp_name in it. - Exporting modules which do not wish to provide any specific name may use the - helper define 'dma_buf_export()', with the same arguments as above, but - without the last argument; a KBUILD_MODNAME pre-processor directive will be - inserted in place of 'exp_name' instead. 2. Userspace gets a handle to pass around to potential buffer-users diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt index e1e2bbd7a40404344adb1c46697cfb47dd47f9ee..831a5363f6be37756b0016c1c30fc0f46055aff8 100644 --- a/Documentation/driver-model/devres.txt +++ b/Documentation/driver-model/devres.txt @@ -276,6 +276,7 @@ IOMAP devm_ioport_unmap() devm_ioremap() devm_ioremap_nocache() + devm_ioremap_wc() devm_ioremap_resource() : checks resource, requests memory region, ioremaps devm_iounmap() pcim_iomap() diff --git a/Documentation/email-clients.txt b/Documentation/email-clients.txt index eede6088f978c25f83463b6d741d627b642fbfd8..c7d49b8855593b2a75e263363a9360e905f50773 100644 --- a/Documentation/email-clients.txt +++ b/Documentation/email-clients.txt @@ -211,7 +211,7 @@ Thunderbird (GUI) Thunderbird is an Outlook clone that likes to mangle text, but there are ways to coerce it into behaving. -- Allows use of an external editor: +- Allow use of an external editor: The easiest thing to do with Thunderbird and patches is to use an "external editor" extension and then just use your favorite $EDITOR for reading/merging patches into the body text. To do this, download @@ -219,6 +219,15 @@ to coerce it into behaving. View->Toolbars->Customize... and finally just click on it when in the Compose dialog. + Please note that "external editor" requires that your editor must not + fork, or in other words, the editor must not return before closing. + You may have to pass additional flags or change the settings of your + editor. Most notably if you are using gvim then you must pass the -f + option to gvim by putting "/usr/bin/gvim -f" (if the binary is in + /usr/bin) to the text editor field in "external editor" settings. If you + are using some other editor then please read its manual to find out how + to do this. + To beat some sense out of the internal editor, do this: - Edit your Thunderbird config settings so that it won't use format=flowed. diff --git a/Documentation/filesystems/f2fs.txt b/Documentation/filesystems/f2fs.txt index dac11d7fef2744adb2b9ae185f9665b10d761be4..e9e750e59efc50c922122d22ba1ec7ca69775a54 100644 --- a/Documentation/filesystems/f2fs.txt +++ b/Documentation/filesystems/f2fs.txt @@ -140,6 +140,12 @@ nobarrier This option can be used if underlying storage guarantees fastboot This option is used when a system wants to reduce mount time as much as possible, even though normal performance can be sacrificed. +extent_cache Enable an extent cache based on rb-tree, it can cache + as many as extent which map between contiguous logical + address and physical address per inode, resulting in + increasing the cache hit ratio. +noinline_data Disable the inline data feature, inline data feature is + enabled by default. ================================================================================ DEBUGFS ENTRIES diff --git a/Documentation/filesystems/nfs/nfs-rdma.txt b/Documentation/filesystems/nfs/nfs-rdma.txt index 724043858b0834f874aff57df4155f1da3dffad8..95c13aa575ff32eebeb4938f435376ca0595a439 100644 --- a/Documentation/filesystems/nfs/nfs-rdma.txt +++ b/Documentation/filesystems/nfs/nfs-rdma.txt @@ -187,8 +187,10 @@ Check RDMA and NFS Setup To further test the InfiniBand software stack, use IPoIB (this assumes you have two IB hosts named host1 and host2): - host1$ ifconfig ib0 a.b.c.x - host2$ ifconfig ib0 a.b.c.y + host1$ ip link set dev ib0 up + host1$ ip address add dev ib0 a.b.c.x + host2$ ip link set dev ib0 up + host2$ ip address add dev ib0 a.b.c.y host1$ ping a.b.c.y host2$ ping a.b.c.x @@ -229,7 +231,8 @@ NFS/RDMA Setup $ modprobe ib_mthca $ modprobe ib_ipoib - $ ifconfig ib0 a.b.c.d + $ ip li set dev ib0 up + $ ip addr add dev ib0 a.b.c.d NOTE: use unique addresses for the client and server diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt index 8e36c7e3c3455b3dd78463e6e722b5f5946dabdb..c3b6b301d8b004778c990e315b6d37250d673223 100644 --- a/Documentation/filesystems/proc.txt +++ b/Documentation/filesystems/proc.txt @@ -1260,9 +1260,9 @@ Various pieces of information about kernel activity are available in the since the system first booted. For a quick look, simply cat the file: > cat /proc/stat - cpu 2255 34 2290 22625563 6290 127 456 0 0 - cpu0 1132 34 1441 11311718 3675 127 438 0 0 - cpu1 1123 0 849 11313845 2614 0 18 0 0 + cpu 2255 34 2290 22625563 6290 127 456 0 0 0 + cpu0 1132 34 1441 11311718 3675 127 438 0 0 0 + cpu1 1123 0 849 11313845 2614 0 18 0 0 0 intr 114930548 113199788 3 0 5 263 0 4 [... lots more numbers ...] ctxt 1990473 btime 1062191376 diff --git a/Documentation/filesystems/xfs.txt b/Documentation/filesystems/xfs.txt index 0bfafe10835772be298d5a3859a1ee31de861f83..5a5a05582b583c42468764fc5a80bf8c126072e6 100644 --- a/Documentation/filesystems/xfs.txt +++ b/Documentation/filesystems/xfs.txt @@ -228,30 +228,19 @@ default behaviour. Deprecated Mount Options ======================== - delaylog/nodelaylog - Delayed logging is the only logging method that XFS supports - now, so these mount options are now ignored. - - Due for removal in 3.12. - - ihashsize=value - In memory inode hashes have been removed, so this option has - no function as of August 2007. Option is deprecated. - - Due for removal in 3.12. +None at present. - irixsgid - This behaviour is now controlled by a sysctl, so the mount - option is ignored. - Due for removal in 3.12. +Removed Mount Options +===================== - osyncisdsync - osyncisosync - O_SYNC and O_DSYNC are fully supported, so there is no need - for these options any more. + Name Removed + ---- ------- + delaylog/nodelaylog v3.20 + ihashsize v3.20 + irixsgid v3.20 + osyncisdsync/osyncisosync v3.20 - Due for removal in 3.12. sysctls ======= diff --git a/Documentation/gpio/board.txt b/Documentation/gpio/board.txt index 8b35f51fe7b6a3e8d11a2abc3104913794349cce..b80606de545ad809fb147688060b26b51af4d5e1 100644 --- a/Documentation/gpio/board.txt +++ b/Documentation/gpio/board.txt @@ -50,10 +50,43 @@ gpiod_is_active_low(power) will be true). ACPI ---- -ACPI does not support function names for GPIOs. Therefore, only the "idx" -argument of gpiod_get_index() is useful to discriminate between GPIOs assigned -to a device. The "con_id" argument can still be set for debugging purposes (it -will appear under error messages as well as debug and sysfs nodes). +ACPI also supports function names for GPIOs in a similar fashion to DT. +The above DT example can be converted to an equivalent ACPI description +with the help of _DSD (Device Specific Data), introduced in ACPI 5.1: + + Device (FOO) { + Name (_CRS, ResourceTemplate () { + GpioIo (Exclusive, ..., IoRestrictionOutputOnly, + "\\_SB.GPI0") {15} // red + GpioIo (Exclusive, ..., IoRestrictionOutputOnly, + "\\_SB.GPI0") {16} // green + GpioIo (Exclusive, ..., IoRestrictionOutputOnly, + "\\_SB.GPI0") {17} // blue + GpioIo (Exclusive, ..., IoRestrictionOutputOnly, + "\\_SB.GPI0") {1} // power + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { + "led-gpios", + Package () { + ^FOO, 0, 0, 1, + ^FOO, 1, 0, 1, + ^FOO, 2, 0, 1, + } + }, + Package () { + "power-gpios", + Package () {^FOO, 3, 0, 0}, + }, + } + }) + } + +For more information about the ACPI GPIO bindings see +Documentation/acpi/gpio-properties.txt. Platform Data ------------- diff --git a/Documentation/gpio/consumer.txt b/Documentation/gpio/consumer.txt index d85fbae451ea930ddd9729dda3b55c44e443814b..c21c1313f09e55bee448fbb62d5efcd93eabe848 100644 --- a/Documentation/gpio/consumer.txt +++ b/Documentation/gpio/consumer.txt @@ -58,7 +58,6 @@ pattern where a GPIO is optional, the gpiod_get_optional() and gpiod_get_index_optional() functions can be used. These functions return NULL instead of -ENOENT if no GPIO has been assigned to the requested function: - struct gpio_desc *gpiod_get_optional(struct device *dev, const char *con_id, enum gpiod_flags flags) @@ -68,6 +67,27 @@ instead of -ENOENT if no GPIO has been assigned to the requested function: unsigned int index, enum gpiod_flags flags) +For a function using multiple GPIOs all of those can be obtained with one call: + + struct gpio_descs *gpiod_get_array(struct device *dev, + const char *con_id, + enum gpiod_flags flags) + +This function returns a struct gpio_descs which contains an array of +descriptors: + + struct gpio_descs { + unsigned int ndescs; + struct gpio_desc *desc[]; + } + +The following function returns NULL instead of -ENOENT if no GPIOs have been +assigned to the requested function: + + struct gpio_descs *gpiod_get_array_optional(struct device *dev, + const char *con_id, + enum gpiod_flags flags) + Device-managed variants of these functions are also defined: struct gpio_desc *devm_gpiod_get(struct device *dev, const char *con_id, @@ -82,20 +102,37 @@ Device-managed variants of these functions are also defined: const char *con_id, enum gpiod_flags flags) - struct gpio_desc * devm_gpiod_get_index_optional(struct device *dev, + struct gpio_desc *devm_gpiod_get_index_optional(struct device *dev, const char *con_id, unsigned int index, enum gpiod_flags flags) + struct gpio_descs *devm_gpiod_get_array(struct device *dev, + const char *con_id, + enum gpiod_flags flags) + + struct gpio_descs *devm_gpiod_get_array_optional(struct device *dev, + const char *con_id, + enum gpiod_flags flags) + A GPIO descriptor can be disposed of using the gpiod_put() function: void gpiod_put(struct gpio_desc *desc) -It is strictly forbidden to use a descriptor after calling this function. The -device-managed variant is, unsurprisingly: +For an array of GPIOs this function can be used: + + void gpiod_put_array(struct gpio_descs *descs) + +It is strictly forbidden to use a descriptor after calling these functions. +It is also not allowed to individually release descriptors (using gpiod_put()) +from an array acquired with gpiod_get_array(). + +The device-managed variants are, unsurprisingly: void devm_gpiod_put(struct device *dev, struct gpio_desc *desc) + void devm_gpiod_put_array(struct device *dev, struct gpio_descs *descs) + Using GPIOs =========== @@ -222,6 +259,26 @@ GPIOs belonging to the same bank or chip simultaneously if supported by the corresponding chip driver. In that case a significantly improved performance can be expected. If simultaneous setting is not possible the GPIOs will be set sequentially. + +The gpiod_set_array() functions take three arguments: + * array_size - the number of array elements + * desc_array - an array of GPIO descriptors + * value_array - an array of values to assign to the GPIOs + +The descriptor array can be obtained using the gpiod_get_array() function +or one of its variants. If the group of descriptors returned by that function +matches the desired group of GPIOs, those GPIOs can be set by simply using +the struct gpio_descs returned by gpiod_get_array(): + + struct gpio_descs *my_gpio_descs = gpiod_get_array(...); + gpiod_set_array(my_gpio_descs->ndescs, my_gpio_descs->desc, + my_gpio_values); + +It is also possible to set a completely arbitrary array of descriptors. The +descriptors may be obtained using any combination of gpiod_get() and +gpiod_get_array(). Afterwards the array of descriptors has to be setup +manually before it can be used with gpiod_set_array(). + Note that for optimal performance GPIOs belonging to the same chip should be contiguous within the array of descriptors. diff --git a/Documentation/hwmon/tmp401 b/Documentation/hwmon/tmp401 index 8eb88e974055f62f2c9226bcd6d98b3e8e5ea908..711f75e189eba003e31a3f762fa16be04d1012d0 100644 --- a/Documentation/hwmon/tmp401 +++ b/Documentation/hwmon/tmp401 @@ -20,7 +20,7 @@ Supported chips: Datasheet: http://focus.ti.com/docs/prod/folders/print/tmp432.html * Texas Instruments TMP435 Prefix: 'tmp435' - Addresses scanned: I2C 0x37, 0x48 - 0x4f + Addresses scanned: I2C 0x48 - 0x4f Datasheet: http://focus.ti.com/docs/prod/folders/print/tmp435.html Authors: diff --git a/Documentation/i2o/README b/Documentation/i2o/README deleted file mode 100644 index ee91e2626ff072e817a0f91e05d01e439c943f0a..0000000000000000000000000000000000000000 --- a/Documentation/i2o/README +++ /dev/null @@ -1,63 +0,0 @@ - - Linux I2O Support (c) Copyright 1999 Red Hat Software - and others. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License - as published by the Free Software Foundation; either version - 2 of the License, or (at your option) any later version. - -AUTHORS (so far) - -Alan Cox, Building Number Three Ltd. - Core code, SCSI and Block OSMs - -Steve Ralston, LSI Logic Corp. - Debugging SCSI and Block OSM - -Deepak Saxena, Intel Corp. - Various core/block extensions - /proc interface, bug fixes - Ioctl interfaces for control - Debugging LAN OSM - -Philip Rumpf - Fixed assorted dumb SMP locking bugs - -Juha Sievanen, University of Helsinki Finland - LAN OSM code - /proc interface to LAN class - Bug fixes - Core code extensions - -Auvo Häkkinen, University of Helsinki Finland - LAN OSM code - /Proc interface to LAN class - Bug fixes - Core code extensions - -Taneli Vähäkangas, University of Helsinki Finland - Fixes to i2o_config - -CREDITS - - This work was made possible by - -Red Hat Software - Funding for the Building #3 part of the project - -Symbios Logic (Now LSI) - Host adapters, hints, known to work platforms when I hit - compatibility problems - -BoxHill Corporation - Loan of initial FibreChannel disk array used for development work. - -European Commission - Funding the work done by the University of Helsinki - -SysKonnect - Loan of FDDI and Gigabit Ethernet cards - -ASUSTeK - Loan of I2O motherboard diff --git a/Documentation/i2o/ioctl b/Documentation/i2o/ioctl deleted file mode 100644 index 27c3c5493116ada2eebf9fcd2480aea55072c5e4..0000000000000000000000000000000000000000 --- a/Documentation/i2o/ioctl +++ /dev/null @@ -1,394 +0,0 @@ - -Linux I2O User Space Interface -rev 0.3 - 04/20/99 - -============================================================================= -Originally written by Deepak Saxena(deepak@plexity.net) -Currently maintained by Deepak Saxena(deepak@plexity.net) -============================================================================= - -I. Introduction - -The Linux I2O subsystem provides a set of ioctl() commands that can be -utilized by user space applications to communicate with IOPs and devices -on individual IOPs. This document defines the specific ioctl() commands -that are available to the user and provides examples of their uses. - -This document assumes the reader is familiar with or has access to the -I2O specification as no I2O message parameters are outlined. For information -on the specification, see http://www.i2osig.org - -This document and the I2O user space interface are currently maintained -by Deepak Saxena. Please send all comments, errata, and bug fixes to -deepak@csociety.purdue.edu - -II. IOP Access - -Access to the I2O subsystem is provided through the device file named -/dev/i2o/ctl. This file is a character file with major number 10 and minor -number 166. It can be created through the following command: - - mknod /dev/i2o/ctl c 10 166 - -III. Determining the IOP Count - - SYNOPSIS - - ioctl(fd, I2OGETIOPS, int *count); - - u8 count[MAX_I2O_CONTROLLERS]; - - DESCRIPTION - - This function returns the system's active IOP table. count should - point to a buffer containing MAX_I2O_CONTROLLERS entries. Upon - returning, each entry will contain a non-zero value if the given - IOP unit is active, and NULL if it is inactive or non-existent. - - RETURN VALUE. - - Returns 0 if no errors occur, and -1 otherwise. If an error occurs, - errno is set appropriately: - - EFAULT Invalid user space pointer was passed - -IV. Getting Hardware Resource Table - - SYNOPSIS - - ioctl(fd, I2OHRTGET, struct i2o_cmd_hrt *hrt); - - struct i2o_cmd_hrtlct - { - u32 iop; /* IOP unit number */ - void *resbuf; /* Buffer for result */ - u32 *reslen; /* Buffer length in bytes */ - }; - - DESCRIPTION - - This function returns the Hardware Resource Table of the IOP specified - by hrt->iop in the buffer pointed to by hrt->resbuf. The actual size of - the data is written into *(hrt->reslen). - - RETURNS - - This function returns 0 if no errors occur. If an error occurs, -1 - is returned and errno is set appropriately: - - EFAULT Invalid user space pointer was passed - ENXIO Invalid IOP number - ENOBUFS Buffer not large enough. If this occurs, the required - buffer length is written into *(hrt->reslen) - -V. Getting Logical Configuration Table - - SYNOPSIS - - ioctl(fd, I2OLCTGET, struct i2o_cmd_lct *lct); - - struct i2o_cmd_hrtlct - { - u32 iop; /* IOP unit number */ - void *resbuf; /* Buffer for result */ - u32 *reslen; /* Buffer length in bytes */ - }; - - DESCRIPTION - - This function returns the Logical Configuration Table of the IOP specified - by lct->iop in the buffer pointed to by lct->resbuf. The actual size of - the data is written into *(lct->reslen). - - RETURNS - - This function returns 0 if no errors occur. If an error occurs, -1 - is returned and errno is set appropriately: - - EFAULT Invalid user space pointer was passed - ENXIO Invalid IOP number - ENOBUFS Buffer not large enough. If this occurs, the required - buffer length is written into *(lct->reslen) - -VI. Setting Parameters - - SYNOPSIS - - ioctl(fd, I2OPARMSET, struct i2o_parm_setget *ops); - - struct i2o_cmd_psetget - { - u32 iop; /* IOP unit number */ - u32 tid; /* Target device TID */ - void *opbuf; /* Operation List buffer */ - u32 oplen; /* Operation List buffer length in bytes */ - void *resbuf; /* Result List buffer */ - u32 *reslen; /* Result List buffer length in bytes */ - }; - - DESCRIPTION - - This function posts a UtilParamsSet message to the device identified - by ops->iop and ops->tid. The operation list for the message is - sent through the ops->opbuf buffer, and the result list is written - into the buffer pointed to by ops->resbuf. The number of bytes - written is placed into *(ops->reslen). - - RETURNS - - The return value is the size in bytes of the data written into - ops->resbuf if no errors occur. If an error occurs, -1 is returned - and errno is set appropriately: - - EFAULT Invalid user space pointer was passed - ENXIO Invalid IOP number - ENOBUFS Buffer not large enough. If this occurs, the required - buffer length is written into *(ops->reslen) - ETIMEDOUT Timeout waiting for reply message - ENOMEM Kernel memory allocation error - - A return value of 0 does not mean that the value was actually - changed properly on the IOP. The user should check the result - list to determine the specific status of the transaction. - -VII. Getting Parameters - - SYNOPSIS - - ioctl(fd, I2OPARMGET, struct i2o_parm_setget *ops); - - struct i2o_parm_setget - { - u32 iop; /* IOP unit number */ - u32 tid; /* Target device TID */ - void *opbuf; /* Operation List buffer */ - u32 oplen; /* Operation List buffer length in bytes */ - void *resbuf; /* Result List buffer */ - u32 *reslen; /* Result List buffer length in bytes */ - }; - - DESCRIPTION - - This function posts a UtilParamsGet message to the device identified - by ops->iop and ops->tid. The operation list for the message is - sent through the ops->opbuf buffer, and the result list is written - into the buffer pointed to by ops->resbuf. The actual size of data - written is placed into *(ops->reslen). - - RETURNS - - EFAULT Invalid user space pointer was passed - ENXIO Invalid IOP number - ENOBUFS Buffer not large enough. If this occurs, the required - buffer length is written into *(ops->reslen) - ETIMEDOUT Timeout waiting for reply message - ENOMEM Kernel memory allocation error - - A return value of 0 does not mean that the value was actually - properly retrieved. The user should check the result list - to determine the specific status of the transaction. - -VIII. Downloading Software - - SYNOPSIS - - ioctl(fd, I2OSWDL, struct i2o_sw_xfer *sw); - - struct i2o_sw_xfer - { - u32 iop; /* IOP unit number */ - u8 flags; /* DownloadFlags field */ - u8 sw_type; /* Software type */ - u32 sw_id; /* Software ID */ - void *buf; /* Pointer to software buffer */ - u32 *swlen; /* Length of software buffer */ - u32 *maxfrag; /* Number of fragments */ - u32 *curfrag; /* Current fragment number */ - }; - - DESCRIPTION - - This function downloads a software fragment pointed by sw->buf - to the iop identified by sw->iop. The DownloadFlags, SwID, SwType - and SwSize fields of the ExecSwDownload message are filled in with - the values of sw->flags, sw->sw_id, sw->sw_type and *(sw->swlen). - - The fragments _must_ be sent in order and be 8K in size. The last - fragment _may_ be shorter, however. The kernel will compute its - size based on information in the sw->swlen field. - - Please note that SW transfers can take a long time. - - RETURNS - - This function returns 0 no errors occur. If an error occurs, -1 - is returned and errno is set appropriately: - - EFAULT Invalid user space pointer was passed - ENXIO Invalid IOP number - ETIMEDOUT Timeout waiting for reply message - ENOMEM Kernel memory allocation error - -IX. Uploading Software - - SYNOPSIS - - ioctl(fd, I2OSWUL, struct i2o_sw_xfer *sw); - - struct i2o_sw_xfer - { - u32 iop; /* IOP unit number */ - u8 flags; /* UploadFlags */ - u8 sw_type; /* Software type */ - u32 sw_id; /* Software ID */ - void *buf; /* Pointer to software buffer */ - u32 *swlen; /* Length of software buffer */ - u32 *maxfrag; /* Number of fragments */ - u32 *curfrag; /* Current fragment number */ - }; - - DESCRIPTION - - This function uploads a software fragment from the IOP identified - by sw->iop, sw->sw_type, sw->sw_id and optionally sw->swlen fields. - The UploadFlags, SwID, SwType and SwSize fields of the ExecSwUpload - message are filled in with the values of sw->flags, sw->sw_id, - sw->sw_type and *(sw->swlen). - - The fragments _must_ be requested in order and be 8K in size. The - user is responsible for allocating memory pointed by sw->buf. The - last fragment _may_ be shorter. - - Please note that SW transfers can take a long time. - - RETURNS - - This function returns 0 if no errors occur. If an error occurs, -1 - is returned and errno is set appropriately: - - EFAULT Invalid user space pointer was passed - ENXIO Invalid IOP number - ETIMEDOUT Timeout waiting for reply message - ENOMEM Kernel memory allocation error - -X. Removing Software - - SYNOPSIS - - ioctl(fd, I2OSWDEL, struct i2o_sw_xfer *sw); - - struct i2o_sw_xfer - { - u32 iop; /* IOP unit number */ - u8 flags; /* RemoveFlags */ - u8 sw_type; /* Software type */ - u32 sw_id; /* Software ID */ - void *buf; /* Unused */ - u32 *swlen; /* Length of the software data */ - u32 *maxfrag; /* Unused */ - u32 *curfrag; /* Unused */ - }; - - DESCRIPTION - - This function removes software from the IOP identified by sw->iop. - The RemoveFlags, SwID, SwType and SwSize fields of the ExecSwRemove message - are filled in with the values of sw->flags, sw->sw_id, sw->sw_type and - *(sw->swlen). Give zero in *(sw->len) if the value is unknown. IOP uses - *(sw->swlen) value to verify correct identication of the module to remove. - The actual size of the module is written into *(sw->swlen). - - RETURNS - - This function returns 0 if no errors occur. If an error occurs, -1 - is returned and errno is set appropriately: - - EFAULT Invalid user space pointer was passed - ENXIO Invalid IOP number - ETIMEDOUT Timeout waiting for reply message - ENOMEM Kernel memory allocation error - -X. Validating Configuration - - SYNOPSIS - - ioctl(fd, I2OVALIDATE, int *iop); - u32 iop; - - DESCRIPTION - - This function posts an ExecConfigValidate message to the controller - identified by iop. This message indicates that the current - configuration is accepted. The iop changes the status of suspect drivers - to valid and may delete old drivers from its store. - - RETURNS - - This function returns 0 if no erro occur. If an error occurs, -1 is - returned and errno is set appropriately: - - ETIMEDOUT Timeout waiting for reply message - ENXIO Invalid IOP number - -XI. Configuration Dialog - - SYNOPSIS - - ioctl(fd, I2OHTML, struct i2o_html *htquery); - struct i2o_html - { - u32 iop; /* IOP unit number */ - u32 tid; /* Target device ID */ - u32 page; /* HTML page */ - void *resbuf; /* Buffer for reply HTML page */ - u32 *reslen; /* Length in bytes of reply buffer */ - void *qbuf; /* Pointer to HTTP query string */ - u32 qlen; /* Length in bytes of query string buffer */ - }; - - DESCRIPTION - - This function posts an UtilConfigDialog message to the device identified - by htquery->iop and htquery->tid. The requested HTML page number is - provided by the htquery->page field, and the resultant data is stored - in the buffer pointed to by htquery->resbuf. If there is an HTTP query - string that is to be sent to the device, it should be sent in the buffer - pointed to by htquery->qbuf. If there is no query string, this field - should be set to NULL. The actual size of the reply received is written - into *(htquery->reslen). - - RETURNS - - This function returns 0 if no error occur. If an error occurs, -1 - is returned and errno is set appropriately: - - EFAULT Invalid user space pointer was passed - ENXIO Invalid IOP number - ENOBUFS Buffer not large enough. If this occurs, the required - buffer length is written into *(ops->reslen) - ETIMEDOUT Timeout waiting for reply message - ENOMEM Kernel memory allocation error - -XII. Events - - In the process of determining this. Current idea is to have use - the select() interface to allow user apps to periodically poll - the /dev/i2o/ctl device for events. When select() notifies the user - that an event is available, the user would call read() to retrieve - a list of all the events that are pending for the specific device. - -============================================================================= -Revision History -============================================================================= - -Rev 0.1 - 04/01/99 -- Initial revision - -Rev 0.2 - 04/06/99 -- Changed return values to match UNIX ioctl() standard. Only return values - are 0 and -1. All errors are reported through errno. -- Added summary of proposed possible event interfaces - -Rev 0.3 - 04/20/99 -- Changed all ioctls() to use pointers to user data instead of actual data -- Updated error values to match the code diff --git a/Documentation/input/alps.txt b/Documentation/input/alps.txt index 92ae734c00c348ab810373e0dc838a92462c932f..c86f2f1ae4f6aa2d9af3e3987e8be06fd237dbef 100644 --- a/Documentation/input/alps.txt +++ b/Documentation/input/alps.txt @@ -58,7 +58,7 @@ To exit command mode, PSMOUSE_CMD_SETSTREAM (EA) is sent to the touchpad. While in command mode, register addresses can be set by first sending a specific command, either EC for v3 devices or F5 for v4 devices. Then the address is sent one nibble at a time, where each nibble is encoded as a -command with optional data. This enoding differs slightly between the v3 and +command with optional data. This encoding differs slightly between the v3 and v4 protocols. Once an address has been set, the addressed register can be read by sending @@ -94,6 +94,10 @@ PS/2 packet format Note that the device never signals overflow condition. +For protocol version 2 devices when the trackpoint is used, and no fingers +are on the touchpad, the M R L bits signal the combined status of both the +pointingstick and touchpad buttons. + ALPS Absolute Mode - Protocol Version 1 -------------------------------------- @@ -107,7 +111,7 @@ ALPS Absolute Mode - Protocol Version 1 ALPS Absolute Mode - Protocol Version 2 --------------------------------------- - byte 0: 1 ? ? ? 1 ? ? ? + byte 0: 1 ? ? ? 1 PSM PSR PSL byte 1: 0 x6 x5 x4 x3 x2 x1 x0 byte 2: 0 x10 x9 x8 x7 ? fin ges byte 3: 0 y9 y8 y7 1 M R L @@ -115,7 +119,8 @@ ALPS Absolute Mode - Protocol Version 2 byte 5: 0 z6 z5 z4 z3 z2 z1 z0 Protocol Version 2 DualPoint devices send standard PS/2 mouse packets for -the DualPoint Stick. +the DualPoint Stick. For non interleaved dualpoint devices the pointingstick +buttons get reported separately in the PSM, PSR and PSL bits. Dualpoint device -- interleaved packet format --------------------------------------------- @@ -139,7 +144,7 @@ ALPS Absolute Mode - Protocol Version 3 --------------------------------------- ALPS protocol version 3 has three different packet formats. The first two are -associated with touchpad events, and the third is associatd with trackstick +associated with touchpad events, and the third is associated with trackstick events. The first type is the touchpad position packet. diff --git a/Documentation/input/event-codes.txt b/Documentation/input/event-codes.txt index 96705616f5820a6d48d6cfda497c7fcf30917e2a..3f0f5ce3338b63a8153410c9b08edba739989e22 100644 --- a/Documentation/input/event-codes.txt +++ b/Documentation/input/event-codes.txt @@ -229,7 +229,7 @@ such device to feedback. EV_PWR: ---------- EV_PWR events are a special type of event used specifically for power -mangement. Its usage is not well defined. To be addressed later. +management. Its usage is not well defined. To be addressed later. Device properties: ================= diff --git a/Documentation/input/gpio-tilt.txt b/Documentation/input/gpio-tilt.txt index 06d60c3ff5e732d22cea71f599298db6432deca4..2cdfd9bcb1afc1015b4f98201f6b38cdab1691b3 100644 --- a/Documentation/input/gpio-tilt.txt +++ b/Documentation/input/gpio-tilt.txt @@ -28,7 +28,7 @@ Example: -------- Example configuration for a single TS1003 tilt switch that rotates around -one axis in 4 steps and emitts the current tilt via two GPIOs. +one axis in 4 steps and emits the current tilt via two GPIOs. static int sg060_tilt_enable(struct device *dev) { /* code to enable the sensors */ diff --git a/Documentation/input/iforce-protocol.txt b/Documentation/input/iforce-protocol.txt index 2d5fbfd6023e8dffda80793e02c58b3f658bab0b..66287151c54a99fd76cab71888ac2b720f4c489b 100644 --- a/Documentation/input/iforce-protocol.txt +++ b/Documentation/input/iforce-protocol.txt @@ -97,7 +97,7 @@ LEN= 0e *** Attack and fade *** OP= 02 LEN= 08 -00-01 Address where to store the parameteres +00-01 Address where to store the parameters 02-03 Duration of attack (little endian encoding, in ms) 04 Level at end of attack. Signed byte. 05-06 Duration of fade. diff --git a/Documentation/input/walkera0701.txt b/Documentation/input/walkera0701.txt index 561385d38482100d9c0a917b8647598aefd9f810..49e3ac60dcef57d045720f5d9f96fc2b522a0f62 100644 --- a/Documentation/input/walkera0701.txt +++ b/Documentation/input/walkera0701.txt @@ -91,7 +91,7 @@ absolute binary value. (10 bits per channel). Next nibble is checksum for first ten nibbles. Next nibbles 12 .. 21 represents four channels (not all channels can be -directly controlled from TX). Binary representations ar the same as in first +directly controlled from TX). Binary representations are the same as in first four channels. In nibbles 22 and 23 is a special magic number. Nibble 24 is checksum for nibbles 12..23. diff --git a/Documentation/input/yealink.txt b/Documentation/input/yealink.txt index 5360e434486ced9970c6c71454b085b3ff617061..8277b76ec50649f3a35f5f5407d135fc37312a0e 100644 --- a/Documentation/input/yealink.txt +++ b/Documentation/input/yealink.txt @@ -93,7 +93,7 @@ Format description: Format specifier '8' : Generic 7 segment digit with individual addressable segments - Reduced capability 7 segm digit, when segments are hard wired together. + Reduced capability 7 segment digit, when segments are hard wired together. '1' : 2 segments digit only able to produce a 1. 'e' : Most significant day of the month digit, able to produce at least 1 2 3. diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt index 8136e1fd30fdede7141d70bc00f5c6b8097ed981..51f4221657bff5b03c9a8ef44116d6e27ef27423 100644 --- a/Documentation/ioctl/ioctl-number.txt +++ b/Documentation/ioctl/ioctl-number.txt @@ -321,6 +321,7 @@ Code Seq#(hex) Include File Comments 0xDB 00-0F drivers/char/mwave/mwavepub.h 0xDD 00-3F ZFCP device driver see drivers/s390/scsi/ +0xEC 00-01 drivers/platform/chrome/cros_ec_dev.h ChromeOS EC driver 0xF3 00-3F drivers/usb/misc/sisusbvga/sisusb.h sisfb (in development) 0xF4 00-1F video/mbxfb.h mbxfb diff --git a/Documentation/kasan.txt b/Documentation/kasan.txt index 092fc10961fede482be1f7983e72db0e6c8ec3a8..4692241789b1f608ebc2535ddef1a07722a3fb19 100644 --- a/Documentation/kasan.txt +++ b/Documentation/kasan.txt @@ -9,7 +9,9 @@ a fast and comprehensive solution for finding use-after-free and out-of-bounds bugs. KASan uses compile-time instrumentation for checking every memory access, -therefore you will need a certain version of GCC > 4.9.2 +therefore you will need a gcc version of 4.9.2 or later. KASan could detect out +of bounds accesses to stack or global variables, but only if gcc 5.0 or later was +used to built the kernel. Currently KASan is supported only for x86_64 architecture and requires that the kernel be built with the SLUB allocator. @@ -23,8 +25,8 @@ To enable KASAN configure kernel with: and choose between CONFIG_KASAN_OUTLINE and CONFIG_KASAN_INLINE. Outline/inline is compiler instrumentation types. The former produces smaller binary the -latter is 1.1 - 2 times faster. Inline instrumentation requires GCC 5.0 or -latter. +latter is 1.1 - 2 times faster. Inline instrumentation requires a gcc version +of 5.0 or later. Currently KASAN works only with the SLUB memory allocator. For better bug detection and nicer report, enable CONFIG_STACKTRACE and put diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 11a76df2e1f1ee837abb694b482def0e3467530e..61ab1628a057cc2c4d8b11d892d834f7e5f7773a 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -165,7 +165,7 @@ multipliers 'Kilo', 'Mega', and 'Giga', equalling 2^10, 2^20, and 2^30 bytes respectively. Such letter suffixes can also be entirely omitted. - acpi= [HW,ACPI,X86] + acpi= [HW,ACPI,X86,ARM64] Advanced Configuration and Power Interface Format: { force | off | strict | noirq | rsdt } force -- enable ACPI if default was off @@ -175,6 +175,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. strictly ACPI specification compliant. rsdt -- prefer RSDT over (default) XSDT copy_dsdt -- copy DSDT to memory + For ARM64, ONLY "acpi=off" or "acpi=force" are available See also Documentation/power/runtime_pm.txt, pci=noacpi @@ -713,10 +714,18 @@ bytes respectively. Such letter suffixes can also be entirely omitted. uart[8250],io,[,options] uart[8250],mmio,[,options] + uart[8250],mmio32,[,options] + uart[8250],0x[,options] Start an early, polled-mode console on the 8250/16550 UART at the specified I/O port or MMIO address, - switching to the matching ttyS device later. The - options are the same as for ttyS, above. + switching to the matching ttyS device later. + MMIO inter-register address stride is either 8-bit + (mmio) or 32-bit (mmio32). + If none of [io|mmio|mmio32], is assumed to be + equivalent to 'mmio'. 'options' are specified in the + same format described for ttyS above; if unspecified, + the h/w is not re-initialized. + hvc Use the hypervisor console device . This is for both Xen and PowerPC hypervisors. @@ -928,6 +937,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. Enable debug messages at boot time. See Documentation/dynamic-debug-howto.txt for details. + eagerfpu= [X86] + on enable eager fpu restore + off disable eager fpu restore + auto selects the default scheme, which automatically + enables eagerfpu restore for xsaveopt. + early_ioremap_debug [KNL] Enable debug messages in early_ioremap support. This is useful for tracking down temporary early mappings @@ -944,11 +959,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted. uart[8250],io,[,options] uart[8250],mmio,[,options] uart[8250],mmio32,[,options] + uart[8250],0x[,options] Start an early, polled-mode console on the 8250/16550 UART at the specified I/O port or MMIO address. MMIO inter-register address stride is either 8-bit (mmio) or 32-bit (mmio32). - The options are the same as for ttyS, above. + If none of [io|mmio|mmio32], is assumed to be + equivalent to 'mmio'. 'options' are specified in the + same format described for "console=ttyS"; if + unspecified, the h/w is not initialized. pl011, Start an early, polled-mode console on a pl011 serial @@ -1966,6 +1985,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. or memmap=0x10000$0x18690000 + memmap=nn[KMG]!ss[KMG] + [KNL,X86] Mark specific memory as protected. + Region of memory to be used, from ss to ss+nn. + The memory region may be marked as e820 type 12 (0xc) + and is NVDIMM or ADR memory. + memory_corruption_check=0/1 [X86] Some BIOSes seem to corrupt the first 64k of memory when doing things like suspend/resume. @@ -2344,12 +2369,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted. parameter, xsave area per process might occupy more memory on xsaves enabled systems. - eagerfpu= [X86] - on enable eager fpu restore - off disable eager fpu restore - auto selects the default scheme, which automatically - enables eagerfpu restore for xsaveopt. - nohlt [BUGS=ARM,SH] Tells the kernel that the sleep(SH) or wfi(ARM) instruction doesn't work correctly and not to use it. This is also useful when using JTAG debugger. @@ -3768,6 +3787,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted. READ_CAPACITY_16 command); f = NO_REPORT_OPCODES (don't use report opcodes command, uas only); + g = MAX_SECTORS_240 (don't transfer more than + 240 sectors at a time, uas only); h = CAPACITY_HEURISTICS (decrease the reported device capacity by one sector if the number is odd); diff --git a/Documentation/kmemcheck.txt b/Documentation/kmemcheck.txt index a41bdebbe87bf459e3c07d1dfd093f9eb0e80c3e..80aae85d8da6c1b8476fd6824553ae7070e5c508 100644 --- a/Documentation/kmemcheck.txt +++ b/Documentation/kmemcheck.txt @@ -82,8 +82,8 @@ menu to even appear in "menuconfig". These are: o CONFIG_DEBUG_PAGEALLOC=n - This option is located under "Kernel hacking" / "Debug page memory - allocations". + This option is located under "Kernel hacking" / "Memory Debugging" + / "Debug page memory allocations". In addition, I highly recommend turning on CONFIG_DEBUG_INFO=y. This is also located under "Kernel hacking". With this, you will be able to get line number diff --git a/Documentation/kprobes.txt b/Documentation/kprobes.txt index 1488b6525eb68dbf8310bc1eeb7946fe815ad919..1f9b3e2b98aec9a6687ae14b4f85d7c143729c07 100644 --- a/Documentation/kprobes.txt +++ b/Documentation/kprobes.txt @@ -305,8 +305,8 @@ architectures: 3. Configuring Kprobes When configuring the kernel using make menuconfig/xconfig/oldconfig, -ensure that CONFIG_KPROBES is set to "y". Under "Instrumentation -Support", look for "Kprobes". +ensure that CONFIG_KPROBES is set to "y". Under "General setup", look +for "Kprobes". So that you can load and unload Kprobes-based instrumentation modules, make sure "Loadable module support" (CONFIG_MODULES) and "Module diff --git a/Documentation/laptops/thinkpad-acpi.txt b/Documentation/laptops/thinkpad-acpi.txt index fc04c14de4bbc3705e14eddb97a214ca8a7f6331..72a150d8f3dfa58975a7ed05d0371e475e059e5b 100644 --- a/Documentation/laptops/thinkpad-acpi.txt +++ b/Documentation/laptops/thinkpad-acpi.txt @@ -1355,6 +1355,24 @@ Sysfs notes: rfkill controller switch "tpacpi_uwb_sw": refer to Documentation/rfkill.txt for details. +Adaptive keyboard +----------------- + +sysfs device attribute: adaptive_kbd_mode + +This sysfs attribute controls the keyboard "face" that will be shown on the +Lenovo X1 Carbon 2nd gen (2014)'s adaptive keyboard. The value can be read +and set. + +1 = Home mode +2 = Web-browser mode +3 = Web-conference mode +4 = Function mode +5 = Layflat mode + +For more details about which buttons will appear depending on the mode, please +review the laptop's user guide: +http://www.lenovo.com/shop/americas/content/user_guides/x1carbon_2_ug_en.pdf Multiple Commands, Module Parameters ------------------------------------ diff --git a/Documentation/md-cluster.txt b/Documentation/md-cluster.txt new file mode 100644 index 0000000000000000000000000000000000000000..de1af7db33551d311eab599bd6a4c227ad8d904b --- /dev/null +++ b/Documentation/md-cluster.txt @@ -0,0 +1,176 @@ +The cluster MD is a shared-device RAID for a cluster. + + +1. On-disk format + +Separate write-intent-bitmap are used for each cluster node. +The bitmaps record all writes that may have been started on that node, +and may not yet have finished. The on-disk layout is: + +0 4k 8k 12k +------------------------------------------------------------------- +| idle | md super | bm super [0] + bits | +| bm bits[0, contd] | bm super[1] + bits | bm bits[1, contd] | +| bm super[2] + bits | bm bits [2, contd] | bm super[3] + bits | +| bm bits [3, contd] | | | + +During "normal" functioning we assume the filesystem ensures that only one +node writes to any given block at a time, so a write +request will + - set the appropriate bit (if not already set) + - commit the write to all mirrors + - schedule the bit to be cleared after a timeout. + +Reads are just handled normally. It is up to the filesystem to +ensure one node doesn't read from a location where another node (or the same +node) is writing. + + +2. DLM Locks for management + +There are two locks for managing the device: + +2.1 Bitmap lock resource (bm_lockres) + + The bm_lockres protects individual node bitmaps. They are named in the + form bitmap001 for node 1, bitmap002 for node and so on. When a node + joins the cluster, it acquires the lock in PW mode and it stays so + during the lifetime the node is part of the cluster. The lock resource + number is based on the slot number returned by the DLM subsystem. Since + DLM starts node count from one and bitmap slots start from zero, one is + subtracted from the DLM slot number to arrive at the bitmap slot number. + +3. Communication + +Each node has to communicate with other nodes when starting or ending +resync, and metadata superblock updates. + +3.1 Message Types + + There are 3 types, of messages which are passed + + 3.1.1 METADATA_UPDATED: informs other nodes that the metadata has been + updated, and the node must re-read the md superblock. This is performed + synchronously. + + 3.1.2 RESYNC: informs other nodes that a resync is initiated or ended + so that each node may suspend or resume the region. + +3.2 Communication mechanism + + The DLM LVB is used to communicate within nodes of the cluster. There + are three resources used for the purpose: + + 3.2.1 Token: The resource which protects the entire communication + system. The node having the token resource is allowed to + communicate. + + 3.2.2 Message: The lock resource which carries the data to + communicate. + + 3.2.3 Ack: The resource, acquiring which means the message has been + acknowledged by all nodes in the cluster. The BAST of the resource + is used to inform the receive node that a node wants to communicate. + +The algorithm is: + + 1. receive status + + sender receiver receiver + ACK:CR ACK:CR ACK:CR + + 2. sender get EX of TOKEN + sender get EX of MESSAGE + sender receiver receiver + TOKEN:EX ACK:CR ACK:CR + MESSAGE:EX + ACK:CR + + Sender checks that it still needs to send a message. Messages received + or other events that happened while waiting for the TOKEN may have made + this message inappropriate or redundant. + + 3. sender write LVB. + sender down-convert MESSAGE from EX to CR + sender try to get EX of ACK + [ wait until all receiver has *processed* the MESSAGE ] + + [ triggered by bast of ACK ] + receiver get CR of MESSAGE + receiver read LVB + receiver processes the message + [ wait finish ] + receiver release ACK + + sender receiver receiver + TOKEN:EX MESSAGE:CR MESSAGE:CR + MESSAGE:CR + ACK:EX + + 4. triggered by grant of EX on ACK (indicating all receivers have processed + message) + sender down-convert ACK from EX to CR + sender release MESSAGE + sender release TOKEN + receiver upconvert to EX of MESSAGE + receiver get CR of ACK + receiver release MESSAGE + + sender receiver receiver + ACK:CR ACK:CR ACK:CR + + +4. Handling Failures + +4.1 Node Failure + When a node fails, the DLM informs the cluster with the slot. The node + starts a cluster recovery thread. The cluster recovery thread: + - acquires the bitmap lock of the failed node + - opens the bitmap + - reads the bitmap of the failed node + - copies the set bitmap to local node + - cleans the bitmap of the failed node + - releases bitmap lock of the failed node + - initiates resync of the bitmap on the current node + + The resync process, is the regular md resync. However, in a clustered + environment when a resync is performed, it needs to tell other nodes + of the areas which are suspended. Before a resync starts, the node + send out RESYNC_START with the (lo,hi) range of the area which needs + to be suspended. Each node maintains a suspend_list, which contains + the list of ranges which are currently suspended. On receiving + RESYNC_START, the node adds the range to the suspend_list. Similarly, + when the node performing resync finishes, it send RESYNC_FINISHED + to other nodes and other nodes remove the corresponding entry from + the suspend_list. + + A helper function, should_suspend() can be used to check if a particular + I/O range should be suspended or not. + +4.2 Device Failure + Device failures are handled and communicated with the metadata update + routine. + +5. Adding a new Device +For adding a new device, it is necessary that all nodes "see" the new device +to be added. For this, the following algorithm is used: + + 1. Node 1 issues mdadm --manage /dev/mdX --add /dev/sdYY which issues + ioctl(ADD_NEW_DISC with disc.state set to MD_DISK_CLUSTER_ADD) + 2. Node 1 sends NEWDISK with uuid and slot number + 3. Other nodes issue kobject_uevent_env with uuid and slot number + (Steps 4,5 could be a udev rule) + 4. In userspace, the node searches for the disk, perhaps + using blkid -t SUB_UUID="" + 5. Other nodes issue either of the following depending on whether the disk + was found: + ioctl(ADD_NEW_DISK with disc.state set to MD_DISK_CANDIDATE and + disc.number set to slot number) + ioctl(CLUSTERED_DISK_NACK) + 6. Other nodes drop lock on no-new-devs (CR) if device is found + 7. Node 1 attempts EX lock on no-new-devs + 8. If node 1 gets the lock, it sends METADATA_UPDATED after unmarking the disk + as SpareLocal + 9. If not (get no-new-dev lock), it fails the operation and sends METADATA_UPDATED + 10. Other nodes get the information whether a disk is added or not + by the following METADATA_UPDATED. diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 6974f1c2b4e1edea11b0d31185153d12ef25957c..f95746189b5ded41d9ae8bdbbcafec4e1da8820e 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -1727,7 +1727,7 @@ There are some more advanced barrier functions: } The dma_rmb() allows us guarantee the device has released ownership - before we read the data from the descriptor, and he dma_wmb() allows + before we read the data from the descriptor, and the dma_wmb() allows us to guarantee the data is written to the descriptor before the device can see it now has ownership. The wmb() is needed to guarantee that the cache coherent memory writes have completed before attempting a write to diff --git a/Documentation/memory-hotplug.txt b/Documentation/memory-hotplug.txt index ea03abfc97e95dc660b8028559d940357bc1c8f7..ce2cfcf35c27a0d0972547e82f61fbc38c85b5ab 100644 --- a/Documentation/memory-hotplug.txt +++ b/Documentation/memory-hotplug.txt @@ -149,7 +149,7 @@ For example, assume 1GiB memory block size. A device for a memory starting at (0x100000000 / 1Gib = 4) This device covers address range [0x100000000 ... 0x140000000) -Under each memory block, you can see 4 files: +Under each memory block, you can see 5 files: /sys/devices/system/memory/memoryXXX/phys_index /sys/devices/system/memory/memoryXXX/phys_device @@ -359,38 +359,51 @@ Need more implementation yet.... -------------------------------- 8. Memory hotplug event notifier -------------------------------- -Memory hotplug has event notifier. There are 6 types of notification. +Hotplugging events are sent to a notification queue. -MEMORY_GOING_ONLINE +There are six types of notification defined in include/linux/memory.h: + +MEM_GOING_ONLINE Generated before new memory becomes available in order to be able to prepare subsystems to handle memory. The page allocator is still unable to allocate from the new memory. -MEMORY_CANCEL_ONLINE +MEM_CANCEL_ONLINE Generated if MEMORY_GOING_ONLINE fails. -MEMORY_ONLINE +MEM_ONLINE Generated when memory has successfully brought online. The callback may allocate pages from the new memory. -MEMORY_GOING_OFFLINE +MEM_GOING_OFFLINE Generated to begin the process of offlining memory. Allocations are no longer possible from the memory but some of the memory to be offlined is still in use. The callback can be used to free memory known to a subsystem from the indicated memory block. -MEMORY_CANCEL_OFFLINE +MEM_CANCEL_OFFLINE Generated if MEMORY_GOING_OFFLINE fails. Memory is available again from the memory block that we attempted to offline. -MEMORY_OFFLINE +MEM_OFFLINE Generated after offlining memory is complete. -A callback routine can be registered by +A callback routine can be registered by calling + hotplug_memory_notifier(callback_func, priority) -The second argument of callback function (action) is event types of above. -The third argument is passed by pointer of struct memory_notify. +Callback functions with higher values of priority are called before callback +functions with lower values. + +A callback function must have the following prototype: + + int callback_func( + struct notifier_block *self, unsigned long action, void *arg); + +The first argument of the callback function (self) is a pointer to the block +of the notifier chain that points to the callback function itself. +The second argument (action) is one of the event types described above. +The third argument (arg) passes a pointer of struct memory_notify. struct memory_notify { unsigned long start_pfn; @@ -412,6 +425,18 @@ node loses all memory. If this is -1, then nodemask status is not changed. If status_changed_nid* >= 0, callback should create/discard structures for the node if necessary. +The callback routine shall return one of the values +NOTIFY_DONE, NOTIFY_OK, NOTIFY_BAD, NOTIFY_STOP +defined in include/linux/notifier.h + +NOTIFY_DONE and NOTIFY_OK have no effect on the further processing. + +NOTIFY_BAD is used as response to the MEM_GOING_ONLINE, MEM_GOING_OFFLINE, +MEM_ONLINE, or MEM_OFFLINE action to cancel hotplugging. It stops +further processing of the notification queue. + +NOTIFY_STOP stops further processing of the notification queue. + -------------- 9. Future Work -------------- diff --git a/Documentation/module-signing.txt b/Documentation/module-signing.txt index 09c2382ad0556b196a3b4bb941b9e86597e8ebc5..c72702ec1ded8b0b5d728e6cd0519a5862d2d3c7 100644 --- a/Documentation/module-signing.txt +++ b/Documentation/module-signing.txt @@ -119,9 +119,9 @@ Most notably, in the x509.genkey file, the req_distinguished_name section should be altered from the default: [ req_distinguished_name ] - O = Magrathea - CN = Glacier signing key - emailAddress = slartibartfast@magrathea.h2g2 + #O = Unspecified company + CN = Build time autogenerated kernel key + #emailAddress = unspecified.user@unspecified.company The generated RSA key size can also be set with: diff --git a/Documentation/networking/bonding.txt b/Documentation/networking/bonding.txt index 83bf4986baeabbcc75e03abd5e3d50edd3e97962..334b49ef02d13eea3bbbb6213ec5241881b20fe6 100644 --- a/Documentation/networking/bonding.txt +++ b/Documentation/networking/bonding.txt @@ -51,6 +51,7 @@ Table of Contents 3.4 Configuring Bonding Manually via Sysfs 3.5 Configuration with Interfaces Support 3.6 Overriding Configuration for Special Cases +3.7 Configuring LACP for 802.3ad mode in a more secure way 4. Querying Bonding Configuration 4.1 Bonding Configuration @@ -178,6 +179,27 @@ active_slave active slave, or the empty string if there is no active slave or the current mode does not use an active slave. +ad_actor_sys_prio + + In an AD system, this specifies the system priority. The allowed range + is 1 - 65535. If the value is not specified, it takes 65535 as the + default value. + + This parameter has effect only in 802.3ad mode and is available through + SysFs interface. + +ad_actor_system + + In an AD system, this specifies the mac-address for the actor in + protocol packet exchanges (LACPDUs). The value cannot be NULL or + multicast. It is preferred to have the local-admin bit set for this + mac but driver does not enforce it. If the value is not given then + system defaults to using the masters' mac address as actors' system + address. + + This parameter has effect only in 802.3ad mode and is available through + SysFs interface. + ad_select Specifies the 802.3ad aggregation selection logic to use. The @@ -220,6 +242,21 @@ ad_select This option was added in bonding version 3.4.0. +ad_user_port_key + + In an AD system, the port-key has three parts as shown below - + + Bits Use + 00 Duplex + 01-05 Speed + 06-15 User-defined + + This defines the upper 10 bits of the port key. The values can be + from 0 - 1023. If not given, the system defaults to 0. + + This parameter has effect only in 802.3ad mode and is available through + SysFs interface. + all_slaves_active Specifies that duplicate frames (received on inactive ports) should be @@ -1622,6 +1659,53 @@ output port selection. This feature first appeared in bonding driver version 3.7.0 and support for output slave selection was limited to round-robin and active-backup modes. +3.7 Configuring LACP for 802.3ad mode in a more secure way +---------------------------------------------------------- + +When using 802.3ad bonding mode, the Actor (host) and Partner (switch) +exchange LACPDUs. These LACPDUs cannot be sniffed, because they are +destined to link local mac addresses (which switches/bridges are not +supposed to forward). However, most of the values are easily predictable +or are simply the machine's MAC address (which is trivially known to all +other hosts in the same L2). This implies that other machines in the L2 +domain can spoof LACPDU packets from other hosts to the switch and potentially +cause mayhem by joining (from the point of view of the switch) another +machine's aggregate, thus receiving a portion of that hosts incoming +traffic and / or spoofing traffic from that machine themselves (potentially +even successfully terminating some portion of flows). Though this is not +a likely scenario, one could avoid this possibility by simply configuring +few bonding parameters: + + (a) ad_actor_system : You can set a random mac-address that can be used for + these LACPDU exchanges. The value can not be either NULL or Multicast. + Also it's preferable to set the local-admin bit. Following shell code + generates a random mac-address as described above. + + # sys_mac_addr=$(printf '%02x:%02x:%02x:%02x:%02x:%02x' \ + $(( (RANDOM & 0xFE) | 0x02 )) \ + $(( RANDOM & 0xFF )) \ + $(( RANDOM & 0xFF )) \ + $(( RANDOM & 0xFF )) \ + $(( RANDOM & 0xFF )) \ + $(( RANDOM & 0xFF ))) + # echo $sys_mac_addr > /sys/class/net/bond0/bonding/ad_actor_system + + (b) ad_actor_sys_prio : Randomize the system priority. The default value + is 65535, but system can take the value from 1 - 65535. Following shell + code generates random priority and sets it. + + # sys_prio=$(( 1 + RANDOM + RANDOM )) + # echo $sys_prio > /sys/class/net/bond0/bonding/ad_actor_sys_prio + + (c) ad_user_port_key : Use the user portion of the port-key. The default + keeps this empty. These are the upper 10 bits of the port-key and value + ranges from 0 - 1023. Following shell code generates these 10 bits and + sets it. + + # usr_port_key=$(( RANDOM & 0x3FF )) + # echo $usr_port_key > /sys/class/net/bond0/bonding/ad_user_port_key + + 4 Querying Bonding Configuration ================================= diff --git a/Documentation/networking/can.txt b/Documentation/networking/can.txt index 5abad1e921ca810c1e765d1d84d1ca4a50ce5016..b48d4a1494113c9842b45de8f299f20ecc96c620 100644 --- a/Documentation/networking/can.txt +++ b/Documentation/networking/can.txt @@ -268,6 +268,9 @@ solution for a couple of reasons: struct can_frame { canid_t can_id; /* 32 bit CAN_ID + EFF/RTR/ERR flags */ __u8 can_dlc; /* frame payload length in byte (0 .. 8) */ + __u8 __pad; /* padding */ + __u8 __res0; /* reserved / padding */ + __u8 __res1; /* reserved / padding */ __u8 data[8] __attribute__((aligned(8))); }; diff --git a/Documentation/networking/dctcp.txt b/Documentation/networking/dctcp.txt index 0d5dfbc89ec9e37e27b53a610594dd112d3c6e37..13a85775320875a886442375fcfc027628613f2b 100644 --- a/Documentation/networking/dctcp.txt +++ b/Documentation/networking/dctcp.txt @@ -8,6 +8,7 @@ the data center network to provide multi-bit feedback to the end hosts. To enable it on end hosts: sysctl -w net.ipv4.tcp_congestion_control=dctcp + sysctl -w net.ipv4.tcp_ecn_fallback=0 (optional) All switches in the data center network running DCTCP must support ECN marking and be configured for marking when reaching defined switch buffer diff --git a/Documentation/networking/ieee802154.txt b/Documentation/networking/ieee802154.txt index 22bbc7225f8ed599e8c8b51653c017a6c4845c53..1700756af0570bf75b6422600beb22c935072575 100644 --- a/Documentation/networking/ieee802154.txt +++ b/Documentation/networking/ieee802154.txt @@ -30,8 +30,8 @@ int sd = socket(PF_IEEE802154, SOCK_DGRAM, 0); The address family, socket addresses etc. are defined in the include/net/af_ieee802154.h header or in the special header -in our userspace package (see either linux-zigbee sourceforge download page -or git tree at git://linux-zigbee.git.sourceforge.net/gitroot/linux-zigbee). +in the userspace package (see either http://wpan.cakelab.org/ or the +git tree at https://github.com/linux-wpan/wpan-tools). One can use SOCK_RAW for passing raw data towards device xmit function. YMMV. @@ -49,15 +49,6 @@ Like with WiFi, there are several types of devices implementing IEEE 802.15.4. Those types of devices require different approach to be hooked into Linux kernel. -MLME - MAC Level Management -============================ - -Most of IEEE 802.15.4 MLME interfaces are directly mapped on netlink commands. -See the include/net/nl802154.h header. Our userspace tools package -(see above) provides CLI configuration utility for radio interfaces and simple -coordinator for IEEE 802.15.4 networks as an example users of MLME protocol. - - HardMAC ======= @@ -75,8 +66,6 @@ net_device with a pointer to struct ieee802154_mlme_ops instance. The fields assoc_req, assoc_resp, disassoc_req, start_req, and scan_req are optional. All other fields are required. -We provide an example of simple HardMAC driver at drivers/ieee802154/fakehard.c - SoftMAC ======= @@ -89,7 +78,8 @@ stack interface for network sniffers (e.g. WireShark). This layer is going to be extended soon. -See header include/net/mac802154.h and several drivers in drivers/ieee802154/. +See header include/net/mac802154.h and several drivers in +drivers/net/ieee802154/. Device drivers API @@ -114,18 +104,17 @@ Moreover IEEE 802.15.4 device operations structure should be filled. Fake drivers ============ -In addition there are two drivers available which simulate real devices with -HardMAC (fakehard) and SoftMAC (fakelb - IEEE 802.15.4 loopback driver) -interfaces. This option provides possibility to test and debug stack without -usage of real hardware. +In addition there is a driver available which simulates a real device with +SoftMAC (fakelb - IEEE 802.15.4 loopback driver) interface. This option +provides possibility to test and debug stack without usage of real hardware. -See sources in drivers/ieee802154 folder for more details. +See sources in drivers/net/ieee802154 folder for more details. 6LoWPAN Linux implementation ============================ -The IEEE 802.15.4 standard specifies an MTU of 128 bytes, yielding about 80 +The IEEE 802.15.4 standard specifies an MTU of 127 bytes, yielding about 80 octets of actual MAC payload once security is turned on, on a wireless link with a link throughput of 250 kbps or less. The 6LoWPAN adaptation format [RFC4944] was specified to carry IPv6 datagrams over such constrained links, @@ -140,7 +129,8 @@ In Semptember 2011 the standard update was published - [RFC6282]. It deprecates HC1 and HC2 compression and defines IPHC encoding format which is used in this Linux implementation. -All the code related to 6lowpan you may find in files: net/ieee802154/6lowpan.* +All the code related to 6lowpan you may find in files: net/6lowpan/* +and net/ieee802154/6lowpan/* To setup 6lowpan interface you need (busybox release > 1.17.0): 1. Add IEEE802.15.4 interface and initialize PANid; diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt index 071fb18dc57c868e99367f9d3872bc0e91401414..5fae7704daab292cf900158666c2d4bb80dd2424 100644 --- a/Documentation/networking/ip-sysctl.txt +++ b/Documentation/networking/ip-sysctl.txt @@ -267,6 +267,15 @@ tcp_ecn - INTEGER but do not request ECN on outgoing connections. Default: 2 +tcp_ecn_fallback - BOOLEAN + If the kernel detects that ECN connection misbehaves, enable fall + back to non-ECN. Currently, this knob implements the fallback + from RFC3168, section 6.1.1.1., but we reserve that in future, + additional detection mechanisms could be implemented under this + knob. The value is not used, if tcp_ecn or per route (or congestion + control) ECN settings are disabled. + Default: 1 (fallback enabled) + tcp_fack - BOOLEAN Enable FACK congestion avoidance and fast retransmission. The value is not used, if tcp_sack is not enabled. @@ -742,8 +751,10 @@ IP Variables: ip_local_port_range - 2 INTEGERS Defines the local port range that is used by TCP and UDP to choose the local port. The first number is the first, the - second the last local port number. The default values are - 32768 and 61000 respectively. + second the last local port number. + If possible, it is better these numbers have different parity. + (one even and one odd values) + The default values are 32768 and 60999 respectively. ip_local_reserved_ports - list of comma separated ranges Specify the ports which are reserved for known third-party @@ -766,7 +777,7 @@ ip_local_reserved_ports - list of comma separated ranges ip_local_port_range, e.g.: $ cat /proc/sys/net/ipv4/ip_local_port_range - 32000 61000 + 32000 60999 $ cat /proc/sys/net/ipv4/ip_local_reserved_ports 8080,9148 @@ -1213,6 +1224,14 @@ auto_flowlabels - BOOLEAN FALSE: disabled Default: false +flowlabel_state_ranges - BOOLEAN + Split the flow label number space into two ranges. 0-0x7FFFF is + reserved for the IPv6 flow manager facility, 0x80000-0xFFFFF + is reserved for stateless flow labels as described in RFC6437. + TRUE: enabled + FALSE: disabled + Default: true + anycast_src_echo_reply - BOOLEAN Controls the use of anycast addresses as source addresses for ICMPv6 echo reply diff --git a/Documentation/networking/mpls-sysctl.txt b/Documentation/networking/mpls-sysctl.txt index 639ddf0ece9b5fdd20bcc858c3067d4e20407163..9ed15f86c17c86ffa69fa3527e932b62f4b9ee20 100644 --- a/Documentation/networking/mpls-sysctl.txt +++ b/Documentation/networking/mpls-sysctl.txt @@ -18,3 +18,12 @@ platform_labels - INTEGER Possible values: 0 - 1048575 Default: 0 + +conf//input - BOOL + Control whether packets can be input on this interface. + + If disabled, packets will be discarded without further + processing. + + 0 - disabled (default) + not 0 - enabled diff --git a/Documentation/networking/pktgen.txt b/Documentation/networking/pktgen.txt index 0344f1d45b3765b016f0388a830e3a8e48af31ce..f4be85e9600578e7411f1baa1ab37041a677fe4a 100644 --- a/Documentation/networking/pktgen.txt +++ b/Documentation/networking/pktgen.txt @@ -1,6 +1,6 @@ - HOWTO for the linux packet generator + HOWTO for the linux packet generator ------------------------------------ Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel @@ -50,17 +50,33 @@ For ixgbe use e.g. "30" resulting in approx 33K interrupts/sec (1/30*10^6): # ethtool -C ethX rx-usecs 30 -Viewing threads -=============== -/proc/net/pktgen/kpktgend_0 -Name: kpktgend_0 max_before_softirq: 10000 -Running: -Stopped: eth1 -Result: OK: max_before_softirq=10000 +Kernel threads +============== +Pktgen creates a thread for each CPU with affinity to that CPU. +Which is controlled through procfile /proc/net/pktgen/kpktgend_X. + +Example: /proc/net/pktgen/kpktgend_0 + + Running: + Stopped: eth4@0 + Result: OK: add_device=eth4@0 + +Most important are the devices assigned to the thread. + +The two basic thread commands are: + * add_device DEVICE@NAME -- adds a single device + * rem_device_all -- remove all associated devices + +When adding a device to a thread, a corrosponding procfile is created +which is used for configuring this device. Thus, device names need to +be unique. -Most important are the devices assigned to the thread. Note that a -device can only belong to one thread. +To support adding the same device to multiple threads, which is useful +with multi queue NICs, a the device naming scheme is extended with "@": + device@something +The part after "@" can be anything, but it is custom to use the thread +number. Viewing devices =============== @@ -69,29 +85,32 @@ The Params section holds configured information. The Current section holds running statistics. The Result is printed after a run or after interruption. Example: -/proc/net/pktgen/eth1 +/proc/net/pktgen/eth4@0 -Params: count 10000000 min_pkt_size: 60 max_pkt_size: 60 - frags: 0 delay: 0 clone_skb: 1000000 ifname: eth1 + Params: count 100000 min_pkt_size: 60 max_pkt_size: 60 + frags: 0 delay: 0 clone_skb: 64 ifname: eth4@0 flows: 0 flowlen: 0 - dst_min: 10.10.11.2 dst_max: - src_min: src_max: - src_mac: 00:00:00:00:00:00 dst_mac: 00:04:23:AC:FD:82 - udp_src_min: 9 udp_src_max: 9 udp_dst_min: 9 udp_dst_max: 9 - src_mac_count: 0 dst_mac_count: 0 - Flags: -Current: - pkts-sofar: 10000000 errors: 39664 - started: 1103053986245187us stopped: 1103053999346329us idle: 880401us - seq_num: 10000011 cur_dst_mac_offset: 0 cur_src_mac_offset: 0 - cur_saddr: 0x10a0a0a cur_daddr: 0x20b0a0a - cur_udp_dst: 9 cur_udp_src: 9 + queue_map_min: 0 queue_map_max: 0 + dst_min: 192.168.81.2 dst_max: + src_min: src_max: + src_mac: 90:e2:ba:0a:56:b4 dst_mac: 00:1b:21:3c:9d:f8 + udp_src_min: 9 udp_src_max: 109 udp_dst_min: 9 udp_dst_max: 9 + src_mac_count: 0 dst_mac_count: 0 + Flags: UDPSRC_RND NO_TIMESTAMP QUEUE_MAP_CPU + Current: + pkts-sofar: 100000 errors: 0 + started: 623913381008us stopped: 623913396439us idle: 25us + seq_num: 100001 cur_dst_mac_offset: 0 cur_src_mac_offset: 0 + cur_saddr: 192.168.8.3 cur_daddr: 192.168.81.2 + cur_udp_dst: 9 cur_udp_src: 42 + cur_queue_map: 0 flows: 0 -Result: OK: 13101142(c12220741+d880401) usec, 10000000 (60byte,0frags) - 763292pps 390Mb/sec (390805504bps) errors: 39664 + Result: OK: 15430(c15405+d25) usec, 100000 (60byte,0frags) + 6480562pps 3110Mb/sec (3110669760bps) errors: 0 -Configuring threads and devices -================================ + +Configuring devices +=================== This is done via the /proc interface, and most easily done via pgset as defined in the sample scripts. @@ -126,7 +145,7 @@ Examples: To select queue 1 of a given device, use queue_map_min=1 and queue_map_max=1 - pgset "src_mac_count 1" Sets the number of MACs we'll range through. + pgset "src_mac_count 1" Sets the number of MACs we'll range through. The 'minimum' MAC is what you set with srcmac. pgset "dst_mac_count 1" Sets the number of MACs we'll range through. @@ -145,6 +164,7 @@ Examples: UDPCSUM, IPSEC # IPsec encapsulation (needs CONFIG_XFRM) NODE_ALLOC # node specific memory allocation + NO_TIMESTAMP # disable timestamping pgset spi SPI_VALUE Set specific SA used to transform packet. @@ -192,24 +212,43 @@ Examples: pgset "rate 300M" set rate to 300 Mb/s pgset "ratep 1000000" set rate to 1Mpps + pgset "xmit_mode netif_receive" RX inject into stack netif_receive_skb() + Works with "burst" but not with "clone_skb". + Default xmit_mode is "start_xmit". + Sample scripts ============== -A collection of small tutorial scripts for pktgen is in the -samples/pktgen directory: +A collection of tutorial scripts and helpers for pktgen is in the +samples/pktgen directory. The helper parameters.sh file support easy +and consistant parameter parsing across the sample scripts. + +Usage example and help: + ./pktgen_sample01_simple.sh -i eth4 -m 00:1B:21:3C:9D:F8 -d 192.168.8.2 + +Usage: ./pktgen_sample01_simple.sh [-vx] -i ethX + -i : ($DEV) output interface/device (required) + -s : ($PKT_SIZE) packet size + -d : ($DEST_IP) destination IP + -m : ($DST_MAC) destination MAC-addr + -t : ($THREADS) threads to start + -c : ($SKB_CLONE) SKB clones send before alloc new SKB + -b : ($BURST) HW level bursting of SKBs + -v : ($VERBOSE) verbose + -x : ($DEBUG) debug + +The global variables being set are also listed. E.g. the required +interface/device parameter "-i" sets variable $DEV. Copy the +pktgen_sampleXX scripts and modify them to fit your own needs. + +The old scripts: -pktgen.conf-1-1 # 1 CPU 1 dev pktgen.conf-1-2 # 1 CPU 2 dev -pktgen.conf-2-1 # 2 CPU's 1 dev -pktgen.conf-2-2 # 2 CPU's 2 dev pktgen.conf-1-1-rdos # 1 CPU 1 dev w. route DoS pktgen.conf-1-1-ip6 # 1 CPU 1 dev ipv6 pktgen.conf-1-1-ip6-rdos # 1 CPU 1 dev ipv6 w. route DoS pktgen.conf-1-1-flows # 1 CPU 1 dev multiple flows. -Run in shell: ./pktgen.conf-X-Y -This does all the setup including sending. - Interrupt affinity =================== @@ -217,6 +256,9 @@ Note that when adding devices to a specific CPU it is a good idea to also assign /proc/irq/XX/smp_affinity so that the TX interrupts are bound to the same CPU. This reduces cache bouncing when freeing skbs. +Plus using the device flag QUEUE_MAP_CPU, which maps the SKBs TX queue +to the running threads CPU (directly from smp_processor_id()). + Enable IPsec ============ Default IPsec transformation with ESP encapsulation plus transport mode @@ -237,18 +279,19 @@ Current commands and configuration options start stop +reset ** Thread commands: add_device rem_device_all -max_before_softirq ** Device commands: count clone_skb +burst debug frags @@ -257,10 +300,17 @@ delay src_mac_count dst_mac_count -pkt_size +pkt_size min_pkt_size max_pkt_size +queue_map_min +queue_map_max +skb_priority + +tos (ipv4) +traffic_class (ipv6) + mpls udp_src_min @@ -269,6 +319,8 @@ udp_src_max udp_dst_min udp_dst_max +node + flag IPSRC_RND IPDST_RND @@ -287,6 +339,9 @@ flag UDPCSUM IPSEC NODE_ALLOC + NO_TIMESTAMP + +spi (ipsec) dst_min dst_max @@ -299,8 +354,10 @@ src_mac clear_counters -dst6 src6 +dst6 +dst6_max +dst6_min flows flowlen @@ -308,6 +365,17 @@ flowlen rate ratep +xmit_mode + +vlan_cfi +vlan_id +vlan_p + +svlan_cfi +svlan_id +svlan_p + + References: ftp://robur.slu.se/pub/Linux/net-development/pktgen-testing/ ftp://robur.slu.se/pub/Linux/net-development/pktgen-testing/examples/ diff --git a/Documentation/networking/scaling.txt b/Documentation/networking/scaling.txt index cbfac0949635c1d109930b051e6c4d96dc4c74d1..59f4db2a0c85c02df4f6cee3176ceb173333cac1 100644 --- a/Documentation/networking/scaling.txt +++ b/Documentation/networking/scaling.txt @@ -282,7 +282,7 @@ following is true: - The current CPU's queue head counter >= the recorded tail counter value in rps_dev_flow[i] -- The current CPU is unset (equal to RPS_NO_CPU) +- The current CPU is unset (>= nr_cpu_ids) - The current CPU is offline After this check, the packet is sent to the (possibly updated) current diff --git a/Documentation/networking/switchdev.txt b/Documentation/networking/switchdev.txt index f981a9295a39a14245f884b1fbc810817f74999c..da82cd75a4f6492a2fcb9b9daaf7cee83e625be4 100644 --- a/Documentation/networking/switchdev.txt +++ b/Documentation/networking/switchdev.txt @@ -1,59 +1,367 @@ -Switch (and switch-ish) device drivers HOWTO -=========================== - -Please note that the word "switch" is here used in very generic meaning. -This include devices supporting L2/L3 but also various flow offloading chips, -including switches embedded into SR-IOV NICs. - -Lets describe a topology a bit. Imagine the following example: - - +----------------------------+ +---------------+ - | SOME switch chip | | CPU | - +----------------------------+ +---------------+ - port1 port2 port3 port4 MNGMNT | PCI-E | - | | | | | +---------------+ - PHY PHY | | | | NIC0 NIC1 - | | | | | | - | | +- PCI-E -+ | | - | +------- MII -------+ | - +------------- MII ------------+ - -In this example, there are two independent lines between the switch silicon -and CPU. NIC0 and NIC1 drivers are not aware of a switch presence. They are -separate from the switch driver. SOME switch chip is by managed by a driver -via PCI-E device MNGMNT. Note that MNGMNT device, NIC0 and NIC1 may be -connected to some other type of bus. - -Now, for the previous example show the representation in kernel: - - +----------------------------+ +---------------+ - | SOME switch chip | | CPU | - +----------------------------+ +---------------+ - sw0p0 sw0p1 sw0p2 sw0p3 MNGMNT | PCI-E | - | | | | | +---------------+ - PHY PHY | | | | eth0 eth1 - | | | | | | - | | +- PCI-E -+ | | - | +------- MII -------+ | - +------------- MII ------------+ - -Lets call the example switch driver for SOME switch chip "SOMEswitch". This -driver takes care of PCI-E device MNGMNT. There is a netdevice instance sw0pX -created for each port of a switch. These netdevices are instances -of "SOMEswitch" driver. sw0pX netdevices serve as a "representation" -of the switch chip. eth0 and eth1 are instances of some other existing driver. - -The only difference of the switch-port netdevice from the ordinary netdevice -is that is implements couple more NDOs: - - ndo_switch_parent_id_get - This returns the same ID for two port netdevices - of the same physical switch chip. This is - mandatory to be implemented by all switch drivers - and serves the caller for recognition of a port - netdevice. - ndo_switch_parent_* - Functions that serve for a manipulation of the switch - chip itself (it can be though of as a "parent" of the - port, therefore the name). They are not port-specific. - Caller might use arbitrary port netdevice of the same - switch and it will make no difference. - ndo_switch_port_* - Functions that serve for a port-specific manipulation. +Ethernet switch device driver model (switchdev) +=============================================== +Copyright (c) 2014 Jiri Pirko +Copyright (c) 2014-2015 Scott Feldman + + +The Ethernet switch device driver model (switchdev) is an in-kernel driver +model for switch devices which offload the forwarding (data) plane from the +kernel. + +Figure 1 is a block diagram showing the components of the switchdev model for +an example setup using a data-center-class switch ASIC chip. Other setups +with SR-IOV or soft switches, such as OVS, are possible. + + +                             User-space tools                                  +                                                                               +       user space                   |                                          +      +-------------------------------------------------------------------+    +       kernel                       | Netlink                                  +                                    |                                          +                     +--------------+-------------------------------+          +                     |         Network stack                        |          +                     |           (Linux)                            |          +                     |                                              |          +                     +----------------------------------------------+          +                                                                               + sw1p2 sw1p4 sw1p6 +                      sw1p1  + sw1p3 +  sw1p5 +         eth1              +                        +    |    +    |    +    |            +                +                        |    |    |    |    |    |            |                +                     +--+----+----+----+-+--+----+---+  +-----+-----+          +                     |         Switch driver         |  |    mgmt   |          +                     |        (this document)        |  |   driver  |          +                     |                               |  |           |          +                     +--------------+----------------+  +-----------+          +                                    |                                          +       kernel                       | HW bus (eg PCI)                          +      +-------------------------------------------------------------------+    +       hardware                     |                                          +                     +--------------+---+------------+                         +                     |         Switch device (sw1)   |                         +                     |  +----+                       +--------+                +                     |  |    v offloaded data path   | mgmt port               +                     |  |    |                       |                         +                     +--|----|----+----+----+----+---+                         +                        |    |    |    |    |    |                             +                        +    +    +    +    +    +                             +                       p1   p2   p3   p4   p5   p6 +                                        +                             front-panel ports                                 +                                                                               + + Fig 1. + + +Include Files +------------- + +#include +#include + + +Configuration +------------- + +Use "depends NET_SWITCHDEV" in driver's Kconfig to ensure switchdev model +support is built for driver. + + +Switch Ports +------------ + +On switchdev driver initialization, the driver will allocate and register a +struct net_device (using register_netdev()) for each enumerated physical switch +port, called the port netdev. A port netdev is the software representation of +the physical port and provides a conduit for control traffic to/from the +controller (the kernel) and the network, as well as an anchor point for higher +level constructs such as bridges, bonds, VLANs, tunnels, and L3 routers. Using +standard netdev tools (iproute2, ethtool, etc), the port netdev can also +provide to the user access to the physical properties of the switch port such +as PHY link state and I/O statistics. + +There is (currently) no higher-level kernel object for the switch beyond the +port netdevs. All of the switchdev driver ops are netdev ops or switchdev ops. + +A switch management port is outside the scope of the switchdev driver model. +Typically, the management port is not participating in offloaded data plane and +is loaded with a different driver, such as a NIC driver, on the management port +device. + +Port Netdev Naming +^^^^^^^^^^^^^^^^^^ + +Udev rules should be used for port netdev naming, using some unique attribute +of the port as a key, for example the port MAC address or the port PHYS name. +Hard-coding of kernel netdev names within the driver is discouraged; let the +kernel pick the default netdev name, and let udev set the final name based on a +port attribute. + +Using port PHYS name (ndo_get_phys_port_name) for the key is particularly +useful for dynamically-named ports where the device names its ports based on +external configuration. For example, if a physical 40G port is split logically +into 4 10G ports, resulting in 4 port netdevs, the device can give a unique +name for each port using port PHYS name. The udev rule would be: + +SUBSYSTEM=="net", ACTION=="add", DRIVER="", ATTR{phys_port_name}!="", \ + NAME="$attr{phys_port_name}" + +Suggested naming convention is "swXpYsZ", where X is the switch name or ID, Y +is the port name or ID, and Z is the sub-port name or ID. For example, sw1p1s0 +would be sub-port 0 on port 1 on switch 1. + +Switch ID +^^^^^^^^^ + +The switchdev driver must implement the switchdev op switchdev_port_attr_get +for SWITCHDEV_ATTR_PORT_PARENT_ID for each port netdev, returning the same +physical ID for each port of a switch. The ID must be unique between switches +on the same system. The ID does not need to be unique between switches on +different systems. + +The switch ID is used to locate ports on a switch and to know if aggregated +ports belong to the same switch. + +Port Features +^^^^^^^^^^^^^ + +NETIF_F_NETNS_LOCAL + +If the switchdev driver (and device) only supports offloading of the default +network namespace (netns), the driver should set this feature flag to prevent +the port netdev from being moved out of the default netns. A netns-aware +driver/device would not set this flag and be responsible for partitioning +hardware to preserve netns containment. This means hardware cannot forward +traffic from a port in one namespace to another port in another namespace. + +Port Topology +^^^^^^^^^^^^^ + +The port netdevs representing the physical switch ports can be organized into +higher-level switching constructs. The default construct is a standalone +router port, used to offload L3 forwarding. Two or more ports can be bonded +together to form a LAG. Two or more ports (or LAGs) can be bridged to bridge +L2 networks. VLANs can be applied to sub-divide L2 networks. L2-over-L3 +tunnels can be built on ports. These constructs are built using standard Linux +tools such as the bridge driver, the bonding/team drivers, and netlink-based +tools such as iproute2. + +The switchdev driver can know a particular port's position in the topology by +monitoring NETDEV_CHANGEUPPER notifications. For example, a port moved into a +bond will see it's upper master change. If that bond is moved into a bridge, +the bond's upper master will change. And so on. The driver will track such +movements to know what position a port is in in the overall topology by +registering for netdevice events and acting on NETDEV_CHANGEUPPER. + +L2 Forwarding Offload +--------------------- + +The idea is to offload the L2 data forwarding (switching) path from the kernel +to the switchdev device by mirroring bridge FDB entries down to the device. An +FDB entry is the {port, MAC, VLAN} tuple forwarding destination. + +To offloading L2 bridging, the switchdev driver/device should support: + + - Static FDB entries installed on a bridge port + - Notification of learned/forgotten src mac/vlans from device + - STP state changes on the port + - VLAN flooding of multicast/broadcast and unknown unicast packets + +Static FDB Entries +^^^^^^^^^^^^^^^^^^ + +The switchdev driver should implement ndo_fdb_add, ndo_fdb_del and ndo_fdb_dump +to support static FDB entries installed to the device. Static bridge FDB +entries are installed, for example, using iproute2 bridge cmd: + + bridge fdb add ADDR dev DEV [vlan VID] [self] + +The driver should use the helper switchdev_port_fdb_xxx ops for ndo_fdb_xxx +ops, and handle add/delete/dump of SWITCHDEV_OBJ_PORT_FDB object using +switchdev_port_obj_xxx ops. + +XXX: what should be done if offloading this rule to hardware fails (for +example, due to full capacity in hardware tables) ? + +Note: by default, the bridge does not filter on VLAN and only bridges untagged +traffic. To enable VLAN support, turn on VLAN filtering: + + echo 1 >/sys/class/net//bridge/vlan_filtering + +Notification of Learned/Forgotten Source MAC/VLANs +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The switch device will learn/forget source MAC address/VLAN on ingress packets +and notify the switch driver of the mac/vlan/port tuples. The switch driver, +in turn, will notify the bridge driver using the switchdev notifier call: + + err = call_switchdev_notifiers(val, dev, info); + +Where val is SWITCHDEV_FDB_ADD when learning and SWITCHDEV_FDB_DEL when +forgetting, and info points to a struct switchdev_notifier_fdb_info. On +SWITCHDEV_FDB_ADD, the bridge driver will install the FDB entry into the +bridge's FDB and mark the entry as NTF_EXT_LEARNED. The iproute2 bridge +command will label these entries "offload": + + $ bridge fdb + 52:54:00:12:35:01 dev sw1p1 master br0 permanent + 00:02:00:00:02:00 dev sw1p1 master br0 offload + 00:02:00:00:02:00 dev sw1p1 self + 52:54:00:12:35:02 dev sw1p2 master br0 permanent + 00:02:00:00:03:00 dev sw1p2 master br0 offload + 00:02:00:00:03:00 dev sw1p2 self + 33:33:00:00:00:01 dev eth0 self permanent + 01:00:5e:00:00:01 dev eth0 self permanent + 33:33:ff:00:00:00 dev eth0 self permanent + 01:80:c2:00:00:0e dev eth0 self permanent + 33:33:00:00:00:01 dev br0 self permanent + 01:00:5e:00:00:01 dev br0 self permanent + 33:33:ff:12:35:01 dev br0 self permanent + +Learning on the port should be disabled on the bridge using the bridge command: + + bridge link set dev DEV learning off + +Learning on the device port should be enabled, as well as learning_sync: + + bridge link set dev DEV learning on self + bridge link set dev DEV learning_sync on self + +Learning_sync attribute enables syncing of the learned/forgotton FDB entry to +the bridge's FDB. It's possible, but not optimal, to enable learning on the +device port and on the bridge port, and disable learning_sync. + +To support learning and learning_sync port attributes, the driver implements +switchdev op switchdev_port_attr_get/set for SWITCHDEV_ATTR_PORT_BRIDGE_FLAGS. +The driver should initialize the attributes to the hardware defaults. + +FDB Ageing +^^^^^^^^^^ + +There are two FDB ageing models supported: 1) ageing by the device, and 2) +ageing by the kernel. Ageing by the device is preferred if many FDB entries +are supported. The driver calls call_switchdev_notifiers(SWITCHDEV_FDB_DEL, +...) to age out the FDB entry. In this model, ageing by the kernel should be +turned off. XXX: how to turn off ageing in kernel on a per-port basis or +otherwise prevent the kernel from ageing out the FDB entry? + +In the kernel ageing model, the standard bridge ageing mechanism is used to age +out stale FDB entries. To keep an FDB entry "alive", the driver should refresh +the FDB entry by calling call_switchdev_notifiers(SWITCHDEV_FDB_ADD, ...). The +notification will reset the FDB entry's last-used time to now. The driver +should rate limit refresh notifications, for example, no more than once a +second. If the FDB entry expires, ndo_fdb_del is called to remove entry from +the device. XXX: this last part isn't currently correct: ndo_fdb_del isn't +called, so the stale entry remains in device...this need to get fixed. + +FDB Flush +^^^^^^^^^ + +XXX: Unimplemented. Need to support FDB flush by bridge driver for port and +remove both static and learned FDB entries. + +STP State Change on Port +^^^^^^^^^^^^^^^^^^^^^^^^ + +Internally or with a third-party STP protocol implementation (e.g. mstpd), the +bridge driver maintains the STP state for ports, and will notify the switch +driver of STP state change on a port using the switchdev op +switchdev_attr_port_set for SWITCHDEV_ATTR_PORT_STP_UPDATE. + +State is one of BR_STATE_*. The switch driver can use STP state updates to +update ingress packet filter list for the port. For example, if port is +DISABLED, no packets should pass, but if port moves to BLOCKED, then STP BPDUs +and other IEEE 01:80:c2:xx:xx:xx link-local multicast packets can pass. + +Note that STP BDPUs are untagged and STP state applies to all VLANs on the port +so packet filters should be applied consistently across untagged and tagged +VLANs on the port. + +Flooding L2 domain +^^^^^^^^^^^^^^^^^^ + +For a given L2 VLAN domain, the switch device should flood multicast/broadcast +and unknown unicast packets to all ports in domain, if allowed by port's +current STP state. The switch driver, knowing which ports are within which +vlan L2 domain, can program the switch device for flooding. The packet should +also be sent to the port netdev for processing by the bridge driver. The +bridge should not reflood the packet to the same ports the device flooded. +XXX: the mechanism to avoid duplicate flood packets is being discuseed. + +It is possible for the switch device to not handle flooding and push the +packets up to the bridge driver for flooding. This is not ideal as the number +of ports scale in the L2 domain as the device is much more efficient at +flooding packets that software. + +IGMP Snooping +^^^^^^^^^^^^^ + +XXX: complete this section + + +L3 Routing Offload +------------------ + +Offloading L3 routing requires that device be programmed with FIB entries from +the kernel, with the device doing the FIB lookup and forwarding. The device +does a longest prefix match (LPM) on FIB entries matching route prefix and +forwards the packet to the matching FIB entry's nexthop(s) egress ports. + +To program the device, the driver implements support for +SWITCHDEV_OBJ_IPV[4|6]_FIB object using switchdev_port_obj_xxx ops. +switchdev_port_obj_add is used for both adding a new FIB entry to the device, +or modifying an existing entry on the device. + +XXX: Currently, only SWITCHDEV_OBJ_IPV4_FIB objects are supported. + +SWITCHDEV_OBJ_IPV4_FIB object passes: + + struct switchdev_obj_ipv4_fib { /* IPV4_FIB */ + u32 dst; + int dst_len; + struct fib_info *fi; + u8 tos; + u8 type; + u32 nlflags; + u32 tb_id; + } ipv4_fib; + +to add/modify/delete IPv4 dst/dest_len prefix on table tb_id. The *fi +structure holds details on the route and route's nexthops. *dev is one of the +port netdevs mentioned in the routes next hop list. If the output port netdevs +referenced in the route's nexthop list don't all have the same switch ID, the +driver is not called to add/modify/delete the FIB entry. + +Routes offloaded to the device are labeled with "offload" in the ip route +listing: + + $ ip route show + default via 192.168.0.2 dev eth0 + 11.0.0.0/30 dev sw1p1 proto kernel scope link src 11.0.0.2 offload + 11.0.0.4/30 via 11.0.0.1 dev sw1p1 proto zebra metric 20 offload + 11.0.0.8/30 dev sw1p2 proto kernel scope link src 11.0.0.10 offload + 11.0.0.12/30 via 11.0.0.9 dev sw1p2 proto zebra metric 20 offload + 12.0.0.2 proto zebra metric 30 offload + nexthop via 11.0.0.1 dev sw1p1 weight 1 + nexthop via 11.0.0.9 dev sw1p2 weight 1 + 12.0.0.3 via 11.0.0.1 dev sw1p1 proto zebra metric 20 offload + 12.0.0.4 via 11.0.0.9 dev sw1p2 proto zebra metric 20 offload + 192.168.0.0/24 dev eth0 proto kernel scope link src 192.168.0.15 + +XXX: add/mod/del IPv6 FIB API + +Nexthop Resolution +^^^^^^^^^^^^^^^^^^ + +The FIB entry's nexthop list contains the nexthop tuple (gateway, dev), but for +the switch device to forward the packet with the correct dst mac address, the +nexthop gateways must be resolved to the neighbor's mac address. Neighbor mac +address discovery comes via the ARP (or ND) process and is available via the +arp_tbl neighbor table. To resolve the routes nexthop gateways, the driver +should trigger the kernel's neighbor resolution process. See the rocker +driver's rocker_port_ipv4_resolve() for an example. + +The driver can monitor for updates to arp_tbl using the netevent notifier +NETEVENT_NEIGH_UPDATE. The device can be programmed with resolved nexthops +for the routes as arp_tbl updates. diff --git a/Documentation/networking/tc-actions-env-rules.txt b/Documentation/networking/tc-actions-env-rules.txt index 70d6cf608251b5cc9b35550c72c2095f2a87c026..f37814693ad31e381fc01d4a1878ba3490cb6d57 100644 --- a/Documentation/networking/tc-actions-env-rules.txt +++ b/Documentation/networking/tc-actions-env-rules.txt @@ -8,14 +8,8 @@ For example if your action queues a packet to be processed later, or intentionally branches by redirecting a packet, then you need to clone the packet. -There are certain fields in the skb tc_verd that need to be reset so we -avoid loops, etc. A few are generic enough that skb_act_clone() -resets them for you, so invoke skb_act_clone() rather than skb_clone(). - 2) If you munge any packet thou shalt call pskb_expand_head in the case someone else is referencing the skb. After that you "own" the skb. -You must also tell us if it is ok to munge the packet (TC_OK2MUNGE), -this way any action downstream can stomp on the packet. 3) Dropping packets you don't own is a no-no. You simply return TC_ACT_SHOT to the caller and they will drop it. diff --git a/Documentation/powerpc/transactional_memory.txt b/Documentation/powerpc/transactional_memory.txt index ba0a2a4a54ba1ffcb484786381b91f5113a62ad6..ded69794a5c09da762db7c4c61cc3d23e619d0fa 100644 --- a/Documentation/powerpc/transactional_memory.txt +++ b/Documentation/powerpc/transactional_memory.txt @@ -74,23 +74,22 @@ Causes of transaction aborts Syscalls ======== -Syscalls made from within an active transaction will not be performed and the -transaction will be doomed by the kernel with the failure code TM_CAUSE_SYSCALL -| TM_CAUSE_PERSISTENT. +Performing syscalls from within transaction is not recommended, and can lead +to unpredictable results. -Syscalls made from within a suspended transaction are performed as normal and -the transaction is not explicitly doomed by the kernel. However, what the -kernel does to perform the syscall may result in the transaction being doomed -by the hardware. The syscall is performed in suspended mode so any side -effects will be persistent, independent of transaction success or failure. No -guarantees are provided by the kernel about which syscalls will affect -transaction success. +Syscalls do not by design abort transactions, but beware: The kernel code will +not be running in transactional state. The effect of syscalls will always +remain visible, but depending on the call they may abort your transaction as a +side-effect, read soon-to-be-aborted transactional data that should not remain +invisible, etc. If you constantly retry a transaction that constantly aborts +itself by calling a syscall, you'll have a livelock & make no progress. -Care must be taken when relying on syscalls to abort during active transactions -if the calls are made via a library. Libraries may cache values (which may -give the appearance of success) or perform operations that cause transaction -failure before entering the kernel (which may produce different failure codes). -Examples are glibc's getpid() and lazy symbol resolution. +Simple syscalls (e.g. sigprocmask()) "could" be OK. Even things like write() +from, say, printf() should be OK as long as the kernel does not access any +memory that was accessed transactionally. + +Consider any syscalls that happen to work as debug-only -- not recommended for +production use. Best to queue them up till after the transaction is over. Signals @@ -177,7 +176,8 @@ kernel aborted a transaction: TM_CAUSE_RESCHED Thread was rescheduled. TM_CAUSE_TLBI Software TLB invalid. TM_CAUSE_FAC_UNAV FP/VEC/VSX unavailable trap. - TM_CAUSE_SYSCALL Syscall from active transaction. + TM_CAUSE_SYSCALL Currently unused; future syscalls that must abort + transactions for consistency will use this. TM_CAUSE_SIGNAL Signal delivered. TM_CAUSE_MISC Currently unused. TM_CAUSE_ALIGNMENT Alignment fault. diff --git a/Documentation/printk-formats.txt b/Documentation/printk-formats.txt index cb6a596072bbe375aacbc6202d0eed7b6ab294cb..2216eb187c213b4c0c5140a760f9df3098150e41 100644 --- a/Documentation/printk-formats.txt +++ b/Documentation/printk-formats.txt @@ -228,7 +228,7 @@ UUID/GUID addresses: lower ('l') or upper case ('L') hex characters - and big endian order in lower ('b') or upper case ('B') hex characters. - Where no additional specifiers are used the default little endian + Where no additional specifiers are used the default big endian order with lower case hex characters will be printed. Passed by reference. @@ -273,6 +273,16 @@ struct clk: Passed by reference. +bitmap and its derivatives such as cpumask and nodemask: + + %*pb 0779 + %*pbl 0,3-6,8-10 + + For printing bitmap and its derivatives such as cpumask and nodemask, + %*pb output the bitmap with field width as the number of bits and %*pbl + output the bitmap as range list with field width as the number of bits. + + Passed by reference. Thank you for your cooperation and attention. diff --git a/Documentation/s390/qeth.txt b/Documentation/s390/qeth.txt index 74122ada99492c573e6cc29303bbc24637b5c1f0..aa06fcf5f8c21d8e5e073307822de89a0cb590fa 100644 --- a/Documentation/s390/qeth.txt +++ b/Documentation/s390/qeth.txt @@ -1,6 +1,6 @@ IBM s390 QDIO Ethernet Driver -HiperSockets Bridge Port Support +OSA and HiperSockets Bridge Port Support Uevents @@ -8,7 +8,7 @@ To generate the events the device must be assigned a role of either a primary or a secondary Bridge Port. For more information, see "z/VM Connectivity, SC24-6174". -When run on HiperSockets Bridge Capable Port hardware, and the state +When run on an OSA or HiperSockets Bridge Capable Port hardware, and the state of some configured Bridge Port device on the channel changes, a udev event with ACTION=CHANGE is emitted on behalf of the corresponding ccwgroup device. The event has the following attributes: diff --git a/Documentation/scheduler/completion.txt b/Documentation/scheduler/completion.txt index f77651eca31ea0b32efea5ecdbf1f05f23e72eab..2622bc7a188b0519f87058773e6dc826c5e785a9 100644 --- a/Documentation/scheduler/completion.txt +++ b/Documentation/scheduler/completion.txt @@ -7,24 +7,24 @@ Introduction: ------------- If you have one or more threads of execution that must wait for some process -to have reached a point or a specific state, completions can provide a race -free solution to this problem. Semantically they are somewhat like a -pthread_barriers and have similar use-cases. +to have reached a point or a specific state, completions can provide a +race-free solution to this problem. Semantically they are somewhat like a +pthread_barrier and have similar use-cases. -Completions are a code synchronization mechanism that is preferable to any +Completions are a code synchronization mechanism which is preferable to any misuse of locks. Any time you think of using yield() or some quirky -msleep(1); loop to allow something else to proceed, you probably want to +msleep(1) loop to allow something else to proceed, you probably want to look into using one of the wait_for_completion*() calls instead. The -advantage of using completions is clear intent of the code but also more +advantage of using completions is clear intent of the code, but also more efficient code as both threads can continue until the result is actually needed. Completions are built on top of the generic event infrastructure in Linux, -with the event reduced to a simple flag appropriately called "done" in -struct completion, that tells the waiting threads of execution if they +with the event reduced to a simple flag (appropriately called "done") in +struct completion that tells the waiting threads of execution if they can continue safely. -As completions are scheduling related the code is found in +As completions are scheduling related, the code is found in kernel/sched/completion.c - for details on completion design and implementation see completions-design.txt @@ -32,9 +32,9 @@ implementation see completions-design.txt Usage: ------ -There are three parts to the using completions, the initialization of the +There are three parts to using completions, the initialization of the struct completion, the waiting part through a call to one of the variants of -wait_for_completion() and the signaling side through a call to complete(), +wait_for_completion() and the signaling side through a call to complete() or complete_all(). Further there are some helper functions for checking the state of completions. @@ -50,7 +50,7 @@ handling of completions is: providing the wait queue to place tasks on for waiting and the flag for indicating the state of affairs. -Completions should be named to convey the intent of the waiter. A good +Completions should be named to convey the intent of the waiter. A good example is: wait_for_completion(&early_console_added); @@ -73,7 +73,7 @@ the default state to "not available", that is, "done" is set to 0. The re-initialization function, reinit_completion(), simply resets the done element to "not available", thus again to 0, without touching the -wait queue. Calling init_completion() on the same completions object is +wait queue. Calling init_completion() twice on the same completion object is most likely a bug as it re-initializes the queue to an empty queue and enqueued tasks could get "lost" - use reinit_completion() in that case. @@ -87,10 +87,17 @@ initialization should always use: DECLARE_COMPLETION_ONSTACK(setup_done) suitable for automatic/local variables on the stack and will make lockdep -happy. Note also that one needs to making *sure* the completion passt to +happy. Note also that one needs to make *sure* the completion passed to work threads remains in-scope, and no references remain to on-stack data when the initiating function returns. +Using on-stack completions for code that calls any of the _timeout or +_interruptible/_killable variants is not advisable as they will require +additional synchronization to prevent the on-stack completion object in +the timeout/signal cases from going out of scope. Consider using dynamically +allocated completions when intending to use the _interruptible/_killable +or _timeout variants of wait_for_completion(). + Waiting for completions: ------------------------ @@ -99,34 +106,38 @@ For a thread of execution to wait for some concurrent work to finish, it calls wait_for_completion() on the initialized completion structure. A typical usage scenario is: - structure completion setup_done; + struct completion setup_done; init_completion(&setup_done); - initialze_work(...,&setup_done,...) + initialize_work(...,&setup_done,...) /* run non-dependent code */ /* do setup */ - wait_for_completion(&seupt_done); complete(setup_done) + wait_for_completion(&setup_done); complete(setup_done) -This is not implying any temporal order of wait_for_completion() and the +This is not implying any temporal order on wait_for_completion() and the call to complete() - if the call to complete() happened before the call to wait_for_completion() then the waiting side simply will continue -immediately as all dependencies are satisfied. +immediately as all dependencies are satisfied if not it will block until +completion is signaled by complete(). -Note that wait_for_completion() is calling spin_lock_irq/spin_unlock_irq +Note that wait_for_completion() is calling spin_lock_irq()/spin_unlock_irq(), so it can only be called safely when you know that interrupts are enabled. -Calling it from hard-irq context will result in hard to detect spurious -enabling of interrupts. +Calling it from hard-irq or irqs-off atomic contexts will result in +hard-to-detect spurious enabling of interrupts. wait_for_completion(): void wait_for_completion(struct completion *done): -The default behavior is to wait without a timeout and mark the task as +The default behavior is to wait without a timeout and to mark the task as uninterruptible. wait_for_completion() and its variants are only safe -in soft-interrupt or process context but not in hard-irq context. +in process context (as they can sleep) but not in atomic context, +interrupt context, with disabled irqs. or preemption is disabled - see also +try_wait_for_completion() below for handling completion in atomic/interrupt +context. + As all variants of wait_for_completion() can (obviously) block for a long -time, you probably don't want to call this with held locks - see also -try_wait_for_completion() below. +time, you probably don't want to call this with held mutexes. Variants available: @@ -141,43 +152,44 @@ A common problem that occurs is to have unclean assignment of return types, so care should be taken with assigning return-values to variables of proper type. Checking for the specific meaning of return values also has been found to be quite inaccurate e.g. constructs like -if(!wait_for_completion_interruptible_timeout(...)) would execute the same +if (!wait_for_completion_interruptible_timeout(...)) would execute the same code path for successful completion and for the interrupted case - which is probably not what you want. int wait_for_completion_interruptible(struct completion *done) -marking the task TASK_INTERRUPTIBLE. If a signal was received while waiting. -It will return -ERESTARTSYS and 0 otherwise. +This function marks the task TASK_INTERRUPTIBLE. If a signal was received +while waiting it will return -ERESTARTSYS; 0 otherwise. unsigned long wait_for_completion_timeout(struct completion *done, unsigned long timeout) -The task is marked as TASK_UNINTERRUPTIBLE and will wait at most timeout -(in jiffies). If timeout occurs it return 0 else the remaining time in -jiffies (but at least 1). Timeouts are preferably passed by msecs_to_jiffies() -or usecs_to_jiffies(). If the returned timeout value is deliberately ignored -a comment should probably explain why (e.g. see drivers/mfd/wm8350-core.c -wm8350_read_auxadc()) +The task is marked as TASK_UNINTERRUPTIBLE and will wait at most 'timeout' +(in jiffies). If timeout occurs it returns 0 else the remaining time in +jiffies (but at least 1). Timeouts are preferably calculated with +msecs_to_jiffies() or usecs_to_jiffies(). If the returned timeout value is +deliberately ignored a comment should probably explain why (e.g. see +drivers/mfd/wm8350-core.c wm8350_read_auxadc()) long wait_for_completion_interruptible_timeout( struct completion *done, unsigned long timeout) -passing a timeout in jiffies and marking the task as TASK_INTERRUPTIBLE. If a -signal was received it will return -ERESTARTSYS, 0 if completion timed-out and -the remaining time in jiffies if completion occurred. +This function passes a timeout in jiffies and marks the task as +TASK_INTERRUPTIBLE. If a signal was received it will return -ERESTARTSYS; +otherwise it returns 0 if the completion timed out or the remaining time in +jiffies if completion occurred. -Further variants include _killable which passes TASK_KILLABLE as the -designated tasks state and will return a -ERESTARTSYS if interrupted or -else 0 if completions was achieved as well as a _timeout variant. +Further variants include _killable which uses TASK_KILLABLE as the +designated tasks state and will return -ERESTARTSYS if it is interrupted or +else 0 if completion was achieved. There is a _timeout variant as well: long wait_for_completion_killable(struct completion *done) long wait_for_completion_killable_timeout(struct completion *done, unsigned long timeout) -The _io variants wait_for_completion_io behave the same as the non-_io +The _io variants wait_for_completion_io() behave the same as the non-_io variants, except for accounting waiting time as waiting on IO, which has -an impact on how scheduling is calculated. +an impact on how the task is accounted in scheduling stats. void wait_for_completion_io(struct completion *done) unsigned long wait_for_completion_io_timeout(struct completion *done @@ -187,13 +199,13 @@ an impact on how scheduling is calculated. Signaling completions: ---------------------- -A thread of execution that wants to signal that the conditions for -continuation have been achieved calls complete() to signal exactly one -of the waiters that it can continue. +A thread that wants to signal that the conditions for continuation have been +achieved calls complete() to signal exactly one of the waiters that it can +continue. void complete(struct completion *done) -or calls complete_all to signal all current and future waiters. +or calls complete_all() to signal all current and future waiters. void complete_all(struct completion *done) @@ -205,32 +217,32 @@ wakeup order is the same in which they were enqueued (FIFO order). If complete() is called multiple times then this will allow for that number of waiters to continue - each call to complete() will simply increment the done element. Calling complete_all() multiple times is a bug though. Both -complete() and complete_all() can be called in hard-irq context safely. +complete() and complete_all() can be called in hard-irq/atomic context safely. There only can be one thread calling complete() or complete_all() on a -particular struct completions at any time - serialized through the wait +particular struct completion at any time - serialized through the wait queue spinlock. Any such concurrent calls to complete() or complete_all() probably are a design bug. Signaling completion from hard-irq context is fine as it will appropriately -lock with spin_lock_irqsave/spin_unlock_irqrestore. +lock with spin_lock_irqsave/spin_unlock_irqrestore and it will never sleep. try_wait_for_completion()/completion_done(): -------------------------------------------- -The try_wait_for_completion will not put the thread on the wait queue but -rather returns false if it would need to enqueue (block) the thread, else it -consumes any posted completions and returns true. +The try_wait_for_completion() function will not put the thread on the wait +queue but rather returns false if it would need to enqueue (block) the thread, +else it consumes one posted completion and returns true. - bool try_wait_for_completion(struct completion *done) + bool try_wait_for_completion(struct completion *done) -Finally to check state of a completions without changing it in any way is -provided by completion_done() returning false if there are any posted -completion that was not yet consumed by waiters implying that there are -waiters and true otherwise; +Finally, to check the state of a completion without changing it in any way, +call completion_done(), which returns false if there are no posted +completions that were not yet consumed by waiters (implying that there are +waiters) and true otherwise; - bool completion_done(struct completion *done) + bool completion_done(struct completion *done) Both try_wait_for_completion() and completion_done() are safe to be called in -hard-irq context. +hard-irq or atomic context. diff --git a/Documentation/serial/tty.txt b/Documentation/serial/tty.txt index 1e52d67d0abf5c8ccb86b6aa5d1170f509d73132..dbe6623fed1c286bd49277486492b2960428eff6 100644 --- a/Documentation/serial/tty.txt +++ b/Documentation/serial/tty.txt @@ -198,6 +198,9 @@ TTY_IO_ERROR If set, causes all subsequent userspace read/write TTY_OTHER_CLOSED Device is a pty and the other side has closed. +TTY_OTHER_DONE Device is a pty and the other side has closed and + all pending input processing has been completed. + TTY_NO_WRITE_SPLIT Prevent driver from splitting up writes into smaller chunks. diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index 2b47704f75cb3bfedf836cf02c75afd82c91e405..2ba71cea01723cf3216ef4e95708789b6e0cc9f2 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -237,8 +237,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += "#include \"" + fabric_mod_name + "_base.h\"\n" buf += "#include \"" + fabric_mod_name + "_fabric.h\"\n\n" - buf += "/* Local pointer to allocated TCM configfs fabric module */\n" - buf += "struct target_fabric_configfs *" + fabric_mod_name + "_fabric_configfs;\n\n" + buf += "static const struct target_core_fabric_ops " + fabric_mod_name + "_ops;\n\n" buf += "static struct se_node_acl *" + fabric_mod_name + "_make_nodeacl(\n" buf += " struct se_portal_group *se_tpg,\n" @@ -309,8 +308,8 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " }\n" buf += " tpg->" + fabric_mod_port + " = " + fabric_mod_port + ";\n" buf += " tpg->" + fabric_mod_port + "_tpgt = tpgt;\n\n" - buf += " ret = core_tpg_register(&" + fabric_mod_name + "_fabric_configfs->tf_ops, wwn,\n" - buf += " &tpg->se_tpg, (void *)tpg,\n" + buf += " ret = core_tpg_register(&" + fabric_mod_name + "_ops, wwn,\n" + buf += " &tpg->se_tpg, tpg,\n" buf += " TRANSPORT_TPG_TYPE_NORMAL);\n" buf += " if (ret < 0) {\n" buf += " kfree(tpg);\n" @@ -370,7 +369,10 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " NULL,\n" buf += "};\n\n" - buf += "static struct target_core_fabric_ops " + fabric_mod_name + "_ops = {\n" + buf += "static const struct target_core_fabric_ops " + fabric_mod_name + "_ops = {\n" + buf += " .module = THIS_MODULE,\n" + buf += " .name = " + fabric_mod_name + ",\n" + buf += " .get_fabric_proto_ident = " + fabric_mod_name + "_get_fabric_proto_ident,\n" buf += " .get_fabric_name = " + fabric_mod_name + "_get_fabric_name,\n" buf += " .get_fabric_proto_ident = " + fabric_mod_name + "_get_fabric_proto_ident,\n" buf += " .tpg_get_wwn = " + fabric_mod_name + "_get_fabric_wwn,\n" @@ -413,75 +415,18 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " .fabric_drop_np = NULL,\n" buf += " .fabric_make_nodeacl = " + fabric_mod_name + "_make_nodeacl,\n" buf += " .fabric_drop_nodeacl = " + fabric_mod_name + "_drop_nodeacl,\n" - buf += "};\n\n" - - buf += "static int " + fabric_mod_name + "_register_configfs(void)\n" - buf += "{\n" - buf += " struct target_fabric_configfs *fabric;\n" - buf += " int ret;\n\n" - buf += " printk(KERN_INFO \"" + fabric_mod_name.upper() + " fabric module %s on %s/%s\"\n" - buf += " \" on \"UTS_RELEASE\"\\n\"," + fabric_mod_name.upper() + "_VERSION, utsname()->sysname,\n" - buf += " utsname()->machine);\n" - buf += " /*\n" - buf += " * Register the top level struct config_item_type with TCM core\n" - buf += " */\n" - buf += " fabric = target_fabric_configfs_init(THIS_MODULE, \"" + fabric_mod_name + "\");\n" - buf += " if (IS_ERR(fabric)) {\n" - buf += " printk(KERN_ERR \"target_fabric_configfs_init() failed\\n\");\n" - buf += " return PTR_ERR(fabric);\n" - buf += " }\n" - buf += " /*\n" - buf += " * Setup fabric->tf_ops from our local " + fabric_mod_name + "_ops\n" - buf += " */\n" - buf += " fabric->tf_ops = " + fabric_mod_name + "_ops;\n" - buf += " /*\n" - buf += " * Setup default attribute lists for various fabric->tf_cit_tmpl\n" - buf += " */\n" - buf += " fabric->tf_cit_tmpl.tfc_wwn_cit.ct_attrs = " + fabric_mod_name + "_wwn_attrs;\n" - buf += " fabric->tf_cit_tmpl.tfc_tpg_base_cit.ct_attrs = NULL;\n" - buf += " fabric->tf_cit_tmpl.tfc_tpg_attrib_cit.ct_attrs = NULL;\n" - buf += " fabric->tf_cit_tmpl.tfc_tpg_param_cit.ct_attrs = NULL;\n" - buf += " fabric->tf_cit_tmpl.tfc_tpg_np_base_cit.ct_attrs = NULL;\n" - buf += " fabric->tf_cit_tmpl.tfc_tpg_nacl_base_cit.ct_attrs = NULL;\n" - buf += " fabric->tf_cit_tmpl.tfc_tpg_nacl_attrib_cit.ct_attrs = NULL;\n" - buf += " fabric->tf_cit_tmpl.tfc_tpg_nacl_auth_cit.ct_attrs = NULL;\n" - buf += " fabric->tf_cit_tmpl.tfc_tpg_nacl_param_cit.ct_attrs = NULL;\n" - buf += " /*\n" - buf += " * Register the fabric for use within TCM\n" - buf += " */\n" - buf += " ret = target_fabric_configfs_register(fabric);\n" - buf += " if (ret < 0) {\n" - buf += " printk(KERN_ERR \"target_fabric_configfs_register() failed\"\n" - buf += " \" for " + fabric_mod_name.upper() + "\\n\");\n" - buf += " return ret;\n" - buf += " }\n" - buf += " /*\n" - buf += " * Setup our local pointer to *fabric\n" - buf += " */\n" - buf += " " + fabric_mod_name + "_fabric_configfs = fabric;\n" - buf += " printk(KERN_INFO \"" + fabric_mod_name.upper() + "[0] - Set fabric -> " + fabric_mod_name + "_fabric_configfs\\n\");\n" - buf += " return 0;\n" - buf += "};\n\n" - buf += "static void __exit " + fabric_mod_name + "_deregister_configfs(void)\n" - buf += "{\n" - buf += " if (!" + fabric_mod_name + "_fabric_configfs)\n" - buf += " return;\n\n" - buf += " target_fabric_configfs_deregister(" + fabric_mod_name + "_fabric_configfs);\n" - buf += " " + fabric_mod_name + "_fabric_configfs = NULL;\n" - buf += " printk(KERN_INFO \"" + fabric_mod_name.upper() + "[0] - Cleared " + fabric_mod_name + "_fabric_configfs\\n\");\n" + buf += "\n" + buf += " .tfc_wwn_attrs = " + fabric_mod_name + "_wwn_attrs;\n" buf += "};\n\n" buf += "static int __init " + fabric_mod_name + "_init(void)\n" buf += "{\n" - buf += " int ret;\n\n" - buf += " ret = " + fabric_mod_name + "_register_configfs();\n" - buf += " if (ret < 0)\n" - buf += " return ret;\n\n" - buf += " return 0;\n" + buf += " return target_register_template(" + fabric_mod_name + "_ops);\n" buf += "};\n\n" + buf += "static void __exit " + fabric_mod_name + "_exit(void)\n" buf += "{\n" - buf += " " + fabric_mod_name + "_deregister_configfs();\n" + buf += " target_unregister_template(" + fabric_mod_name + "_ops);\n" buf += "};\n\n" buf += "MODULE_DESCRIPTION(\"" + fabric_mod_name.upper() + " series fabric driver\");\n" diff --git a/Documentation/target/tcmu-design.txt b/Documentation/target/tcmu-design.txt index 5518465290bf5d64b3ae9b94dd5440ed0a2b97c3..263b907517ac2cd14e3b8472f4bc23f4aa8aae07 100644 --- a/Documentation/target/tcmu-design.txt +++ b/Documentation/target/tcmu-design.txt @@ -15,8 +15,7 @@ Contents: a) Discovering and configuring TCMU uio devices b) Waiting for events on the device(s) c) Managing the command ring -3) Command filtering and pass_level -4) A final note +3) A final note TCM Userspace Design @@ -138,27 +137,40 @@ signals the kernel via a 4-byte write(). When cmd_head equals cmd_tail, the ring is empty -- no commands are currently waiting to be processed by userspace. -TCMU commands start with a common header containing "len_op", a 32-bit -value that stores the length, as well as the opcode in the lowest -unused bits. Currently only two opcodes are defined, TCMU_OP_PAD and -TCMU_OP_CMD. When userspace encounters a command with PAD opcode, it -should skip ahead by the bytes in "length". (The kernel inserts PAD -entries to ensure each CMD entry fits contigously into the circular -buffer.) - -When userspace handles a CMD, it finds the SCSI CDB (Command Data -Block) via tcmu_cmd_entry.req.cdb_off. This is an offset from the -start of the overall shared memory region, not the entry. The data -in/out buffers are accessible via tht req.iov[] array. Note that -each iov.iov_base is also an offset from the start of the region. - -TCMU currently does not support BIDI operations. +TCMU commands are 8-byte aligned. They start with a common header +containing "len_op", a 32-bit value that stores the length, as well as +the opcode in the lowest unused bits. It also contains cmd_id and +flags fields for setting by the kernel (kflags) and userspace +(uflags). + +Currently only two opcodes are defined, TCMU_OP_CMD and TCMU_OP_PAD. + +When the opcode is CMD, the entry in the command ring is a struct +tcmu_cmd_entry. Userspace finds the SCSI CDB (Command Data Block) via +tcmu_cmd_entry.req.cdb_off. This is an offset from the start of the +overall shared memory region, not the entry. The data in/out buffers +are accessible via tht req.iov[] array. iov_cnt contains the number of +entries in iov[] needed to describe either the Data-In or Data-Out +buffers. For bidirectional commands, iov_cnt specifies how many iovec +entries cover the Data-Out area, and iov_bidi_count specifies how many +iovec entries immediately after that in iov[] cover the Data-In +area. Just like other fields, iov.iov_base is an offset from the start +of the region. When completing a command, userspace sets rsp.scsi_status, and rsp.sense_buffer if necessary. Userspace then increments mailbox.cmd_tail by entry.hdr.length (mod cmdr_size) and signals the kernel via the UIO method, a 4-byte write to the file descriptor. +When the opcode is PAD, userspace only updates cmd_tail as above -- +it's a no-op. (The kernel inserts PAD entries to ensure each CMD entry +is contiguous within the command ring.) + +More opcodes may be added in the future. If userspace encounters an +opcode it does not handle, it must set UNKNOWN_OP bit (bit 0) in +hdr.uflags, update cmd_tail, and proceed with processing additional +commands, if any. + The Data Area: This is shared-memory space after the command ring. The organization @@ -311,7 +323,7 @@ int handle_device_events(int fd, void *map) /* Process events from cmd ring until we catch up with cmd_head */ while (ent != (void *)mb + mb->cmdr_off + mb->cmd_head) { - if (tcmu_hdr_get_op(&ent->hdr) == TCMU_OP_CMD) { + if (tcmu_hdr_get_op(ent->hdr.len_op) == TCMU_OP_CMD) { uint8_t *cdb = (void *)mb + ent->req.cdb_off; bool success = true; @@ -326,8 +338,12 @@ int handle_device_events(int fd, void *map) ent->rsp.scsi_status = SCSI_CHECK_CONDITION; } } + else if (tcmu_hdr_get_op(ent->hdr.len_op) != TCMU_OP_PAD) { + /* Tell the kernel we didn't handle unknown opcodes */ + ent->hdr.uflags |= TCMU_UFLAG_UNKNOWN_OP; + } else { - /* Do nothing for PAD entries */ + /* Do nothing for PAD entries except update cmd_tail */ } /* update cmd_tail */ @@ -347,28 +363,6 @@ int handle_device_events(int fd, void *map) } -Command filtering and pass_level --------------------------------- - -TCMU supports a "pass_level" option with valid values of 0 or 1. When -the value is 0 (the default), nearly all SCSI commands received for -the device are passed through to the handler. This allows maximum -flexibility but increases the amount of code required by the handler, -to support all mandatory SCSI commands. If pass_level is set to 1, -then only IO-related commands are presented, and the rest are handled -by LIO's in-kernel command emulation. The commands presented at level -1 include all versions of: - -READ -WRITE -WRITE_VERIFY -XDWRITEREAD -WRITE_SAME -COMPARE_AND_WRITE -SYNCHRONIZE_CACHE -UNMAP - - A final note ------------ diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight.txt index 02361552a3eac314a68338c5638f4239ed0d28d7..77d14d51a670a523a14ec9b4581f66d720ba3e76 100644 --- a/Documentation/trace/coresight.txt +++ b/Documentation/trace/coresight.txt @@ -14,7 +14,7 @@ document is concerned with the latter. HW assisted tracing is becoming increasingly useful when dealing with systems that have many SoCs and other components like GPU and DMA engines. ARM has developed a HW assisted tracing solution by means of different components, each -being added to a design at systhesis time to cater to specific tracing needs. +being added to a design at synthesis time to cater to specific tracing needs. Compoments are generally categorised as source, link and sinks and are (usually) discovered using the AMBA bus. diff --git a/Documentation/video4linux/v4l2-controls.txt b/Documentation/video4linux/v4l2-controls.txt index 0f84ce8c9a7b1389c4c9b34fd9b5f427bdb22c40..5517db602f37b0d3f9a0939832a2494103c422de 100644 --- a/Documentation/video4linux/v4l2-controls.txt +++ b/Documentation/video4linux/v4l2-controls.txt @@ -344,7 +344,9 @@ implement g_volatile_ctrl like this: } Note that you use the 'new value' union as well in g_volatile_ctrl. In general -controls that need to implement g_volatile_ctrl are read-only controls. +controls that need to implement g_volatile_ctrl are read-only controls. If they +are not, a V4L2_EVENT_CTRL_CH_VALUE will not be generated when the control +changes. To mark a control as volatile you have to set V4L2_CTRL_FLAG_VOLATILE: diff --git a/Documentation/video4linux/v4l2-framework.txt b/Documentation/video4linux/v4l2-framework.txt index f586e29ce22110cfbe8bfcee63a20cd7ab108547..59e619f9bbf54558f69a97405100d036b09d20d6 100644 --- a/Documentation/video4linux/v4l2-framework.txt +++ b/Documentation/video4linux/v4l2-framework.txt @@ -793,8 +793,8 @@ video_register_device_no_warn() instead. Whenever a device node is created some attributes are also created for you. If you look in /sys/class/video4linux you see the devices. Go into e.g. -video0 and you will see 'name', 'debug' and 'index' attributes. The 'name' -attribute is the 'name' field of the video_device struct. The 'debug' attribute +video0 and you will see 'name', 'dev_debug' and 'index' attributes. The 'name' +attribute is the 'name' field of the video_device struct. The 'dev_debug' attribute can be used to enable core debugging. See the next section for more detailed information on this. @@ -821,7 +821,7 @@ unregister the device if the registration failed. video device debugging ---------------------- -The 'debug' attribute that is created for each video, vbi, radio or swradio +The 'dev_debug' attribute that is created for each video, vbi, radio or swradio device in /sys/class/video4linux// allows you to enable logging of file operations. diff --git a/Documentation/video4linux/vivid.txt b/Documentation/video4linux/vivid.txt index 6cfc8541a362ccb4871259f01c91bdaadb3a8aba..cd4b5a1ac529695964940701b7627396394ac4de 100644 --- a/Documentation/video4linux/vivid.txt +++ b/Documentation/video4linux/vivid.txt @@ -912,6 +912,11 @@ looped to the video input provided that: sequence and field counting in struct v4l2_buffer on the capture side may not be 100% accurate. +- field settings V4L2_FIELD_SEQ_TB/BT are not supported. While it is possible to + implement this, it would mean a lot of work to get this right. Since these + field values are rarely used the decision was made not to implement this for + now. + - on the input side the "Standard Signal Mode" for the S-Video input or the "DV Timings Signal Mode" for the HDMI input should be configured so that a valid signal is passed to the video input. diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index bc9f6fe44e27614c2f26f155385fe0d5d13d2e3b..9fa2bf8c3f6f13282c92c33671b5ad9a3eaa1d0a 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -3573,3 +3573,20 @@ struct { @ar - access register number KVM handlers should exit to userspace with rc = -EREMOTE. + + +8. Other capabilities. +---------------------- + +This section lists capabilities that give information about other +features of the KVM implementation. + +8.1 KVM_CAP_PPC_HWRNG + +Architectures: ppc + +This capability, if KVM_CHECK_EXTENSION indicates that it is +available, means that that the kernel has an implementation of the +H_RANDOM hypercall backed by a hardware random-number generator. +If present, the kernel H_RANDOM handler can be enabled for guest use +with the KVM_CAP_PPC_ENABLE_HCALL capability. diff --git a/Documentation/virtual/kvm/mmu.txt b/Documentation/virtual/kvm/mmu.txt index 53838d9c6295792501f2825175ac9c314c1a2fc7..c59bd9bc41efa984cfd5f0e17ac5fd6156acfca6 100644 --- a/Documentation/virtual/kvm/mmu.txt +++ b/Documentation/virtual/kvm/mmu.txt @@ -169,6 +169,10 @@ Shadow pages contain the following information: Contains the value of cr4.smep && !cr0.wp for which the page is valid (pages for which this is true are different from other pages; see the treatment of cr0.wp=0 below). + role.smap_andnot_wp: + Contains the value of cr4.smap && !cr0.wp for which the page is valid + (pages for which this is true are different from other pages; see the + treatment of cr0.wp=0 below). gfn: Either the guest page table containing the translations shadowed by this page, or the base page frame for linear translations. See role.direct. @@ -344,10 +348,16 @@ on fault type: (user write faults generate a #PF) -In the first case there is an additional complication if CR4.SMEP is -enabled: since we've turned the page into a kernel page, the kernel may now -execute it. We handle this by also setting spte.nx. If we get a user -fetch or read fault, we'll change spte.u=1 and spte.nx=gpte.nx back. +In the first case there are two additional complications: +- if CR4.SMEP is enabled: since we've turned the page into a kernel page, + the kernel may now execute it. We handle this by also setting spte.nx. + If we get a user fetch or read fault, we'll change spte.u=1 and + spte.nx=gpte.nx back. +- if CR4.SMAP is disabled: since the page has been changed to a kernel + page, it can not be reused when CR4.SMAP is enabled. We set + CR4.SMAP && !CR0.WP into shadow page's role to avoid this case. Note, + here we do not care the case that CR4.SMAP is enabled since KVM will + directly inject #PF to guest due to failed permission check. To prevent an spte that was converted into a kernel page with cr0.wp=0 from being written by the kernel after cr0.wp has changed to 1, we make diff --git a/Documentation/vm/pagemap.txt b/Documentation/vm/pagemap.txt index 6fbd55ef6b45379f4e92c7ee009657c3c73bcd7c..6bfbc172cdb96b437728a34eadf3e257ab456799 100644 --- a/Documentation/vm/pagemap.txt +++ b/Documentation/vm/pagemap.txt @@ -131,7 +131,8 @@ Short descriptions to the page flags: 13. SWAPCACHE page is mapped to swap space, ie. has an associated swap entry 14. SWAPBACKED page is backed by swap/RAM -The page-types tool in this directory can be used to query the above flags. +The page-types tool in the tools/vm directory can be used to query the +above flags. Using pagemap to do something useful: diff --git a/Documentation/vm/transhuge.txt b/Documentation/vm/transhuge.txt index 6b31cfbe2a9a1197b8d33d294e90bd6f64d3fcd9..8143b9e8373db41746330c468dede07acfd96b56 100644 --- a/Documentation/vm/transhuge.txt +++ b/Documentation/vm/transhuge.txt @@ -159,6 +159,17 @@ for each pass: /sys/kernel/mm/transparent_hugepage/khugepaged/full_scans +max_ptes_none specifies how many extra small pages (that are +not already mapped) can be allocated when collapsing a group +of small pages into one large page. + +/sys/kernel/mm/transparent_hugepage/khugepaged/max_ptes_none + +A higher value leads to use additional memory for programs. +A lower value leads to gain less thp performance. Value of +max_ptes_none can waste cpu time very little, you can +ignore it. + == Boot parameter == You can change the sysfs boot time defaults of Transparent Hugepage diff --git a/Documentation/zh_CN/arm64/booting.txt b/Documentation/zh_CN/arm64/booting.txt index 6f6d956ac1c9724bd47fd6a5a77d22f09fe1cd9b..7cd36af11e71c2964082dc9d37540a7566923c31 100644 --- a/Documentation/zh_CN/arm64/booting.txt +++ b/Documentation/zh_CN/arm64/booting.txt @@ -15,6 +15,8 @@ Documentation/arm64/booting.txt 的中文翻译 交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 译存在问题，请联系中文版维护者。 +本文翻译提交时的 Git 检出点为： bc465aa9d045feb0e13b4a8f32cc33c1943f62d6 + 英文版维护者： Will Deacon 中文版维护者： 傅炜 Fu Wei 中文版翻译者： 傅炜 Fu Wei @@ -88,22 +90,44 @@ AArch64 内核当前没有提供自解压代码，因此如果使用了压缩内 u32 code0; /* 可执行代码 */ u32 code1; /* 可执行代码 */ - u64 text_offset; /* 映像装载偏移 */ - u64 res0 = 0; /* 保留 */ - u64 res1 = 0; /* 保留 */ + u64 text_offset; /* 映像装载偏移，小端模式 */ + u64 image_size; /* 映像实际大小, 小端模式 */ + u64 flags; /* 内核旗标, 小端模式 * u64 res2 = 0; /* 保留 */ u64 res3 = 0; /* 保留 */ u64 res4 = 0; /* 保留 */ u32 magic = 0x644d5241; /* 魔数, 小端, "ARM\x64" */ - u32 res5 = 0; /* 保留 */ + u32 res5; /* 保留 （用于 PE COFF 偏移） */ 映像头注释： +- 自 v3.17 起，除非另有说明，所有域都是小端模式。 + - code0/code1 负责跳转到 stext. -映像必须位于系统 RAM 起始处的特定偏移（当前是 0x80000）。系统 RAM -的起始地址必须是以 2MB 对齐的。 +- 当通过 EFI 启动时， 最初 code0/code1 被跳过。 + res5 是到 PE 文件头的偏移，而 PE 文件头含有 EFI 的启动入口点 （efi_stub_entry）。 + 当 stub 代码完成了它的使命，它会跳转到 code0 继续正常的启动流程。 + +- v3.17 之前，未明确指定 text_offset 的字节序。此时，image_size 为零， + 且 text_offset 依照内核字节序为 0x80000。 + 当 image_size 非零，text_offset 为小端模式且是有效值，应被引导加载程序使用。 + 当 image_size 为零，text_offset 可假定为 0x80000。 + +- flags 域 (v3.17 引入) 为 64 位小端模式，其编码如下： + 位 0: 内核字节序。 1 表示大端模式，0 表示小端模式。 + 位 1-63: 保留。 + +- 当 image_size 为零时，引导装载程序应该试图在内核映像末尾之后尽可能多地保留空闲内存 + 供内核直接使用。对内存空间的需求量因所选定的内核特性而异, 且无实际限制。 + +内核映像必须被放置在靠近可用系统内存起始的 2MB 对齐为基址的 text_offset 字节处，并从那里被调用。 +当前，对 Linux 来说在此基址以下的内存是无法使用的，因此强烈建议将系统内存的起始作为这个基址。 +从映像起始地址算起，最少必须为内核释放出 image_size 字节的空间。 + +任何提供给内核的内存（甚至在 2MB 对齐的基地址之前），若未从内核中标记为保留 +(如在设备树（dtb）的 memreserve 区域），都将被认为对内核是可用。 在跳转入内核前，必须符合以下状态： @@ -124,8 +148,12 @@ AArch64 内核当前没有提供自解压代码，因此如果使用了压缩内 - 高速缓存、MMU MMU 必须关闭。 指令缓存开启或关闭都可以。 - 数据缓存必须关闭且无效。 - 外部高速缓存（如果存在）必须配置并禁用。 + 已载入的内核映像的相应内存区必须被清理，以达到缓存一致性点（PoC）。 + 当存在系统缓存或其他使能缓存的一致性主控器时，通常需使用虚拟地址维护其缓存，而非 set/way 操作。 + 遵从通过虚拟地址操作维护构架缓存的系统缓存必须被配置，并可以被使能。 + 而不通过虚拟地址操作维护构架缓存的系统缓存（不推荐），必须被配置且禁用。 + + *译者注：对于 PoC 以及缓存相关内容，请参考 ARMv8 构架参考手册 ARM DDI 0487A - 架构计时器 CNTFRQ 必须设定为计时器的频率，且 CNTVOFF 必须设定为对所有 CPU @@ -141,6 +169,14 @@ AArch64 内核当前没有提供自解压代码，因此如果使用了压缩内 在进入内核映像的异常级中，所有构架中可写的系统寄存器必须通过软件 在一个更高的异常级别下初始化，以防止在 未知 状态下运行。 + 对于拥有 GICv3 中断控制器的系统： + - 若当前在 EL3 ： + ICC_SRE_EL3.Enable (位 3) 必须初始化为 0b1。 + ICC_SRE_EL3.SRE (位 0) 必须初始化为 0b1。 + - 若内核运行在 EL1： + ICC_SRE_EL2.Enable (位 3) 必须初始化为 0b1。 + ICC_SRE_EL2.SRE (位 0) 必须初始化为 0b1。 + 以上对于 CPU 模式、高速缓存、MMU、架构计时器、一致性、系统寄存器的 必要条件描述适用于所有 CPU。所有 CPU 必须在同一异常级别跳入内核。 @@ -170,7 +206,7 @@ AArch64 内核当前没有提供自解压代码，因此如果使用了压缩内 ARM DEN 0022A：用于 ARM 上的电源状态协调接口系统软件）中描述的 CPU_ON 调用来将 CPU 带入内核。 - *译者注:到文档翻译时，此文档已更新为 ARM DEN 0022B。 + *译者注: ARM DEN 0022A 已更新到 ARM DEN 0022C。 设备树必须包含一个 ‘psci’ 节点，请参考以下文档： Documentation/devicetree/bindings/arm/psci.txt diff --git a/Documentation/zh_CN/arm64/legacy_instructions.txt b/Documentation/zh_CN/arm64/legacy_instructions.txt new file mode 100644 index 0000000000000000000000000000000000000000..68362a1ab7179a6ed0d3346c3a74d206d515485f --- /dev/null +++ b/Documentation/zh_CN/arm64/legacy_instructions.txt @@ -0,0 +1,72 @@ +Chinese translated version of Documentation/arm64/legacy_instructions.txt + +If you have any comment or update to the content, please contact the +original document maintainer directly. However, if you have a problem +communicating in English you can also ask the Chinese maintainer for +help. Contact the Chinese maintainer if this translation is outdated +or if there is a problem with the translation. + +Maintainer: Punit Agrawal + Suzuki K. Poulose +Chinese maintainer: Fu Wei +--------------------------------------------------------------------- +Documentation/arm64/legacy_instructions.txt 的中文翻译 + +如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 +交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 +译存在问题，请联系中文版维护者。 + +本文翻译提交时的 Git 检出点为： bc465aa9d045feb0e13b4a8f32cc33c1943f62d6 + +英文版维护者： Punit Agrawal + Suzuki K. Poulose +中文版维护者： 傅炜 Fu Wei +中文版翻译者： 傅炜 Fu Wei +中文版校译者： 傅炜 Fu Wei + +以下为正文 +--------------------------------------------------------------------- +Linux 内核在 arm64 上的移植提供了一个基础框架，以支持构架中正在被淘汰或已废弃指令的模拟执行。 +这个基础框架的代码使用未定义指令钩子（hooks）来支持模拟。如果指令存在，它也允许在硬件中启用该指令。 + +模拟模式可通过写 sysctl 节点（/proc/sys/abi）来控制。 +不同的执行方式及 sysctl 节点的相应值，解释如下： + +* Undef（未定义） + 值： 0 + 产生未定义指令终止异常。它是那些构架中已废弃的指令，如 SWP，的默认处理方式。 + +* Emulate（模拟） + 值： 1 + 使用软件模拟方式。为解决软件迁移问题，这种模拟指令模式的使用是被跟踪的，并会发出速率限制警告。 + 它是那些构架中正在被淘汰的指令，如 CP15 barriers（隔离指令），的默认处理方式。 + +* Hardware Execution（硬件执行） + 值： 2 + 虽然标记为正在被淘汰，但一些实现可能提供硬件执行这些指令的使能/禁用操作。 + 使用硬件执行一般会有更好的性能，但将无法收集运行时对正被淘汰指令的使用统计数据。 + +默认执行模式依赖于指令在构架中状态。正在被淘汰的指令应该以模拟（Emulate）作为默认模式， +而已废弃的指令必须默认使用未定义（Undef）模式 + +注意：指令模拟可能无法应对所有情况。更多详情请参考单独的指令注释。 + +受支持的遗留指令 +------------- +* SWP{B} +节点: /proc/sys/abi/swp +状态: 已废弃 +默认执行方式: Undef (0) + +* CP15 Barriers +节点: /proc/sys/abi/cp15_barrier +状态: 正被淘汰，不推荐使用 +默认执行方式: Emulate (1) + +* SETEND +节点: /proc/sys/abi/setend +状态: 正被淘汰，不推荐使用 +默认执行方式: Emulate (1)* +注：为了使能这个特性，系统中的所有 CPU 必须在 EL0 支持混合字节序。 +如果一个新的 CPU （不支持混合字节序） 在使能这个特性后被热插入系统， +在应用中可能会出现不可预期的结果。 diff --git a/Documentation/zh_CN/arm64/memory.txt b/Documentation/zh_CN/arm64/memory.txt index a782704c1cb59ab868de82d573291ac8780f6297..19b3a52d5d9479178604a0d73666c27a2ff17f07 100644 --- a/Documentation/zh_CN/arm64/memory.txt +++ b/Documentation/zh_CN/arm64/memory.txt @@ -15,6 +15,8 @@ Documentation/arm64/memory.txt 的中文翻译 交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 译存在问题，请联系中文版维护者。 +本文翻译提交时的 Git 检出点为： bc465aa9d045feb0e13b4a8f32cc33c1943f62d6 + 英文版维护者： Catalin Marinas 中文版维护者： 傅炜 Fu Wei 中文版翻译者： 傅炜 Fu Wei @@ -26,69 +28,53 @@ Documentation/arm64/memory.txt 的中文翻译 =========================== 作者: Catalin Marinas -日期: 2012 年 02 月 20 日 本文档描述 AArch64 Linux 内核所使用的虚拟内存布局。此构架可以实现 页大小为 4KB 的 4 级转换表和页大小为 64KB 的 3 级转换表。 -AArch64 Linux 使用页大小为 4KB 的 3 级转换表配置，对于用户和内核 -都有 39-bit (512GB) 的虚拟地址空间。对于页大小为 64KB的配置，仅 -使用 2 级转换表，但内存布局相同。 +AArch64 Linux 使用 3 级或 4 级转换表，其页大小配置为 4KB，对于用户和内核 +分别都有 39-bit (512GB) 或 48-bit (256TB) 的虚拟地址空间。 +对于页大小为 64KB的配置，仅使用 2 级转换表，有 42-bit (4TB) 的虚拟地址空间，但内存布局相同。 -用户地址空间的 63:39 位为 0，而内核地址空间的相应位为 1。TTBRx 的 +用户地址空间的 63:48 位为 0，而内核地址空间的相应位为 1。TTBRx 的 选择由虚拟地址的 63 位给出。swapper_pg_dir 仅包含内核（全局）映射， -而用户 pgd 仅包含用户（非全局）映射。swapper_pgd_dir 地址被写入 +而用户 pgd 仅包含用户（非全局）映射。swapper_pg_dir 地址被写入 TTBR1 中，且从不写入 TTBR0。 -AArch64 Linux 在页大小为 4KB 时的内存布局： +AArch64 Linux 在页大小为 4KB，并使用 3 级转换表时的内存布局： 起始地址 结束地址 大小 用途 ----------------------------------------------------------------------- 0000000000000000 0000007fffffffff 512GB 用户空间 +ffffff8000000000 ffffffffffffffff 512GB 内核空间 -ffffff8000000000 ffffffbbfffeffff ~240GB vmalloc - -ffffffbbffff0000 ffffffbbffffffff 64KB [防护页] - -ffffffbc00000000 ffffffbdffffffff 8GB vmemmap - -ffffffbe00000000 ffffffbffbbfffff ~8GB [防护页，未来用于 vmmemap] -ffffffbffbc00000 ffffffbffbdfffff 2MB earlyprintk 设备 +AArch64 Linux 在页大小为 4KB，并使用 4 级转换表时的内存布局： -ffffffbffbe00000 ffffffbffbe0ffff 64KB PCI I/O 空间 - -ffffffbffbe10000 ffffffbcffffffff ~2MB [防护页] - -ffffffbffc000000 ffffffbfffffffff 64MB 模块 - -ffffffc000000000 ffffffffffffffff 256GB 内核逻辑内存映射 +起始地址 结束地址 大小 用途 +----------------------------------------------------------------------- +0000000000000000 0000ffffffffffff 256TB 用户空间 +ffff000000000000 ffffffffffffffff 256TB 内核空间 -AArch64 Linux 在页大小为 64KB 时的内存布局： +AArch64 Linux 在页大小为 64KB，并使用 2 级转换表时的内存布局： 起始地址 结束地址 大小 用途 ----------------------------------------------------------------------- 0000000000000000 000003ffffffffff 4TB 用户空间 +fffffc0000000000 ffffffffffffffff 4TB 内核空间 -fffffc0000000000 fffffdfbfffeffff ~2TB vmalloc - -fffffdfbffff0000 fffffdfbffffffff 64KB [防护页] - -fffffdfc00000000 fffffdfdffffffff 8GB vmemmap - -fffffdfe00000000 fffffdfffbbfffff ~8GB [防护页，未来用于 vmmemap] -fffffdfffbc00000 fffffdfffbdfffff 2MB earlyprintk 设备 +AArch64 Linux 在页大小为 64KB，并使用 3 级转换表时的内存布局： -fffffdfffbe00000 fffffdfffbe0ffff 64KB PCI I/O 空间 - -fffffdfffbe10000 fffffdfffbffffff ~2MB [防护页] +起始地址 结束地址 大小 用途 +----------------------------------------------------------------------- +0000000000000000 0000ffffffffffff 256TB 用户空间 +ffff000000000000 ffffffffffffffff 256TB 内核空间 -fffffdfffc000000 fffffdffffffffff 64MB 模块 -fffffe0000000000 ffffffffffffffff 2TB 内核逻辑内存映射 +更详细的内核虚拟内存布局，请参阅内核启动信息。 4KB 页大小的转换表查找： @@ -102,7 +88,7 @@ fffffe0000000000 ffffffffffffffff 2TB 内核逻辑内存映射 | | | | +-> [20:12] L3 索引 | | | +-----------> [29:21] L2 索引 | | +---------------------> [38:30] L1 索引 - | +-------------------------------> [47:39] L0 索引 (未使用) + | +-------------------------------> [47:39] L0 索引 +-------------------------------------------------> [63] TTBR0/1 @@ -115,10 +101,11 @@ fffffe0000000000 ffffffffffffffff 2TB 内核逻辑内存映射 | | | | v | | | | [15:0] 页内偏移 | | | +----------> [28:16] L3 索引 - | | +--------------------------> [41:29] L2 索引 (仅使用 38:29 ) - | +-------------------------------> [47:42] L1 索引 (未使用) + | | +--------------------------> [41:29] L2 索引 + | +-------------------------------> [47:42] L1 索引 +-------------------------------------------------> [63] TTBR0/1 + 当使用 KVM 时, 管理程序（hypervisor）在 EL2 中通过相对内核虚拟地址的 一个固定偏移来映射内核页（内核虚拟地址的高 24 位设为零）: diff --git a/MAINTAINERS b/MAINTAINERS index f7bbaece56498fcc75b722c042c9a1678a629b81..5bb0b9e3059f8ed3526133a774495c33da17a6b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -51,9 +51,9 @@ trivial patch so apply some common sense. or does something very odd once a month document it. PLEASE remember that submissions must be made under the terms - of the OSDL certificate of contribution and should include a - Signed-off-by: line. The current version of this "Developer's - Certificate of Origin" (DCO) is listed in the file + of the Linux Foundation certificate of contribution and should + include a Signed-off-by: line. The current version of this + "Developer's Certificate of Origin" (DCO) is listed in the file Documentation/SubmittingPatches. 6. Make sure you have the right to send any changes you make. If you @@ -569,6 +569,12 @@ L: nios2-dev@lists.rocketboards.org (moderated for non-subscribers) S: Maintained F: drivers/mailbox/mailbox-altera.c +ALTERA PIO DRIVER +M: Tien Hock Loh +L: linux-gpio@vger.kernel.org +S: Maintained +F: drivers/gpio/gpio-altera.c + ALTERA TRIPLE SPEED ETHERNET DRIVER M: Vince Bridgers L: netdev@vger.kernel.org @@ -646,7 +652,6 @@ M: Tom Lendacky L: netdev@vger.kernel.org S: Supported F: drivers/net/ethernet/amd/xgbe/ -F: drivers/net/phy/amd-xgbe-phy.c AMS (Apple Motion Sensor) DRIVER M: Michael Hanselmann @@ -880,12 +885,16 @@ S: Maintained F: drivers/media/rc/meson-ir.c N: meson[x68] +ARM/Annapurna Labs ALPINE ARCHITECTURE +M: Tsahee Zidenberg +S: Maintained +F: arch/arm/mach-alpine/ + ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES -M: Andrew Victor M: Nicolas Ferre +M: Alexandre Belloni M: Jean-Christophe Plagniol-Villard L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -W: http://maxim.org.za/at91_26.html W: http://www.linux4sam.org S: Supported F: arch/arm/mach-at91/ @@ -912,6 +921,13 @@ M: Krzysztof Halasa S: Maintained F: arch/arm/mach-cns3xxx/ +ARM/CAVIUM THUNDER NETWORK DRIVER +M: Sunil Goutham +M: Robert Richter +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: drivers/net/ethernet/cavium/ + ARM/CIRRUS LOGIC CLPS711X ARM ARCHITECTURE M: Alexander Shiyan L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -952,7 +968,7 @@ ARM/CORESIGHT FRAMEWORK AND DRIVERS M: Mathieu Poirier L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: drivers/coresight/* +F: drivers/hwtracing/coresight/* F: Documentation/trace/coresight.txt F: Documentation/devicetree/bindings/arm/coresight.txt F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* @@ -964,7 +980,7 @@ S: Maintained ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE M: Hans Ulli Kroll L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -T: git git://git.berlios.de/gemini-board +T: git git://github.com/ulli-kroll/linux.git S: Maintained F: arch/arm/mach-gemini/ @@ -979,6 +995,12 @@ F: drivers/clocksource/timer-prima2.c F: drivers/clocksource/timer-atlas7.c N: [^a-z]sirf +ARM/CONEXANT DIGICOLOR MACHINE SUPPORT +M: Baruch Siach +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +N: digicolor + ARM/EBSA110 MACHINE SUPPORT M: Russell King L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -1177,7 +1199,7 @@ ARM/MAGICIAN MACHINE SUPPORT M: Philipp Zabel S: Maintained -ARM/Marvell Armada 370 and Armada XP SOC support +ARM/Marvell Kirkwood and Armada 370, 375, 38x, XP SOC support M: Jason Cooper M: Andrew Lunn M: Gregory Clement @@ -1186,12 +1208,17 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-mvebu/ F: drivers/rtc/rtc-armada38x.c +F: arch/arm/boot/dts/armada* +F: arch/arm/boot/dts/kirkwood* + ARM/Marvell Berlin SoC support M: Sebastian Hesselbarth L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-berlin/ +F: arch/arm/boot/dts/berlin* + ARM/Marvell Dove/MV78xx0/Orion SOC support M: Jason Cooper @@ -1204,6 +1231,9 @@ F: arch/arm/mach-dove/ F: arch/arm/mach-mv78xx0/ F: arch/arm/mach-orion5x/ F: arch/arm/plat-orion/ +F: arch/arm/boot/dts/dove* +F: arch/arm/boot/dts/orion5x* + ARM/Orion SoC/Technologic Systems TS-78xx platform support M: Alexander Clouter @@ -1255,22 +1285,6 @@ L: openmoko-kernel@lists.openmoko.org (subscribers-only) W: http://wiki.openmoko.org/wiki/Neo_FreeRunner S: Supported -ARM/QUALCOMM MSM MACHINE SUPPORT -M: David Brown -M: Daniel Walker -M: Bryan Huntsman -L: linux-arm-msm@vger.kernel.org -F: arch/arm/mach-msm/ -F: drivers/video/fbdev/msm/ -F: drivers/mmc/host/msm_sdcc.c -F: drivers/mmc/host/msm_sdcc.h -F: drivers/tty/serial/msm_serial.h -F: drivers/tty/serial/msm_serial.c -F: drivers/*/pm8???-* -F: drivers/mfd/ssbi.c -T: git git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm.git -S: Maintained - ARM/TOSA MACHINE SUPPORT M: Dmitry Eremin-Solenikov M: Dirk Opfer @@ -1328,6 +1342,11 @@ L: linux-soc@vger.kernel.org S: Maintained F: arch/arm/mach-qcom/ F: drivers/soc/qcom/ +F: drivers/tty/serial/msm_serial.h +F: drivers/tty/serial/msm_serial.c +F: drivers/*/pm8???-* +F: drivers/mfd/ssbi.c +F: drivers/firmware/qcom_scm.c T: git git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git ARM/RADISYS ENP2611 MACHINE SUPPORT @@ -1366,6 +1385,7 @@ N: rockchip ARM/SAMSUNG EXYNOS ARM ARCHITECTURES M: Kukjin Kim +M: Krzysztof Kozlowski L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) S: Maintained @@ -1426,11 +1446,9 @@ F: arch/arm/boot/dts/emev2* F: arch/arm/boot/dts/r7s* F: arch/arm/boot/dts/r8a* F: arch/arm/boot/dts/sh* -F: arch/arm/configs/ape6evm_defconfig F: arch/arm/configs/armadillo800eva_defconfig F: arch/arm/configs/bockw_defconfig F: arch/arm/configs/kzm9g_defconfig -F: arch/arm/configs/mackerel_defconfig F: arch/arm/configs/marzen_defconfig F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S @@ -1441,9 +1459,10 @@ ARM/SOCFPGA ARCHITECTURE M: Dinh Nguyen S: Maintained F: arch/arm/mach-socfpga/ +F: arch/arm/boot/dts/socfpga* +F: arch/arm/configs/socfpga_defconfig W: http://www.rocketboards.org -T: git://git.rocketboards.org/linux-socfpga.git -T: git://git.rocketboards.org/linux-socfpga-next.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT M: Dinh Nguyen @@ -1822,7 +1841,7 @@ S: Supported F: drivers/spi/spi-atmel.* ATMEL SSC DRIVER -M: Bo Shen +M: Nicolas Ferre L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported F: drivers/misc/atmel-ssc.c @@ -1931,7 +1950,7 @@ S: Maintained F: drivers/net/wireless/b43legacy/ BACKLIGHT CLASS/SUBSYSTEM -M: Jingoo Han +M: Jingoo Han M: Lee Jones S: Maintained F: drivers/video/backlight/ @@ -2118,8 +2137,9 @@ S: Supported F: drivers/net/ethernet/broadcom/bnx2x/ BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE -M: Christian Daudt M: Florian Fainelli +M: Ray Jui +M: Scott Branden L: bcm-kernel-feedback-list@broadcom.com T: git git://github.com/broadcom/mach-bcm S: Maintained @@ -2170,7 +2190,6 @@ S: Maintained F: drivers/usb/gadget/udc/bcm63xx_udc.* BROADCOM BCM7XXX ARM ARCHITECTURE -M: Marc Carino M: Brian Norris M: Gregory Fong M: Florian Fainelli @@ -2414,7 +2433,6 @@ L: linux-security-module@vger.kernel.org S: Supported F: include/linux/capability.h F: include/uapi/linux/capability.h -F: security/capability.c F: security/commoncap.c F: kernel/capability.c @@ -2571,6 +2589,7 @@ F: include/linux/cleancache.h CLK API M: Russell King +L: linux-clk@vger.kernel.org S: Maintained F: include/linux/clk.h @@ -2631,7 +2650,7 @@ F: drivers/media/platform/coda/ COMMON CLK FRAMEWORK M: Mike Turquette M: Stephen Boyd -L: linux-kernel@vger.kernel.org +L: linux-clk@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git S: Maintained F: drivers/clk/ @@ -3067,10 +3086,16 @@ F: drivers/net/fddi/defxx.* DELL LAPTOP DRIVER M: Matthew Garrett +M: Pali Rohár L: platform-driver-x86@vger.kernel.org S: Maintained F: drivers/platform/x86/dell-laptop.c +DELL LAPTOP FREEFALL DRIVER +M: Pali Rohár +S: Maintained +F: drivers/platform/x86/dell-smo8800.c + DELL LAPTOP SMM DRIVER M: Guenter Roeck S: Maintained @@ -3085,6 +3110,7 @@ F: drivers/firmware/dcdbas.* DELL WMI EXTRAS DRIVER M: Matthew Garrett +M: Pali Rohár S: Maintained F: drivers/platform/x86/dell-wmi.c @@ -3272,12 +3298,6 @@ F: drivers/firmware/dmi-id.c F: drivers/firmware/dmi_scan.c F: include/linux/dmi.h -DOCKING STATION DRIVER -M: Shaohua Li -L: linux-acpi@vger.kernel.org -S: Supported -F: drivers/acpi/dock.c - DOCUMENTATION M: Jonathan Corbet L: linux-doc@vger.kernel.org @@ -3285,7 +3305,9 @@ S: Maintained F: Documentation/ X: Documentation/ABI/ X: Documentation/devicetree/ -X: Documentation/[a-z][a-z]_[A-Z][A-Z]/ +X: Documentation/acpi +X: Documentation/power +X: Documentation/spi T: git git://git.lwn.net/linux-2.6.git docs-next DOUBLETALK DRIVER @@ -3409,9 +3431,15 @@ T: git git://people.freedesktop.org/~airlied/linux S: Supported F: drivers/gpu/drm/rcar-du/ F: drivers/gpu/drm/shmobile/ -F: include/linux/platform_data/rcar-du.h F: include/linux/platform_data/shmob_drm.h +DRM DRIVERS FOR ROCKCHIP +M: Mark Yao +L: dri-devel@lists.freedesktop.org +S: Maintained +F: drivers/gpu/drm/rockchip/ +F: Documentation/devicetree/bindings/video/rockchip* + DSBR100 USB FM RADIO DRIVER M: Alexey Klimov L: linux-media@vger.kernel.org @@ -3802,10 +3830,11 @@ M: David Woodhouse L: linux-embedded@vger.kernel.org S: Maintained -EMULEX LPFC FC SCSI DRIVER -M: James Smart +EMULEX/AVAGO LPFC FC/FCOE SCSI DRIVER +M: James Smart +M: Dick Kennedy L: linux-scsi@vger.kernel.org -W: http://sourceforge.net/projects/lpfcxxxx +W: http://www.avagotech.com S: Supported F: drivers/scsi/lpfc/ @@ -3904,7 +3933,7 @@ F: drivers/extcon/ F: Documentation/extcon/ EXYNOS DP DRIVER -M: Jingoo Han +M: Jingoo Han L: dri-devel@lists.freedesktop.org S: Maintained F: drivers/gpu/drm/exynos/exynos_dp* @@ -4363,11 +4392,10 @@ F: fs/gfs2/ F: include/uapi/linux/gfs2_ondisk.h GIGASET ISDN DRIVERS -M: Hansjoerg Lipp -M: Tilman Schmidt +M: Paul Bolle L: gigaset307x-common@lists.sourceforge.net W: http://gigaset307x.sourceforge.net/ -S: Maintained +S: Odd Fixes F: Documentation/isdn/README.gigaset F: drivers/isdn/gigaset/ F: include/uapi/linux/gigaset_dev.h @@ -4466,7 +4494,7 @@ S: Maintained F: block/partitions/efi.* STK1160 USB VIDEO CAPTURE DRIVER -M: Ezequiel Garcia +M: Ezequiel Garcia L: linux-media@vger.kernel.org T: git git://linuxtv.org/media_tree.git S: Maintained @@ -4514,7 +4542,7 @@ M: Jean Delvare M: Guenter Roeck L: lm-sensors@lm-sensors.org W: http://www.lm-sensors.org/ -T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/ +T: quilt http://jdelvare.nerim.net/devel/linux/jdelvare-hwmon/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git S: Maintained F: Documentation/hwmon/ @@ -5009,6 +5037,11 @@ W: http://industrypack.sourceforge.net S: Maintained F: drivers/ipack/ +INGENIC JZ4780 DMA Driver +M: Zubair Lutfullah Kakakhel +S: Maintained +F: drivers/dma/dma-jz4780.c + INTEGRITY MEASUREMENT ARCHITECTURE (IMA) M: Mimi Zohar M: Dmitry Kasatkin @@ -5029,17 +5062,19 @@ S: Orphan F: drivers/video/fbdev/imsttfb.c INFINIBAND SUBSYSTEM -M: Roland Dreier +M: Doug Ledford M: Sean Hefty M: Hal Rosenstock L: linux-rdma@vger.kernel.org W: http://www.openfabrics.org/ Q: http://patchwork.kernel.org/project/linux-rdma/list/ -T: git git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma.git S: Supported F: Documentation/infiniband/ F: drivers/infiniband/ F: include/uapi/linux/if_infiniband.h +F: include/uapi/rdma/ +F: include/rdma/ INOTIFY M: John McCutchan @@ -5792,6 +5827,7 @@ F: drivers/scsi/53c700* LED SUBSYSTEM M: Bryan Wu M: Richard Purdie +M: Jacek Anaszewski L: linux-leds@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds.git S: Maintained @@ -6158,16 +6194,6 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/ S: Maintained F: drivers/media/dvb-frontends/m88rs2000* -M88TS2022 MEDIA DRIVER -M: Antti Palosaari -L: linux-media@vger.kernel.org -W: http://linuxtv.org/ -W: http://palosaari.fi/linux/ -Q: http://patchwork.linuxtv.org/project/linux-media/list/ -T: git git://linuxtv.org/anttip/media_tree.git -S: Maintained -F: drivers/media/tuners/m88ts2022* - MA901 MASTERKIT USB FM RADIO DRIVER M: Alexey Klimov L: linux-media@vger.kernel.org @@ -6346,6 +6372,12 @@ F: include/uapi/linux/meye.h F: include/uapi/linux/ivtv* F: include/uapi/linux/uvcvideo.h +MEDIATEK MT7601U WIRELESS LAN DRIVER +M: Jakub Kicinski +L: linux-wireless@vger.kernel.org +S: Maintained +F: drivers/net/wireless/mediatek/mt7601u/ + MEGARAID SCSI/SAS DRIVERS M: Kashyap Desai M: Sumit Saxena @@ -6591,6 +6623,7 @@ M: Laurent Pinchart L: linux-media@vger.kernel.org T: git git://linuxtv.org/media_tree.git S: Maintained +F: Documentation/devicetree/bindings/media/i2c/mt9v032.txt F: drivers/media/i2c/mt9v032.c F: include/media/mt9v032.h @@ -6946,6 +6979,17 @@ T: git git://git.rocketboards.org/linux-socfpga-next.git S: Maintained F: arch/nios2/ +NOKIA N900 POWER SUPPLY DRIVERS +M: Pali Rohár +S: Maintained +F: include/linux/power/bq2415x_charger.h +F: include/linux/power/bq27x00_battery.h +F: include/linux/power/isp1704_charger.h +F: drivers/power/bq2415x_charger.c +F: drivers/power/bq27x00_battery.c +F: drivers/power/isp1704_charger.c +F: drivers/power/rx51_battery.c + NTB DRIVER M: Jon Mason M: Dave Jiang @@ -7008,6 +7052,8 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git S: Maintained F: arch/arm/*omap*/ +F: arch/arm/configs/omap1_defconfig +F: arch/arm/configs/omap2plus_defconfig F: drivers/i2c/busses/i2c-omap.c F: drivers/irqchip/irq-omap-intc.c F: drivers/mfd/*omap*.c @@ -7138,6 +7184,7 @@ OMAP IMAGING SUBSYSTEM (OMAP3 ISP and OMAP4 ISS) M: Laurent Pinchart L: linux-media@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/media/ti,omap3isp.txt F: drivers/media/platform/omap3isp/ F: drivers/staging/media/omap4iss/ @@ -7237,6 +7284,15 @@ F: Documentation/devicetree/ F: arch/*/boot/dts/ F: include/dt-bindings/ +OPEN FIRMWARE AND DEVICE TREE OVERLAYS +M: Pantelis Antoniou +L: devicetree@vger.kernel.org +S: Maintained +F: Documentation/devicetree/dynamic-resolution-notes.txt +F: Documentation/devicetree/overlay-notes.txt +F: drivers/of/overlay.c +F: drivers/of/resolver.c + OPENRISC ARCHITECTURE M: Jonas Bonn W: http://openrisc.net @@ -7522,7 +7578,7 @@ S: Maintained F: drivers/pci/host/*rcar* PCI DRIVER FOR SAMSUNG EXYNOS -M: Jingoo Han +M: Jingoo Han L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) @@ -7530,8 +7586,8 @@ S: Maintained F: drivers/pci/host/pci-exynos.c PCI DRIVER FOR SYNOPSIS DESIGNWARE -M: Mohit Kumar -M: Jingoo Han +M: Jingoo Han +M: Pratyush Anand L: linux-pci@vger.kernel.org S: Maintained F: drivers/pci/host/*designware* @@ -7545,7 +7601,7 @@ F: Documentation/devicetree/bindings/pci/host-generic-pci.txt F: drivers/pci/host/pci-host-generic.c PCIE DRIVER FOR ST SPEAR13XX -M: Mohit Kumar +M: Pratyush Anand L: linux-pci@vger.kernel.org S: Maintained F: drivers/pci/host/*spear* @@ -8113,6 +8169,12 @@ S: Maintained F: Documentation/blockdev/ramdisk.txt F: drivers/block/brd.c +PERSISTENT MEMORY DRIVER +M: Ross Zwisler +L: linux-nvdimm@lists.01.org +S: Supported +F: drivers/block/pmem.c + RANDOM NUMBER DRIVER M: "Theodore Ts'o" S: Maintained @@ -8482,7 +8544,7 @@ S: Supported F: sound/soc/samsung/ SAMSUNG FRAMEBUFFER DRIVER -M: Jingoo Han +M: Jingoo Han L: linux-fbdev@vger.kernel.org S: Maintained F: drivers/video/fbdev/s3c-fb.c @@ -8781,21 +8843,33 @@ F: drivers/misc/phantom.c F: include/uapi/linux/phantom.h SERVER ENGINES 10Gbps iSCSI - BladeEngine 2 DRIVER -M: Jayamohan Kallickal +M: Jayamohan Kallickal +M: Minh Tran +M: John Soni Jose L: linux-scsi@vger.kernel.org -W: http://www.emulex.com +W: http://www.avagotech.com S: Supported F: drivers/scsi/be2iscsi/ -SERVER ENGINES 10Gbps NIC - BladeEngine 2 DRIVER -M: Sathya Perla -M: Subbu Seetharaman -M: Ajit Khaparde +Emulex 10Gbps NIC BE2, BE3-R, Lancer, Skyhawk-R DRIVER +M: Sathya Perla +M: Ajit Khaparde +M: Padmanabh Ratnakar +M: Sriharsha Basavapatna L: netdev@vger.kernel.org W: http://www.emulex.com S: Supported F: drivers/net/ethernet/emulex/benet/ +EMULEX ONECONNECT ROCE DRIVER +M: Selvin Xavier +M: Devesh Sharma +M: Mitesh Ahuja +L: linux-rdma@vger.kernel.org +W: http://www.emulex.com +S: Supported +F: drivers/infiniband/hw/ocrdma/ + SFC NETWORK DRIVER M: Solarflare linux maintainers M: Shradha Shah @@ -8969,6 +9043,16 @@ T: git git://linuxtv.org/mhadli/v4l-dvb-davinci_devices.git S: Maintained F: drivers/media/platform/am437x/ +OV2659 OMNIVISION SENSOR DRIVER +M: Lad, Prabhakar +L: linux-media@vger.kernel.org +W: http://linuxtv.org/ +Q: http://patchwork.linuxtv.org/project/linux-media/list/ +T: git git://linuxtv.org/mhadli/v4l-dvb-davinci_devices.git +S: Maintained +F: drivers/media/i2c/ov2659.c +F: include/media/ov2659.h + SIS 190 ETHERNET DRIVER M: Francois Romieu L: netdev@vger.kernel.org @@ -9918,10 +10002,23 @@ S: Maintained F: drivers/platform/x86/topstar-laptop.c TOSHIBA ACPI EXTRAS DRIVER +M: Azael Avalos L: platform-driver-x86@vger.kernel.org -S: Orphan +S: Maintained F: drivers/platform/x86/toshiba_acpi.c +TOSHIBA BLUETOOTH DRIVER +M: Azael Avalos +L: platform-driver-x86@vger.kernel.org +S: Maintained +F: drivers/platform/x86/toshiba_bluetooth.c + +TOSHIBA HDD ACTIVE PROTECTION SENSOR DRIVER +M: Azael Avalos +L: platform-driver-x86@vger.kernel.org +S: Maintained +F: drivers/platform/x86/toshiba_haps.c + TOSHIBA SMM DRIVER M: Jonathan Buzzard L: tlinux-users@tce.toshiba-dme.co.jp @@ -10478,7 +10575,6 @@ F: include/linux/virtio_console.h F: include/uapi/linux/virtio_console.h VIRTIO CORE, NET AND BLOCK DRIVERS -M: Rusty Russell M: "Michael S. Tsirkin" L: virtualization@lists.linux-foundation.org S: Maintained @@ -10498,9 +10594,14 @@ S: Maintained F: drivers/vhost/ F: include/uapi/linux/vhost.h -VIA RHINE NETWORK DRIVER -M: Roger Luethi +VIRTIO INPUT DRIVER +M: Gerd Hoffmann S: Maintained +F: drivers/virtio/virtio_input.c +F: include/uapi/linux/virtio_input.h + +VIA RHINE NETWORK DRIVER +S: Orphan F: drivers/net/ethernet/via/via-rhine.c VIA SD/MMC CARD CONTROLLER DRIVER @@ -10573,6 +10674,14 @@ L: linux-kernel@vger.kernel.org S: Maintained F: drivers/misc/vmw_balloon.c +VMWARE VMMOUSE SUBDRIVER +M: "VMware Graphics" +M: "VMware, Inc." +L: linux-input@vger.kernel.org +S: Maintained +F: drivers/input/mouse/vmmouse.c +F: drivers/input/mouse/vmmouse.h + VMWARE VMXNET3 ETHERNET DRIVER M: Shreyas Bhatewara M: "VMware, Inc." @@ -10898,6 +11007,16 @@ L: linux-serial@vger.kernel.org S: Maintained F: drivers/tty/serial/uartlite.c +XILINX VIDEO IP CORES +M: Hyun Kwon +M: Laurent Pinchart +L: linux-media@vger.kernel.org +T: git git://linuxtv.org/media_tree.git +S: Supported +F: Documentation/devicetree/bindings/media/xilinx/ +F: drivers/media/platform/xilinx/ +F: include/uapi/linux/xilinx-v4l2-controls.h + XILLYBUS DRIVER M: Eli Billauer L: linux-kernel@vger.kernel.org @@ -10962,6 +11081,7 @@ F: drivers/media/pci/zoran/ ZRAM COMPRESSED RAM BLOCK DEVICE DRVIER M: Minchan Kim M: Nitin Gupta +R: Sergey Senozhatsky L: linux-kernel@vger.kernel.org S: Maintained F: drivers/block/zram/ diff --git a/Makefile b/Makefile index 6cc5b243422459cb3ec4317274ebc26c69e0e595..40a8b068ac2699428f5419603bd4464e3c0b47cc 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ VERSION = 4 -PATCHLEVEL = 0 +PATCHLEVEL = 1 SUBLEVEL = 0 -EXTRAVERSION = +EXTRAVERSION = -rc7 NAME = Hurr durr I'ma sheep # *DOCUMENTATION* diff --git a/README b/README index a24ec89ba4420ad38e8848422ca5f69baa5ffe1c..69c68fb4a10908a4f8d1986c6fdad2ec7b3c397b 100644 --- a/README +++ b/README @@ -1,6 +1,6 @@ - Linux kernel release 3.x + Linux kernel release 4.x -These are the release notes for Linux version 3. Read them carefully, +These are the release notes for Linux version 4. Read them carefully, as they tell you what this is all about, explain how to install the kernel, and what to do if something goes wrong. @@ -62,11 +62,7 @@ INSTALLING the kernel source: directory where you have permissions (eg. your home directory) and unpack it: - gzip -cd linux-3.X.tar.gz | tar xvf - - - or - - bzip2 -dc linux-3.X.tar.bz2 | tar xvf - + xz -cd linux-4.X.tar.xz | tar xvf - Replace "X" with the version number of the latest kernel. @@ -75,16 +71,12 @@ INSTALLING the kernel source: files. They should match the library, and not get messed up by whatever the kernel-du-jour happens to be. - - You can also upgrade between 3.x releases by patching. Patches are - distributed in the traditional gzip and the newer bzip2 format. To - install by patching, get all the newer patch files, enter the - top level directory of the kernel source (linux-3.X) and execute: - - gzip -cd ../patch-3.x.gz | patch -p1 - - or + - You can also upgrade between 4.x releases by patching. Patches are + distributed in the xz format. To install by patching, get all the + newer patch files, enter the top level directory of the kernel source + (linux-4.X) and execute: - bzip2 -dc ../patch-3.x.bz2 | patch -p1 + xz -cd ../patch-4.x.xz | patch -p1 Replace "x" for all versions bigger than the version "X" of your current source tree, _in_order_, and you should be ok. You may want to remove @@ -92,13 +84,13 @@ INSTALLING the kernel source: that there are no failed patches (some-file-name# or some-file-name.rej). If there are, either you or I have made a mistake. - Unlike patches for the 3.x kernels, patches for the 3.x.y kernels + Unlike patches for the 4.x kernels, patches for the 4.x.y kernels (also known as the -stable kernels) are not incremental but instead apply - directly to the base 3.x kernel. For example, if your base kernel is 3.0 - and you want to apply the 3.0.3 patch, you must not first apply the 3.0.1 - and 3.0.2 patches. Similarly, if you are running kernel version 3.0.2 and - want to jump to 3.0.3, you must first reverse the 3.0.2 patch (that is, - patch -R) _before_ applying the 3.0.3 patch. You can read more on this in + directly to the base 4.x kernel. For example, if your base kernel is 4.0 + and you want to apply the 4.0.3 patch, you must not first apply the 4.0.1 + and 4.0.2 patches. Similarly, if you are running kernel version 4.0.2 and + want to jump to 4.0.3, you must first reverse the 4.0.2 patch (that is, + patch -R) _before_ applying the 4.0.3 patch. You can read more on this in Documentation/applying-patches.txt Alternatively, the script patch-kernel can be used to automate this @@ -120,7 +112,7 @@ INSTALLING the kernel source: SOFTWARE REQUIREMENTS - Compiling and running the 3.x kernels requires up-to-date + Compiling and running the 4.x kernels requires up-to-date versions of various software packages. Consult Documentation/Changes for the minimum version numbers required and how to get updates for these packages. Beware that using @@ -137,12 +129,12 @@ BUILD directory for the kernel: place for the output files (including .config). Example: - kernel source code: /usr/src/linux-3.X + kernel source code: /usr/src/linux-4.X build directory: /home/name/build/kernel To configure and build the kernel, use: - cd /usr/src/linux-3.X + cd /usr/src/linux-4.X make O=/home/name/build/kernel menuconfig make O=/home/name/build/kernel sudo make O=/home/name/build/kernel modules_install install diff --git a/arch/alpha/boot/Makefile b/arch/alpha/boot/Makefile index cd143887380a26da88e8372828dc586ce3ff7b31..8399bd0e68e8e5cb7aba078cd40864d89b971eed 100644 --- a/arch/alpha/boot/Makefile +++ b/arch/alpha/boot/Makefile @@ -14,6 +14,9 @@ targets := vmlinux.gz vmlinux \ tools/bootpzh bootloader bootpheader bootpzheader OBJSTRIP := $(obj)/tools/objstrip +HOSTCFLAGS := -Wall -I$(objtree)/usr/include +BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj) + # SRM bootable image. Copy to offset 512 of a partition. $(obj)/bootimage: $(addprefix $(obj)/tools/,mkbb lxboot bootlx) $(obj)/vmlinux.nh ( cat $(obj)/tools/lxboot $(obj)/tools/bootlx $(obj)/vmlinux.nh ) > $@ @@ -96,13 +99,14 @@ $(obj)/tools/bootph: $(obj)/bootpheader $(OBJSTRIP) FORCE $(obj)/tools/bootpzh: $(obj)/bootpzheader $(OBJSTRIP) FORCE $(call if_changed,objstrip) -LDFLAGS_bootloader := -static -uvsprintf -T #-N -relax -LDFLAGS_bootpheader := -static -uvsprintf -T #-N -relax -LDFLAGS_bootpzheader := -static -uvsprintf -T #-N -relax +LDFLAGS_bootloader := -static -T # -N -relax +LDFLAGS_bootloader := -static -T # -N -relax +LDFLAGS_bootpheader := -static -T # -N -relax +LDFLAGS_bootpzheader := -static -T # -N -relax -OBJ_bootlx := $(obj)/head.o $(obj)/main.o -OBJ_bootph := $(obj)/head.o $(obj)/bootp.o -OBJ_bootpzh := $(obj)/head.o $(obj)/bootpz.o $(obj)/misc.o +OBJ_bootlx := $(obj)/head.o $(obj)/stdio.o $(obj)/main.o +OBJ_bootph := $(obj)/head.o $(obj)/stdio.o $(obj)/bootp.o +OBJ_bootpzh := $(obj)/head.o $(obj)/stdio.o $(obj)/bootpz.o $(obj)/misc.o $(obj)/bootloader: $(obj)/bootloader.lds $(OBJ_bootlx) $(LIBS_Y) FORCE $(call if_changed,ld) diff --git a/arch/alpha/boot/main.c b/arch/alpha/boot/main.c index 3baf2d1e908df5760f1304bab309ae70877eee03..dd6eb4a33582e63def4b015c0a1ad496889feacd 100644 --- a/arch/alpha/boot/main.c +++ b/arch/alpha/boot/main.c @@ -19,7 +19,6 @@ #include "ksize.h" -extern int vsprintf(char *, const char *, va_list); extern unsigned long switch_to_osf_pal(unsigned long nr, struct pcb_struct * pcb_va, struct pcb_struct * pcb_pa, unsigned long *vptb); diff --git a/arch/alpha/boot/stdio.c b/arch/alpha/boot/stdio.c new file mode 100644 index 0000000000000000000000000000000000000000..f844dae8a54a8b75b4b9fa413033224d94a07af6 --- /dev/null +++ b/arch/alpha/boot/stdio.c @@ -0,0 +1,306 @@ +/* + * Copyright (C) Paul Mackerras 1997. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include + +size_t strnlen(const char * s, size_t count) +{ + const char *sc; + + for (sc = s; count-- && *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} + +# define do_div(n, base) ({ \ + unsigned int __base = (base); \ + unsigned int __rem; \ + __rem = ((unsigned long long)(n)) % __base; \ + (n) = ((unsigned long long)(n)) / __base; \ + __rem; \ +}) + + +static int skip_atoi(const char **s) +{ + int i, c; + + for (i = 0; '0' <= (c = **s) && c <= '9'; ++*s) + i = i*10 + c - '0'; + return i; +} + +#define ZEROPAD 1 /* pad with zero */ +#define SIGN 2 /* unsigned/signed long */ +#define PLUS 4 /* show plus */ +#define SPACE 8 /* space if plus */ +#define LEFT 16 /* left justified */ +#define SPECIAL 32 /* 0x */ +#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ + +static char * number(char * str, unsigned long long num, int base, int size, int precision, int type) +{ + char c,sign,tmp[66]; + const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; + int i; + + if (type & LARGE) + digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + if (type & LEFT) + type &= ~ZEROPAD; + if (base < 2 || base > 36) + return 0; + c = (type & ZEROPAD) ? '0' : ' '; + sign = 0; + if (type & SIGN) { + if ((signed long long)num < 0) { + sign = '-'; + num = - (signed long long)num; + size--; + } else if (type & PLUS) { + sign = '+'; + size--; + } else if (type & SPACE) { + sign = ' '; + size--; + } + } + if (type & SPECIAL) { + if (base == 16) + size -= 2; + else if (base == 8) + size--; + } + i = 0; + if (num == 0) + tmp[i++]='0'; + else while (num != 0) { + tmp[i++] = digits[do_div(num, base)]; + } + if (i > precision) + precision = i; + size -= precision; + if (!(type&(ZEROPAD+LEFT))) + while(size-->0) + *str++ = ' '; + if (sign) + *str++ = sign; + if (type & SPECIAL) { + if (base==8) + *str++ = '0'; + else if (base==16) { + *str++ = '0'; + *str++ = digits[33]; + } + } + if (!(type & LEFT)) + while (size-- > 0) + *str++ = c; + while (i < precision--) + *str++ = '0'; + while (i-- > 0) + *str++ = tmp[i]; + while (size-- > 0) + *str++ = ' '; + return str; +} + +int vsprintf(char *buf, const char *fmt, va_list args) +{ + int len; + unsigned long long num; + int i, base; + char * str; + const char *s; + + int flags; /* flags to number() */ + + int field_width; /* width of output field */ + int precision; /* min. # of digits for integers; max + number of chars for from string */ + int qualifier; /* 'h', 'l', or 'L' for integer fields */ + /* 'z' support added 23/7/1999 S.H. */ + /* 'z' changed to 'Z' --davidm 1/25/99 */ + + + for (str=buf ; *fmt ; ++fmt) { + if (*fmt != '%') { + *str++ = *fmt; + continue; + } + + /* process flags */ + flags = 0; + repeat: + ++fmt; /* this also skips first '%' */ + switch (*fmt) { + case '-': flags |= LEFT; goto repeat; + case '+': flags |= PLUS; goto repeat; + case ' ': flags |= SPACE; goto repeat; + case '#': flags |= SPECIAL; goto repeat; + case '0': flags |= ZEROPAD; goto repeat; + } + + /* get field width */ + field_width = -1; + if ('0' <= *fmt && *fmt <= '9') + field_width = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + field_width = va_arg(args, int); + if (field_width < 0) { + field_width = -field_width; + flags |= LEFT; + } + } + + /* get the precision */ + precision = -1; + if (*fmt == '.') { + ++fmt; + if ('0' <= *fmt && *fmt <= '9') + precision = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + precision = va_arg(args, int); + } + if (precision < 0) + precision = 0; + } + + /* get the conversion qualifier */ + qualifier = -1; + if (*fmt == 'l' && *(fmt + 1) == 'l') { + qualifier = 'q'; + fmt += 2; + } else if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' + || *fmt == 'Z') { + qualifier = *fmt; + ++fmt; + } + + /* default base */ + base = 10; + + switch (*fmt) { + case 'c': + if (!(flags & LEFT)) + while (--field_width > 0) + *str++ = ' '; + *str++ = (unsigned char) va_arg(args, int); + while (--field_width > 0) + *str++ = ' '; + continue; + + case 's': + s = va_arg(args, char *); + if (!s) + s = ""; + + len = strnlen(s, precision); + + if (!(flags & LEFT)) + while (len < field_width--) + *str++ = ' '; + for (i = 0; i < len; ++i) + *str++ = *s++; + while (len < field_width--) + *str++ = ' '; + continue; + + case 'p': + if (field_width == -1) { + field_width = 2*sizeof(void *); + flags |= ZEROPAD; + } + str = number(str, + (unsigned long) va_arg(args, void *), 16, + field_width, precision, flags); + continue; + + + case 'n': + if (qualifier == 'l') { + long * ip = va_arg(args, long *); + *ip = (str - buf); + } else if (qualifier == 'Z') { + size_t * ip = va_arg(args, size_t *); + *ip = (str - buf); + } else { + int * ip = va_arg(args, int *); + *ip = (str - buf); + } + continue; + + case '%': + *str++ = '%'; + continue; + + /* integer number formats - set up the flags and "break" */ + case 'o': + base = 8; + break; + + case 'X': + flags |= LARGE; + case 'x': + base = 16; + break; + + case 'd': + case 'i': + flags |= SIGN; + case 'u': + break; + + default: + *str++ = '%'; + if (*fmt) + *str++ = *fmt; + else + --fmt; + continue; + } + if (qualifier == 'l') { + num = va_arg(args, unsigned long); + if (flags & SIGN) + num = (signed long) num; + } else if (qualifier == 'q') { + num = va_arg(args, unsigned long long); + if (flags & SIGN) + num = (signed long long) num; + } else if (qualifier == 'Z') { + num = va_arg(args, size_t); + } else if (qualifier == 'h') { + num = (unsigned short) va_arg(args, int); + if (flags & SIGN) + num = (signed short) num; + } else { + num = va_arg(args, unsigned int); + if (flags & SIGN) + num = (signed int) num; + } + str = number(str, num, base, field_width, precision, flags); + } + *str = '\0'; + return str-buf; +} + +int sprintf(char * buf, const char *fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); + i=vsprintf(buf,fmt,args); + va_end(args); + return i; +} diff --git a/arch/alpha/boot/tools/objstrip.c b/arch/alpha/boot/tools/objstrip.c index 367d53d031fc04d51af471273a0256a5a08432c7..dee82695f48bad69b0d9cf81457196e321d2ff55 100644 --- a/arch/alpha/boot/tools/objstrip.c +++ b/arch/alpha/boot/tools/objstrip.c @@ -27,6 +27,9 @@ #include #ifdef __ELF__ # include +# define elfhdr elf64_hdr +# define elf_phdr elf64_phdr +# define elf_check_arch(x) ((x)->e_machine == EM_ALPHA) #endif /* bootfile size must be multiple of BLOCK_SIZE: */ diff --git a/arch/alpha/include/asm/types.h b/arch/alpha/include/asm/types.h index f61e1a56c3787bcbd4a2ab093d1c58c7715fa6c4..4cb4b6d3452c0b3439c3aa3c0f928f74de09fb3a 100644 --- a/arch/alpha/include/asm/types.h +++ b/arch/alpha/include/asm/types.h @@ -2,6 +2,5 @@ #define _ALPHA_TYPES_H #include -#include #endif /* _ALPHA_TYPES_H */ diff --git a/arch/alpha/include/asm/unistd.h b/arch/alpha/include/asm/unistd.h index c509d306db4561ea65a40703b42e7f9bd078d352..a56e608db2f9e4aad716b96669de02c7571dc1df 100644 --- a/arch/alpha/include/asm/unistd.h +++ b/arch/alpha/include/asm/unistd.h @@ -3,7 +3,7 @@ #include -#define NR_SYSCALLS 511 +#define NR_SYSCALLS 514 #define __ARCH_WANT_OLD_READDIR #define __ARCH_WANT_STAT64 diff --git a/arch/alpha/include/uapi/asm/unistd.h b/arch/alpha/include/uapi/asm/unistd.h index d214a0358100b6ad82a63fce68bc6016eb9ddaa4..aa33bf5aacb6c1666203e38700939750c90cb5c5 100644 --- a/arch/alpha/include/uapi/asm/unistd.h +++ b/arch/alpha/include/uapi/asm/unistd.h @@ -472,5 +472,8 @@ #define __NR_sched_setattr 508 #define __NR_sched_getattr 509 #define __NR_renameat2 510 +#define __NR_getrandom 511 +#define __NR_memfd_create 512 +#define __NR_execveat 513 #endif /* _UAPI_ALPHA_UNISTD_H */ diff --git a/arch/alpha/kernel/err_ev6.c b/arch/alpha/kernel/err_ev6.c index 253cf1a87481e815ad9a724dde1fef51b5616d09..51267ac5729b9c7276a0e838357bfb8ffd29e7db 100644 --- a/arch/alpha/kernel/err_ev6.c +++ b/arch/alpha/kernel/err_ev6.c @@ -6,7 +6,6 @@ * Error handling code supporting Alpha systems */ -#include #include #include diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c index 7b2be251c30fb92981d4aef8cf4f8951bed24728..51f2c8654253f2bd6667ccff24c0db09a7f80ccc 100644 --- a/arch/alpha/kernel/irq.c +++ b/arch/alpha/kernel/irq.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c index e51f578636a5718d4f0e438b90b4b78a12b6b7da..36dc91ace83ae97069df82f5e3923a24275c6a9b 100644 --- a/arch/alpha/kernel/osf_sys.c +++ b/arch/alpha/kernel/osf_sys.c @@ -1019,14 +1019,13 @@ SYSCALL_DEFINE2(osf_settimeofday, struct timeval32 __user *, tv, if (tv) { if (get_tv32((struct timeval *)&kts, tv)) return -EFAULT; + kts.tv_nsec *= 1000; } if (tz) { if (copy_from_user(&ktz, tz, sizeof(*tz))) return -EFAULT; } - kts.tv_nsec *= 1000; - return do_sys_settimeofday(tv ? &kts : NULL, tz ? &ktz : NULL); } diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c index 1941a07b5811f925aed82e853aab4efb081f74ca..84d13263ce46f193ef0b223466cea2f522ca109d 100644 --- a/arch/alpha/kernel/process.c +++ b/arch/alpha/kernel/process.c @@ -236,12 +236,11 @@ release_thread(struct task_struct *dead_task) } /* - * Copy an alpha thread.. + * Copy architecture-specific thread state */ - int copy_thread(unsigned long clone_flags, unsigned long usp, - unsigned long arg, + unsigned long kthread_arg, struct task_struct *p) { extern void ret_from_fork(void); @@ -262,7 +261,7 @@ copy_thread(unsigned long clone_flags, unsigned long usp, sizeof(struct switch_stack) + sizeof(struct pt_regs)); childstack->r26 = (unsigned long) ret_from_kernel_thread; childstack->r9 = usp; /* function */ - childstack->r10 = arg; + childstack->r10 = kthread_arg; childregs->hae = alpha_mv.hae_cache, childti->pcb.usp = 0; return 0; diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c index 99ac36d5de4efd10832804e82509e062606720e2..2f24447fef92071b0ba9b94d09f8ed1fdc25d2d1 100644 --- a/arch/alpha/kernel/smp.c +++ b/arch/alpha/kernel/smp.c @@ -63,7 +63,6 @@ static struct { enum ipi_message_type { IPI_RESCHEDULE, IPI_CALL_FUNC, - IPI_CALL_FUNC_SINGLE, IPI_CPU_STOP, }; @@ -506,7 +505,6 @@ setup_profiling_timer(unsigned int multiplier) return -EINVAL; } - static void send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation) { @@ -552,10 +550,6 @@ handle_ipi(struct pt_regs *regs) generic_smp_call_function_interrupt(); break; - case IPI_CALL_FUNC_SINGLE: - generic_smp_call_function_single_interrupt(); - break; - case IPI_CPU_STOP: halt(); @@ -606,7 +600,7 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask) void arch_send_call_function_single_ipi(int cpu) { - send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); + send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC); } static void diff --git a/arch/alpha/kernel/srmcons.c b/arch/alpha/kernel/srmcons.c index 6f01d9ad7b814700d8bd56094b13d3af3474cc11..72b59511e59aa350cc58d568cf896edba4f53602 100644 --- a/arch/alpha/kernel/srmcons.c +++ b/arch/alpha/kernel/srmcons.c @@ -237,8 +237,7 @@ srmcons_init(void) return -ENODEV; } - -module_init(srmcons_init); +device_initcall(srmcons_init); /* diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c index f21d61fab6787331d21571958185b637fc601bb7..24e41bd7d3c99060a7411c1c5774941249c89d72 100644 --- a/arch/alpha/kernel/sys_marvel.c +++ b/arch/alpha/kernel/sys_marvel.c @@ -331,7 +331,7 @@ marvel_map_irq(const struct pci_dev *cdev, u8 slot, u8 pin) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline); irq = intline; - msi_loc = pci_find_capability(dev, PCI_CAP_ID_MSI); + msi_loc = dev->msi_cap; msg_ctl = 0; if (msi_loc) pci_read_config_word(dev, msi_loc + PCI_MSI_FLAGS, &msg_ctl); diff --git a/arch/alpha/kernel/systbls.S b/arch/alpha/kernel/systbls.S index 24789713f1eafb4757ec1084c32225ce88bf4ad4..9b62e3fd4f038a925657beb15de3de89f8548473 100644 --- a/arch/alpha/kernel/systbls.S +++ b/arch/alpha/kernel/systbls.S @@ -529,6 +529,9 @@ sys_call_table: .quad sys_sched_setattr .quad sys_sched_getattr .quad sys_renameat2 /* 510 */ + .quad sys_getrandom + .quad sys_memfd_create + .quad sys_execveat .size sys_call_table, . - sys_call_table .type sys_call_table, @object diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c index 9c4c189eb22f5a9db2d2ae678756a5241b3e1ee5..74aceead06e98a391a1f0fc49f5486ef2562844c 100644 --- a/arch/alpha/kernel/traps.c +++ b/arch/alpha/kernel/traps.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include diff --git a/arch/alpha/oprofile/op_model_ev4.c b/arch/alpha/oprofile/op_model_ev4.c index 18aa9b4f94f1822be3e01ea0906fd2cf234c1205..086a0d5445c528b631cec10fd48c5643a4101f86 100644 --- a/arch/alpha/oprofile/op_model_ev4.c +++ b/arch/alpha/oprofile/op_model_ev4.c @@ -8,7 +8,6 @@ */ #include -#include #include #include diff --git a/arch/alpha/oprofile/op_model_ev5.c b/arch/alpha/oprofile/op_model_ev5.c index c32f8a0ad92543a0d6e6767e698f51da0972c17e..c300f5ef3482b82330d41c0b4d318362d76d4092 100644 --- a/arch/alpha/oprofile/op_model_ev5.c +++ b/arch/alpha/oprofile/op_model_ev5.c @@ -8,7 +8,6 @@ */ #include -#include #include #include diff --git a/arch/alpha/oprofile/op_model_ev6.c b/arch/alpha/oprofile/op_model_ev6.c index 1c84cc257fc7ec7a6c3df970722b381f0ed17ff3..02edf59716144e0939eb2933cfb303fa457ecbd7 100644 --- a/arch/alpha/oprofile/op_model_ev6.c +++ b/arch/alpha/oprofile/op_model_ev6.c @@ -8,7 +8,6 @@ */ #include -#include #include #include diff --git a/arch/alpha/oprofile/op_model_ev67.c b/arch/alpha/oprofile/op_model_ev67.c index 34a57a12655377727930f8abba88082f3afde149..adb1744d20f3845efb48a314e56784a5c5470a0a 100644 --- a/arch/alpha/oprofile/op_model_ev67.c +++ b/arch/alpha/oprofile/op_model_ev67.c @@ -9,7 +9,6 @@ */ #include -#include #include #include diff --git a/arch/arc/Kconfig.debug b/arch/arc/Kconfig.debug index a7fc0da25650ef8920e5cfc9f25d417a36081617..ff6a4b5ce92781442aa10f37537d0d6afb1d15f3 100644 --- a/arch/arc/Kconfig.debug +++ b/arch/arc/Kconfig.debug @@ -2,19 +2,6 @@ menu "Kernel hacking" source "lib/Kconfig.debug" -config EARLY_PRINTK - bool "Early printk" if EMBEDDED - default y - help - Write kernel log output directly into the VGA buffer or to a serial - port. - - This is useful for kernel debugging when your machine crashes very - early before the console code is initialized. For normal operation - it is not recommended because it looks ugly and doesn't cooperate - with klogd/syslogd or the X server. You should normally N here, - unless you want to debug such a crash. - config 16KSTACKS bool "Use 16Kb for kernel stacks instead of 8Kb" help diff --git a/arch/arc/boot/dts/angel4.dts b/arch/arc/boot/dts/angel4.dts index 757e0c62c4f98c18139d3ce71c008467549b87ef..3b076fbd83661c1c1889ce178465fb881d24f111 100644 --- a/arch/arc/boot/dts/angel4.dts +++ b/arch/arc/boot/dts/angel4.dts @@ -64,7 +64,7 @@ phy0: ethernet-phy@0 { }; arcpmu0: pmu { - compatible = "snps,arc700-pmu"; + compatible = "snps,arc700-pct"; }; }; }; diff --git a/arch/arc/configs/nsimosci_defconfig b/arch/arc/configs/nsimosci_defconfig index 278dacf2a3f94c66830815572a28d2f754e6abc8..d2ac4e56ba1dd6955c43044aa0ec8da7e062c785 100644 --- a/arch/arc/configs/nsimosci_defconfig +++ b/arch/arc/configs/nsimosci_defconfig @@ -2,6 +2,9 @@ CONFIG_CROSS_COMPILE="arc-linux-uclibc-" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_DEFAULT_HOSTNAME="ARCLinux" # CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y @@ -9,7 +12,7 @@ CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="../arc_initramfs" +CONFIG_INITRAMFS_SOURCE="../arc_initramfs/" CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y # CONFIG_SLUB_DEBUG is not set @@ -21,12 +24,9 @@ CONFIG_MODULES=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set CONFIG_ARC_PLAT_FPGA_LEGACY=y -# CONFIG_ARC_IDE is not set -# CONFIG_ARCTANGENT_EMAC is not set # CONFIG_ARC_HAS_RTSC is not set CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci" # CONFIG_COMPACTION is not set -# CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -39,23 +39,23 @@ CONFIG_INET=y # CONFIG_FIRMWARE_IN_KERNEL is not set # CONFIG_BLK_DEV is not set CONFIG_NETDEVICES=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y # CONFIG_MOUSE_PS2_ALPS is not set # CONFIG_MOUSE_PS2_LOGIPS2PP is not set # CONFIG_MOUSE_PS2_SYNAPTICS is not set +# CONFIG_MOUSE_PS2_CYPRESS is not set # CONFIG_MOUSE_PS2_TRACKPOINT is not set CONFIG_MOUSE_PS2_TOUCHKIT=y -# CONFIG_SERIO_I8042 is not set # CONFIG_SERIO_SERPORT is not set CONFIG_SERIO_ARC_PS2=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_ARC=y -CONFIG_SERIAL_ARC_CONSOLE=y # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set CONFIG_FB=y @@ -72,4 +72,3 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_XZ_DEC=y diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index be33db8a2ee3c3af4ea3d2c9670d4388933a1969..e2b1b1211b0d4ddbb527ed7239eaf05759dfae27 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -30,6 +30,7 @@ #define ARC_REG_D_UNCACH_BCR 0x6A #define ARC_REG_BPU_BCR 0xc0 #define ARC_REG_ISA_CFG_BCR 0xc1 +#define ARC_REG_RTT_BCR 0xF2 #define ARC_REG_SMART_BCR 0xFF /* status32 Bits Positions */ @@ -50,11 +51,7 @@ * [15: 8] = Exception Cause Code * [ 7: 0] = Exception Parameters (for certain types only) */ -#define ECR_VEC_MASK 0xff0000 -#define ECR_CODE_MASK 0x00ff00 -#define ECR_PARAM_MASK 0x0000ff - -/* Exception Cause Vector Values */ +#define ECR_V_MEM_ERR 0x01 #define ECR_V_INSN_ERR 0x02 #define ECR_V_MACH_CHK 0x20 #define ECR_V_ITLB_MISS 0x21 @@ -62,7 +59,8 @@ #define ECR_V_PROTV 0x23 #define ECR_V_TRAP 0x25 -/* Protection Violation Exception Cause Code Values */ +/* DTLB Miss and Protection Violation Cause Codes */ + #define ECR_C_PROTV_INST_FETCH 0x00 #define ECR_C_PROTV_LOAD 0x01 #define ECR_C_PROTV_STORE 0x02 @@ -173,11 +171,11 @@ } \ } -#define WRITE_BCR(reg, into) \ +#define WRITE_AUX(reg, into) \ { \ unsigned int tmp; \ if (sizeof(tmp) == sizeof(into)) { \ - tmp = (*(unsigned int *)(into)); \ + tmp = (*(unsigned int *)&(into)); \ write_aux_reg(reg, tmp); \ } else { \ extern void bogus_undefined(void); \ diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h index 067551b6920af99fe733f1f13d4aee8b1903a77b..9917a45fc430d042a4f59006abf84ceedad1bca7 100644 --- a/arch/arc/include/asm/atomic.h +++ b/arch/arc/include/asm/atomic.h @@ -99,7 +99,7 @@ static inline void atomic_##op(int i, atomic_t *v) \ atomic_ops_unlock(flags); \ } -#define ATOMIC_OP_RETURN(op, c_op) \ +#define ATOMIC_OP_RETURN(op, c_op, asm_op) \ static inline int atomic_##op##_return(int i, atomic_t *v) \ { \ unsigned long flags; \ diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h index 1a5bf07eefe2d445861ecafd2ac03b0b36e9c458..4051e9525939fd9050b06b048bec8e1a47307d7b 100644 --- a/arch/arc/include/asm/bitops.h +++ b/arch/arc/include/asm/bitops.h @@ -32,6 +32,20 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *m) m += nr >> 5; + /* + * ARC ISA micro-optimization: + * + * Instructions dealing with bitpos only consider lower 5 bits (0-31) + * e.g (x << 33) is handled like (x << 1) by ASL instruction + * (mem pointer still needs adjustment to point to next word) + * + * Hence the masking to clamp @nr arg can be elided in general. + * + * However if @nr is a constant (above assumed it in a register), + * and greater than 31, gcc can optimize away (x << 33) to 0, + * as overflow, given the 32-bit ISA. Thus masking needs to be done + * for constant @nr, but no code is generated due to const prop. + */ if (__builtin_constant_p(nr)) nr &= 0x1f; @@ -374,29 +388,20 @@ __test_and_change_bit(unsigned long nr, volatile unsigned long *m) * This routine doesn't need to be atomic. */ static inline int -__constant_test_bit(unsigned int nr, const volatile unsigned long *addr) -{ - return ((1UL << (nr & 31)) & - (((const volatile unsigned int *)addr)[nr >> 5])) != 0; -} - -static inline int -__test_bit(unsigned int nr, const volatile unsigned long *addr) +test_bit(unsigned int nr, const volatile unsigned long *addr) { unsigned long mask; addr += nr >> 5; - /* ARC700 only considers 5 bits in bit-fiddling insn */ + if (__builtin_constant_p(nr)) + nr &= 0x1f; + mask = 1 << nr; return ((mask & *addr) != 0); } -#define test_bit(nr, addr) (__builtin_constant_p(nr) ? \ - __constant_test_bit((nr), (addr)) : \ - __test_bit((nr), (addr))) - /* * Count the number of zeros, starting from MSB * Helper for fls( ) friends diff --git a/arch/arc/include/asm/perf_event.h b/arch/arc/include/asm/perf_event.h index cbf755e32a03f3c19296b552e3f767865fbacc86..2b8880e953a294f4dc4abf7fbe7ae04580dd82ce 100644 --- a/arch/arc/include/asm/perf_event.h +++ b/arch/arc/include/asm/perf_event.h @@ -54,29 +54,13 @@ struct arc_reg_cc_build { #define PERF_COUNT_ARC_BPOK (PERF_COUNT_HW_MAX + 3) #define PERF_COUNT_ARC_EDTLB (PERF_COUNT_HW_MAX + 4) #define PERF_COUNT_ARC_EITLB (PERF_COUNT_HW_MAX + 5) -#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 6) +#define PERF_COUNT_ARC_LDC (PERF_COUNT_HW_MAX + 6) +#define PERF_COUNT_ARC_STC (PERF_COUNT_HW_MAX + 7) + +#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 8) /* - * The "generalized" performance events seem to really be a copy - * of the available events on x86 processors; the mapping to ARC - * events is not always possible 1-to-1. Fortunately, there doesn't - * seem to be an exact definition for these events, so we can cheat - * a bit where necessary. - * - * In particular, the following PERF events may behave a bit differently - * compared to other architectures: - * - * PERF_COUNT_HW_CPU_CYCLES - * Cycles not in halted state - * - * PERF_COUNT_HW_REF_CPU_CYCLES - * Reference cycles not in halted state, same as PERF_COUNT_HW_CPU_CYCLES - * for now as we don't do Dynamic Voltage/Frequency Scaling (yet) - * - * PERF_COUNT_HW_BUS_CYCLES - * Unclear what this means, Intel uses 0x013c, which according to - * their datasheet means "unhalted reference cycles". It sounds similar - * to PERF_COUNT_HW_REF_CPU_CYCLES, and we use the same counter for it. + * Some ARC pct quirks: * * PERF_COUNT_HW_STALLED_CYCLES_BACKEND * PERF_COUNT_HW_STALLED_CYCLES_FRONTEND @@ -91,21 +75,38 @@ struct arc_reg_cc_build { * Note that I$ cache misses aren't counted by either of the two! */ +/* + * ARC PCT has hardware conditions with fixed "names" but variable "indexes" + * (based on a specific RTL build) + * Below is the static map between perf generic/arc specific event_id and + * h/w condition names. + * At the time of probe, we loop thru each index and find it's name to + * complete the mapping of perf event_id to h/w index as latter is needed + * to program the counter really + */ static const char * const arc_pmu_ev_hw_map[] = { + /* count cycles */ [PERF_COUNT_HW_CPU_CYCLES] = "crun", [PERF_COUNT_HW_REF_CPU_CYCLES] = "crun", [PERF_COUNT_HW_BUS_CYCLES] = "crun", - [PERF_COUNT_HW_INSTRUCTIONS] = "iall", - [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush", [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall", - [PERF_COUNT_ARC_DCLM] = "dclm", - [PERF_COUNT_ARC_DCSM] = "dcsm", - [PERF_COUNT_ARC_ICM] = "icm", - [PERF_COUNT_ARC_BPOK] = "bpok", - [PERF_COUNT_ARC_EDTLB] = "edtlb", - [PERF_COUNT_ARC_EITLB] = "eitlb", + + /* counts condition */ + [PERF_COUNT_HW_INSTRUCTIONS] = "iall", + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", + [PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */ + [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */ + + [PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */ + [PERF_COUNT_ARC_STC] = "imemwrc", /* Instr: mem write cached */ + + [PERF_COUNT_ARC_DCLM] = "dclm", /* D-cache Load Miss */ + [PERF_COUNT_ARC_DCSM] = "dcsm", /* D-cache Store Miss */ + [PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */ + [PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */ + [PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */ }; #define C(_x) PERF_COUNT_HW_CACHE_##_x @@ -114,11 +115,11 @@ static const char * const arc_pmu_ev_hw_map[] = { static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [C(L1D)] = { [C(OP_READ)] = { - [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC, [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC, [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM, }, [C(OP_PREFETCH)] = { @@ -128,7 +129,7 @@ static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { }, [C(L1I)] = { [C(OP_READ)] = { - [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS, [C(RESULT_MISS)] = PERF_COUNT_ARC_ICM, }, [C(OP_WRITE)] = { @@ -156,9 +157,10 @@ static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { }, [C(DTLB)] = { [C(OP_READ)] = { - [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC, [C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB, }, + /* DTLB LD/ST Miss not segregated by h/w*/ [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c index ae1c485cbc68ea116d84a0625050c0ab80fea89c..fd2ec50102f201254b1e5e51b4bbc7fa93fba95a 100644 --- a/arch/arc/kernel/perf_event.c +++ b/arch/arc/kernel/perf_event.c @@ -16,6 +16,7 @@ #include #include #include +#include struct arc_pmu { struct pmu pmu; @@ -25,6 +26,46 @@ struct arc_pmu { int ev_hw_idx[PERF_COUNT_ARC_HW_MAX]; }; +struct arc_callchain_trace { + int depth; + void *perf_stuff; +}; + +static int callchain_trace(unsigned int addr, void *data) +{ + struct arc_callchain_trace *ctrl = data; + struct perf_callchain_entry *entry = ctrl->perf_stuff; + perf_callchain_store(entry, addr); + + if (ctrl->depth++ < 3) + return 0; + + return -1; +} + +void +perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) +{ + struct arc_callchain_trace ctrl = { + .depth = 0, + .perf_stuff = entry, + }; + + arc_unwind_core(NULL, regs, callchain_trace, &ctrl); +} + +void +perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) +{ + /* + * User stack can't be unwound trivially with kernel dwarf unwinder + * So for now just record the user PC + */ + perf_callchain_store(entry, instruction_pointer(regs)); +} + +static struct arc_pmu *arc_pmu; + /* read counter #idx; note that counter# != event# on ARC! */ static uint64_t arc_pmu_read_counter(int idx) { @@ -47,7 +88,6 @@ static uint64_t arc_pmu_read_counter(int idx) static void arc_perf_event_update(struct perf_event *event, struct hw_perf_event *hwc, int idx) { - struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu); uint64_t prev_raw_count, new_raw_count; int64_t delta; @@ -89,13 +129,16 @@ static int arc_pmu_cache_event(u64 config) if (ret == CACHE_OP_UNSUPPORTED) return -ENOENT; + pr_debug("init cache event: type/op/result %d/%d/%d with h/w %d \'%s\'\n", + cache_type, cache_op, cache_result, ret, + arc_pmu_ev_hw_map[ret]); + return ret; } /* initializes hw_perf_event structure if event is supported */ static int arc_pmu_event_init(struct perf_event *event) { - struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu); struct hw_perf_event *hwc = &event->hw; int ret; @@ -106,8 +149,9 @@ static int arc_pmu_event_init(struct perf_event *event) if (arc_pmu->ev_hw_idx[event->attr.config] < 0) return -ENOENT; hwc->config = arc_pmu->ev_hw_idx[event->attr.config]; - pr_debug("initializing event %d with cfg %d\n", - (int) event->attr.config, (int) hwc->config); + pr_debug("init event %d with h/w %d \'%s\'\n", + (int) event->attr.config, (int) hwc->config, + arc_pmu_ev_hw_map[event->attr.config]); return 0; case PERF_TYPE_HW_CACHE: ret = arc_pmu_cache_event(event->attr.config); @@ -183,8 +227,6 @@ static void arc_pmu_stop(struct perf_event *event, int flags) static void arc_pmu_del(struct perf_event *event, int flags) { - struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu); - arc_pmu_stop(event, PERF_EF_UPDATE); __clear_bit(event->hw.idx, arc_pmu->used_mask); @@ -194,7 +236,6 @@ static void arc_pmu_del(struct perf_event *event, int flags) /* allocate hardware counter and optionally start counting */ static int arc_pmu_add(struct perf_event *event, int flags) { - struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu); struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; @@ -247,10 +288,7 @@ static int arc_pmu_device_probe(struct platform_device *pdev) BUG_ON(pct_bcr.c > ARC_PMU_MAX_HWEVENTS); READ_BCR(ARC_REG_CC_BUILD, cc_bcr); - if (!cc_bcr.v) { - pr_err("Performance counters exist, but no countable conditions?\n"); - return -ENODEV; - } + BUG_ON(!cc_bcr.v); /* Counters exist but No countable conditions ? */ arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu), GFP_KERNEL); if (!arc_pmu) @@ -263,19 +301,22 @@ static int arc_pmu_device_probe(struct platform_device *pdev) arc_pmu->n_counters, arc_pmu->counter_size, cc_bcr.c); cc_name.str[8] = 0; - for (i = 0; i < PERF_COUNT_HW_MAX; i++) + for (i = 0; i < PERF_COUNT_ARC_HW_MAX; i++) arc_pmu->ev_hw_idx[i] = -1; + /* loop thru all available h/w condition indexes */ for (j = 0; j < cc_bcr.c; j++) { write_aux_reg(ARC_REG_CC_INDEX, j); cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0); cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1); + + /* See if it has been mapped to a perf event_id */ for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) { if (arc_pmu_ev_hw_map[i] && !strcmp(arc_pmu_ev_hw_map[i], cc_name.str) && strlen(arc_pmu_ev_hw_map[i])) { - pr_debug("mapping %d to idx %d with name %s\n", - i, j, cc_name.str); + pr_debug("mapping perf event %2d to h/w event \'%8s\' (idx %d)\n", + i, cc_name.str, j); arc_pmu->ev_hw_idx[i] = j; } } @@ -302,7 +343,7 @@ static int arc_pmu_device_probe(struct platform_device *pdev) #ifdef CONFIG_OF static const struct of_device_id arc_pmu_match[] = { - { .compatible = "snps,arc700-pmu" }, + { .compatible = "snps,arc700-pct" }, {}, }; MODULE_DEVICE_TABLE(of, arc_pmu_match); @@ -310,7 +351,7 @@ MODULE_DEVICE_TABLE(of, arc_pmu_match); static struct platform_driver arc_pmu_driver = { .driver = { - .name = "arc700-pmu", + .name = "arc700-pct", .of_match_table = of_match_ptr(arc_pmu_match), }, .probe = arc_pmu_device_probe, diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c index f46efd14059d302712df70442604c19f1a8f2fe6..e095c557afdddc3aefce744c97d5d7bb20a6f2e6 100644 --- a/arch/arc/kernel/process.c +++ b/arch/arc/kernel/process.c @@ -49,7 +49,10 @@ void arch_cpu_idle(void) asmlinkage void ret_from_fork(void); -/* Layout of Child kernel mode stack as setup at the end of this function is +/* + * Copy architecture-specific thread state + * + * Layout of Child kernel mode stack as setup at the end of this function is * * | ... | * | ... | @@ -81,7 +84,7 @@ asmlinkage void ret_from_fork(void); * ------------------ <===== END of PAGE */ int copy_thread(unsigned long clone_flags, - unsigned long usp, unsigned long arg, + unsigned long usp, unsigned long kthread_arg, struct task_struct *p) { struct pt_regs *c_regs; /* child's pt_regs */ @@ -112,7 +115,7 @@ int copy_thread(unsigned long clone_flags, if (unlikely(p->flags & PF_KTHREAD)) { memset(c_regs, 0, sizeof(struct pt_regs)); - c_callee->r13 = arg; /* argument to kernel thread */ + c_callee->r13 = kthread_arg; c_callee->r14 = usp; /* function */ return 0; diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index 900f68a7008832017296f3dc641e70203358c5d6..1d167c6df8caae8a48d59b2aa08539e9f20b51d6 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -120,7 +120,10 @@ static void read_arc_build_cfg_regs(void) READ_BCR(ARC_REG_SMART_BCR, bcr); cpu->extn.smart = bcr.ver ? 1 : 0; - cpu->extn.debug = cpu->extn.ap | cpu->extn.smart; + READ_BCR(ARC_REG_RTT_BCR, bcr); + cpu->extn.rtt = bcr.ver ? 1 : 0; + + cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt; } static const struct cpuinfo_data arc_cpu_tbl[] = { diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c index 3eadfdabc32295008aa899d74dab4057173ea19e..c927aa84e652e0ac80d37a632c60e1c0201b6d0d 100644 --- a/arch/arc/kernel/traps.c +++ b/arch/arc/kernel/traps.c @@ -42,7 +42,7 @@ void die(const char *str, struct pt_regs *regs, unsigned long address) * -for kernel, chk if due to copy_(to|from)_user, otherwise die() */ static noinline int -handle_exception(const char *str, struct pt_regs *regs, siginfo_t *info) +unhandled_exception(const char *str, struct pt_regs *regs, siginfo_t *info) { if (user_mode(regs)) { struct task_struct *tsk = current; @@ -71,7 +71,7 @@ int name(unsigned long address, struct pt_regs *regs) \ .si_code = sicode, \ .si_addr = (void __user *)address, \ }; \ - return handle_exception(str, regs, &info);\ + return unhandled_exception(str, regs, &info);\ } /* diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c index 8c3a3e02ba92c8adbc368dba9a3cd283f32c3e72..12b2100db0731a2a9ce99ce1398ae4599eaca87a 100644 --- a/arch/arc/mm/cache_arc700.c +++ b/arch/arc/mm/cache_arc700.c @@ -266,7 +266,7 @@ static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr, * Machine specific helpers for Entire D-Cache or Per Line ops */ -static unsigned int __before_dc_op(const int op) +static inline unsigned int __before_dc_op(const int op) { unsigned int reg = reg; @@ -284,7 +284,7 @@ static unsigned int __before_dc_op(const int op) return reg; } -static void __after_dc_op(const int op, unsigned int reg) +static inline void __after_dc_op(const int op, unsigned int reg) { if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS); diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c index 523412369f70a813e0d250013639cae6cb4c1447..d44eedd8c3220e6923b26ea8d10fc6f0f84005f3 100644 --- a/arch/arc/mm/init.c +++ b/arch/arc/mm/init.c @@ -71,7 +71,7 @@ early_param("initrd", early_initrd); */ void __init setup_arch_memory(void) { - unsigned long zones_size[MAX_NR_ZONES] = { 0, 0 }; + unsigned long zones_size[MAX_NR_ZONES]; unsigned long end_mem = CONFIG_LINUX_LINK_BASE + arc_mem_sz; init_mm.start_code = (unsigned long)_text; @@ -90,7 +90,7 @@ void __init setup_arch_memory(void) /*------------- externs in mm need setting up ---------------*/ /* first page of system - kernel .vector starts here */ - min_low_pfn = PFN_DOWN(CONFIG_LINUX_LINK_BASE); + min_low_pfn = ARCH_PFN_OFFSET; /* Last usable page of low mem (no HIGHMEM yet for ARC port) */ max_low_pfn = max_pfn = PFN_DOWN(end_mem); @@ -111,7 +111,7 @@ void __init setup_arch_memory(void) /*-------------- node setup --------------------------------*/ memset(zones_size, 0, sizeof(zones_size)); - zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn; + zones_size[ZONE_NORMAL] = max_mapnr; /* * We can't use the helper free_area_init(zones[]) because it uses @@ -123,6 +123,8 @@ void __init setup_arch_memory(void) zones_size, /* num pages per zone */ min_low_pfn, /* first pfn of node */ NULL); /* NO holes */ + + high_memory = (void *)end_mem; } /* @@ -133,7 +135,6 @@ void __init setup_arch_memory(void) */ void __init mem_init(void) { - high_memory = (void *)(CONFIG_LINUX_LINK_BASE + arc_mem_sz); free_all_bootmem(); mem_init_print_info(NULL); } diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 392e7ae69452e26b97ed8e8d265b7958e0ae75c2..45df48ba0b128dd408e2275687b1757c87e0ca74 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -362,19 +362,6 @@ config ARCH_VERSATILE help This enables support for ARM Ltd Versatile board. -config ARCH_AT91 - bool "Atmel AT91" - select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP - select IRQ_DOMAIN - select NEED_MACH_IO_H if PCCARD - select PINCTRL - select PINCTRL_AT91 - select USE_OF - help - This enables support for systems based on Atmel - AT91RM9200, AT91SAM9 and SAMA5 processors. - config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB @@ -632,18 +619,6 @@ config ARCH_PXA help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. -config ARCH_MSM - bool "Qualcomm MSM (non-multiplatform)" - select ARCH_REQUIRE_GPIOLIB - select COMMON_CLK - select GENERIC_CLOCKEVENTS - help - Support for Qualcomm MSM/QSD based systems. This runs on the - apps processor of the MSM/QSD and depends on a shared memory - interface to the modem processor which runs the baseband - stack and controls some vital subsystems - (clock and power control, etc). - config ARCH_SHMOBILE_LEGACY bool "Renesas ARM SoCs (non-multiplatform)" select ARCH_SHMOBILE @@ -653,7 +628,6 @@ config ARCH_SHMOBILE_LEGACY select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_MACH_CLKDEV select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select MULTI_IRQ_HANDLER @@ -851,6 +825,8 @@ config ARCH_VIRT # source "arch/arm/mach-mvebu/Kconfig" +source "arch/arm/mach-alpine/Kconfig" + source "arch/arm/mach-asm9260/Kconfig" source "arch/arm/mach-at91/Kconfig" @@ -897,8 +873,6 @@ source "arch/arm/mach-ks8695/Kconfig" source "arch/arm/mach-meson/Kconfig" -source "arch/arm/mach-msm/Kconfig" - source "arch/arm/mach-moxart/Kconfig" source "arch/arm/mach-mv78xx0/Kconfig" @@ -1523,7 +1497,7 @@ config HZ_FIXED int default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ ARCH_S5PV210 || ARCH_EXYNOS4 - default AT91_TIMER_HZ if ARCH_AT91 + default 128 if SOC_AT91RM9200 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY default 0 @@ -1856,35 +1830,6 @@ config ZBOOT_ROM Say Y here if you intend to execute your compressed kernel image (zImage) directly from ROM or flash. If unsure, say N. -choice - prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" - depends on ZBOOT_ROM && ARCH_SH7372 - default ZBOOT_ROM_NONE - help - Include experimental SD/MMC loading code in the ROM-able zImage. - With this enabled it is possible to write the ROM-able zImage - kernel image to an MMC or SD card and boot the kernel straight - from the reset vector. At reset the processor Mask ROM will load - the first part of the ROM-able zImage which in turn loads the - rest the kernel image to RAM. - -config ZBOOT_ROM_NONE - bool "No SD/MMC loader in zImage (EXPERIMENTAL)" - help - Do not load image from SD or MMC - -config ZBOOT_ROM_MMCIF - bool "Include MMCIF loader in zImage (EXPERIMENTAL)" - help - Load image from MMCIF hardware block. - -config ZBOOT_ROM_SH_MOBILE_SDHI - bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" - help - Load image from SDHI hardware block - -endchoice - config ARM_APPENDED_DTB bool "Use appended device tree blob to zImage (EXPERIMENTAL)" depends on OF @@ -2158,6 +2103,8 @@ source "net/Kconfig" source "drivers/Kconfig" +source "drivers/firmware/Kconfig" + source "fs/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 970de7518341d2382ee86a8c9a0cefde2bca2739..0c12ffb155a23c604c9bbb9b849a913d359e34ae 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -93,6 +93,14 @@ choice prompt "Kernel low-level debugging port" depends on DEBUG_LL + config DEBUG_ALPINE_UART0 + bool "Kernel low-level debugging messages via Alpine UART0" + depends on ARCH_ALPINE + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Alpine based platforms. + config DEBUG_ASM9260_UART bool "Kernel low-level debugging via asm9260 UART" depends on MACH_ASM9260 @@ -448,25 +456,6 @@ choice Say Y here if you want kernel low-level debugging support on MMP UART3. - config DEBUG_MSM_UART - bool "Kernel low-level debugging messages via MSM UART" - depends on ARCH_MSM - help - Say Y here if you want the debug print routines to direct - their output to the serial port on MSM devices. - - ARCH DEBUG_UART_PHYS DEBUG_UART_VIRT # - MSM7X00A, QSD8X50 0xa9a00000 0xe1000000 UART1 - MSM7X00A, QSD8X50 0xa9b00000 0xe1000000 UART2 - MSM7X00A, QSD8X50 0xa9c00000 0xe1000000 UART3 - - MSM7X30 0xaca00000 0xe1000000 UART1 - MSM7X30 0xacb00000 0xe1000000 UART2 - MSM7X30 0xacc00000 0xe1000000 UART3 - - Please adjust DEBUG_UART_PHYS and DEBUG_UART_BASE configuration - options based on your needs. - config DEBUG_QCOM_UARTDM bool "Kernel low-level debugging messages via QCOM UARTDM" depends on ARCH_QCOM @@ -806,7 +795,7 @@ choice via SCIF2 on Renesas R-Car H1 (R8A7779). config DEBUG_RCAR_GEN2_SCIF0 - bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7793)" + bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7793" depends on ARCH_R8A7790 || ARCH_R8A7791 || ARCH_R8A7793 help Say Y here if you want kernel low-level debugging support @@ -821,12 +810,11 @@ choice via SCIF2 on Renesas R-Car E2 (R8A7794). config DEBUG_RMOBILE_SCIFA0 - bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4/SH7372" - depends on ARCH_R8A73A4 || ARCH_SH7372 + bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4" + depends on ARCH_R8A73A4 help Say Y here if you want kernel low-level debugging support - via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4) or SH-Mobile - AP4 (SH7372). + via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4). config DEBUG_RMOBILE_SCIFA1 bool "Kernel low-level debugging messages via SCIFA1 on R8A7740" @@ -1295,7 +1283,7 @@ config DEBUG_LL_INCLUDE DEBUG_IMX6SL_UART || \ DEBUG_IMX6SX_UART default "debug/ks8695.S" if DEBUG_KS8695_UART - default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM + default "debug/msm.S" if DEBUG_QCOM_UARTDM default "debug/netx.S" if DEBUG_NETX_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2 @@ -1388,7 +1376,6 @@ config DEBUG_UART_PHYS default 0x80230000 if DEBUG_PICOXCELL_UART default 0x808c0000 if ARCH_EP93XX default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART - default 0xa9a00000 if DEBUG_MSM_UART default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1 default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX default 0xc0013000 if DEBUG_U300_UART @@ -1417,6 +1404,7 @@ config DEBUG_UART_PHYS default 0xf8b00000 if DEBUG_HIX5HD2_UART default 0xf991e000 if DEBUG_QCOM_UARTDM default 0xfcb00000 if DEBUG_HI3620_UART + default 0xfd883000 if DEBUG_ALPINE_UART0 default 0xfe800000 if ARCH_IOP32X default 0xff690000 if DEBUG_RK32_UART2 default 0xffc02000 if DEBUG_SOCFPGA_UART @@ -1433,7 +1421,7 @@ config DEBUG_UART_PHYS DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ DEBUG_LL_UART_EFM32 || \ DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ - DEBUG_MSM_UART || DEBUG_NETX_UART || \ + DEBUG_NETX_UART || \ DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \ DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \ @@ -1446,7 +1434,6 @@ config DEBUG_UART_VIRT hex "Virtual base address of debug UART" default 0xe0000a00 if DEBUG_NETX_UART default 0xe0010fe0 if ARCH_RPC - default 0xe1000000 if DEBUG_MSM_UART default 0xf0000be0 if ARCH_EBSA110 default 0xf0010000 if DEBUG_ASM9260_UART default 0xf01fb000 if DEBUG_NOMADIK_UART @@ -1483,6 +1470,7 @@ config DEBUG_UART_VIRT default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX default 0xfd000000 if ARCH_SPEAR13XX default 0xfd012000 if ARCH_MV78XX0 + default 0xfd883000 if DEBUG_ALPINE_UART0 default 0xfde12000 if ARCH_DOVE default 0xfe012000 if ARCH_ORION5X default 0xf31004c0 if DEBUG_MESON_UARTAO @@ -1526,7 +1514,7 @@ config DEBUG_UART_VIRT default DEBUG_UART_PHYS if !MMU depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ - DEBUG_MSM_UART || DEBUG_NETX_UART || \ + DEBUG_NETX_UART || \ DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \ DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 @@ -1543,7 +1531,7 @@ config DEBUG_UART_8250_WORD depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 depends on DEBUG_UART_8250_SHIFT >= 2 default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \ - ARCH_KEYSTONE || \ + ARCH_KEYSTONE || DEBUG_ALPINE_UART0 || \ DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ DEBUG_DAVINCI_DA8XX_UART2 || \ DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \ @@ -1556,7 +1544,7 @@ config DEBUG_UART_8250_FLOW_CONTROL config DEBUG_UNCOMPRESS bool - depends on ARCH_MULTIPLATFORM || ARCH_MSM || PLAT_SAMSUNG + depends on ARCH_MULTIPLATFORM || PLAT_SAMSUNG default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \ (!DEBUG_TEGRA_UART || !ZBOOT_ROM) help @@ -1573,7 +1561,8 @@ config DEBUG_UNCOMPRESS config UNCOMPRESS_INCLUDE string default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \ - PLAT_SAMSUNG || ARCH_EFM32 + PLAT_SAMSUNG || ARCH_EFM32 || \ + ARCH_SHMOBILE_LEGACY default "mach/uncompress.h" config EARLY_PRINTK @@ -1610,59 +1599,6 @@ config DEBUG_SET_MODULE_RONX against certain classes of kernel exploits. If in doubt, say "N". -menuconfig CORESIGHT - bool "CoreSight Tracing Support" - select ARM_AMBA - help - This framework provides a kernel interface for the CoreSight debug - and trace drivers to register themselves with. It's intended to build - a topological view of the CoreSight components based on a DT - specification and configure the right serie of components when a - trace source gets enabled. - -if CORESIGHT -config CORESIGHT_LINKS_AND_SINKS - bool "CoreSight Link and Sink drivers" - help - This enables support for CoreSight link and sink drivers that are - responsible for transporting and collecting the trace data - respectively. Link and sinks are dynamically aggregated with a trace - entity at run time to form a complete trace path. - -config CORESIGHT_LINK_AND_SINK_TMC - bool "Coresight generic TMC driver" - depends on CORESIGHT_LINKS_AND_SINKS - help - This enables support for the Trace Memory Controller driver. Depending - on its configuration the device can act as a link (embedded trace router - - ETR) or sink (embedded trace FIFO). The driver complies with the - generic implementation of the component without special enhancement or - added features. - -config CORESIGHT_SINK_TPIU - bool "Coresight generic TPIU driver" - depends on CORESIGHT_LINKS_AND_SINKS - help - This enables support for the Trace Port Interface Unit driver, responsible - for bridging the gap between the on-chip coresight components and a trace - port collection engine, typically connected to an external host for use - case capturing more traces than the on-board coresight memory can handle. - -config CORESIGHT_SINK_ETBV10 - bool "Coresight ETBv1.0 driver" - depends on CORESIGHT_LINKS_AND_SINKS - help - This enables support for the Embedded Trace Buffer version 1.0 driver - that complies with the generic implementation of the component without - special enhancement or added features. +source "drivers/hwtracing/coresight/Kconfig" -config CORESIGHT_SOURCE_ETM3X - bool "CoreSight Embedded Trace Macrocell 3.x driver" - select CORESIGHT_LINKS_AND_SINKS - help - This driver provides support for processor ETM3.x and PTM1.x modules, - which allows tracing the instructions that a processor is executing - This is primarily useful for instruction level tracing. Depending - the ETM version data tracing may also be available. -endif endmenu diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5575d9fa8806cd5f74409242a7041f2e96b16453..985227cbbd1bd797546c36099dcd7cc17c0efc4f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -136,13 +136,13 @@ textofs-$(CONFIG_PM_H1940) := 0x00108000 ifeq ($(CONFIG_ARCH_SA1100),y) textofs-$(CONFIG_SA1111) := 0x00208000 endif -textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000 textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. +machine-$(CONFIG_ARCH_ALPINE) += alpine machine-$(CONFIG_ARCH_AT91) += at91 machine-$(CONFIG_ARCH_AXXIA) += axxia machine-$(CONFIG_ARCH_BCM) += bcm @@ -171,7 +171,6 @@ machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MMP) += mmp machine-$(CONFIG_ARCH_MOXART) += moxart -machine-$(CONFIG_ARCH_MSM) += msm machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_MXC) += imx diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 3ea230aa94b7e061f53b2b4cea9f867bb6c6aa17..6e1fb2b2ecc750ee4898240d1421d985888cc096 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -6,21 +6,6 @@ OBJS = -# Ensure that MMCIF loader code appears early in the image -# to minimise that number of bocks that have to be read in -# order to load it. -ifeq ($(CONFIG_ZBOOT_ROM_MMCIF),y) -OBJS += mmcif-sh7372.o -endif - -# Ensure that SDHI loader code appears early in the image -# to minimise that number of bocks that have to be read in -# order to load it. -ifeq ($(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI),y) -OBJS += sdhi-shmobile.o -OBJS += sdhi-sh7372.o -endif - AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) HEAD = head.o OBJS += misc.o decompress.o diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S index e7f80928949c8da53a13b2bca5ace2928c1ba4c2..22a75259faa32996dffa65843c8b85f29c7d7357 100644 --- a/arch/arm/boot/compressed/head-shmobile.S +++ b/arch/arm/boot/compressed/head-shmobile.S @@ -25,36 +25,6 @@ /* load board-specific initialization code */ #include -#if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI) - /* Load image from MMC/SD */ - adr sp, __tmp_stack + 256 - ldr r0, __image_start - ldr r1, __image_end - subs r1, r1, r0 - ldr r0, __load_base - bl mmc_loader - - /* Jump to loaded code */ - ldr r0, __loaded - ldr r1, __image_start - sub r0, r0, r1 - ldr r1, __load_base - add pc, r0, r1 - -__image_start: - .long _start -__image_end: - .long _got_end -__load_base: - .long MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM -__loaded: - .long __continue - .align -__tmp_stack: - .space 256 -__continue: -#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */ - adr r0, dtb_info ldmia r0, {r1, r3, r4, r5, r7} diff --git a/arch/arm/boot/compressed/mmcif-sh7372.c b/arch/arm/boot/compressed/mmcif-sh7372.c deleted file mode 100644 index 672ae95db5c3177aedc1dfdb3825a490b31e9fc2..0000000000000000000000000000000000000000 --- a/arch/arm/boot/compressed/mmcif-sh7372.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * sh7372 MMCIF loader - * - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2010 Simon Horman - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include -#include -#include - -#define MMCIF_BASE (void __iomem *)0xe6bd0000 - -#define PORT84CR (void __iomem *)0xe6050054 -#define PORT85CR (void __iomem *)0xe6050055 -#define PORT86CR (void __iomem *)0xe6050056 -#define PORT87CR (void __iomem *)0xe6050057 -#define PORT88CR (void __iomem *)0xe6050058 -#define PORT89CR (void __iomem *)0xe6050059 -#define PORT90CR (void __iomem *)0xe605005a -#define PORT91CR (void __iomem *)0xe605005b -#define PORT92CR (void __iomem *)0xe605005c -#define PORT99CR (void __iomem *)0xe6050063 - -#define SMSTPCR3 (void __iomem *)0xe615013c - -/* SH7372 specific MMCIF loader - * - * loads the zImage from an MMC card starting from block 1. - * - * The image must be start with a vrl4 header and - * the zImage must start at offset 512 of the image. That is, - * at block 2 (=byte 1024) on the media - * - * Use the following line to write the vrl4 formated zImage - * to an MMC card - * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1 - */ -asmlinkage void mmc_loader(unsigned char *buf, unsigned long len) -{ - mmc_init_progress(); - mmc_update_progress(MMC_PROGRESS_ENTER); - - /* Initialise MMC - * registers: PORT84CR-PORT92CR - * (MMCD0_0-MMCD0_7,MMCCMD0 Control) - * value: 0x04 - select function 4 - */ - __raw_writeb(0x04, PORT84CR); - __raw_writeb(0x04, PORT85CR); - __raw_writeb(0x04, PORT86CR); - __raw_writeb(0x04, PORT87CR); - __raw_writeb(0x04, PORT88CR); - __raw_writeb(0x04, PORT89CR); - __raw_writeb(0x04, PORT90CR); - __raw_writeb(0x04, PORT91CR); - __raw_writeb(0x04, PORT92CR); - - /* Initialise MMC - * registers: PORT99CR (MMCCLK0 Control) - * value: 0x10 | 0x04 - enable output | select function 4 - */ - __raw_writeb(0x14, PORT99CR); - - /* Enable clock to MMC hardware block */ - __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3); - - mmc_update_progress(MMC_PROGRESS_INIT); - - /* setup MMCIF hardware */ - sh_mmcif_boot_init(MMCIF_BASE); - - mmc_update_progress(MMC_PROGRESS_LOAD); - - /* load kernel via MMCIF interface */ - sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */ - (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf); - - - /* Disable clock to MMC hardware block */ - __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3); - - mmc_update_progress(MMC_PROGRESS_DONE); -} diff --git a/arch/arm/boot/compressed/sdhi-sh7372.c b/arch/arm/boot/compressed/sdhi-sh7372.c deleted file mode 100644 index d279294f238116fa4fbd3c71931149528516b483..0000000000000000000000000000000000000000 --- a/arch/arm/boot/compressed/sdhi-sh7372.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * SuperH Mobile SDHI - * - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2010 Kuninori Morimoto - * Copyright (C) 2010 Simon Horman - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Parts inspired by u-boot - */ - -#include -#include -#include -#include - -#include "sdhi-shmobile.h" - -#define PORT179CR 0xe60520b3 -#define PORT180CR 0xe60520b4 -#define PORT181CR 0xe60520b5 -#define PORT182CR 0xe60520b6 -#define PORT183CR 0xe60520b7 -#define PORT184CR 0xe60520b8 - -#define SMSTPCR3 0xe615013c - -#define CR_INPUT_ENABLE 0x10 -#define CR_FUNCTION1 0x01 - -#define SDHI1_BASE (void __iomem *)0xe6860000 -#define SDHI_BASE SDHI1_BASE - -/* SuperH Mobile SDHI loader - * - * loads the zImage from an SD card starting from block 0 - * on physical partition 1 - * - * The image must be start with a vrl4 header and - * the zImage must start at offset 512 of the image. That is, - * at block 1 (=byte 512) of physical partition 1 - * - * Use the following line to write the vrl4 formated zImage - * to an SD card - * # dd if=vrl4.out of=/dev/sdx bs=512 - */ -asmlinkage void mmc_loader(unsigned short *buf, unsigned long len) -{ - int high_capacity; - - mmc_init_progress(); - - mmc_update_progress(MMC_PROGRESS_ENTER); - /* Initialise SDHI1 */ - /* PORT184CR: GPIO_FN_SDHICMD1 Control */ - __raw_writeb(CR_FUNCTION1, PORT184CR); - /* PORT179CR: GPIO_FN_SDHICLK1 Control */ - __raw_writeb(CR_INPUT_ENABLE|CR_FUNCTION1, PORT179CR); - /* PORT181CR: GPIO_FN_SDHID1_3 Control */ - __raw_writeb(CR_FUNCTION1, PORT183CR); - /* PORT182CR: GPIO_FN_SDHID1_2 Control */ - __raw_writeb(CR_FUNCTION1, PORT182CR); - /* PORT183CR: GPIO_FN_SDHID1_1 Control */ - __raw_writeb(CR_FUNCTION1, PORT181CR); - /* PORT180CR: GPIO_FN_SDHID1_0 Control */ - __raw_writeb(CR_FUNCTION1, PORT180CR); - - /* Enable clock to SDHI1 hardware block */ - __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 13), SMSTPCR3); - - /* setup SDHI hardware */ - mmc_update_progress(MMC_PROGRESS_INIT); - high_capacity = sdhi_boot_init(SDHI_BASE); - if (high_capacity < 0) - goto err; - - mmc_update_progress(MMC_PROGRESS_LOAD); - /* load kernel */ - if (sdhi_boot_do_read(SDHI_BASE, high_capacity, - 0, /* Kernel is at block 1 */ - (len + TMIO_BBS - 1) / TMIO_BBS, buf)) - goto err; - - /* Disable clock to SDHI1 hardware block */ - __raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3); - - mmc_update_progress(MMC_PROGRESS_DONE); - - return; -err: - for(;;); -} diff --git a/arch/arm/boot/compressed/sdhi-shmobile.c b/arch/arm/boot/compressed/sdhi-shmobile.c deleted file mode 100644 index bd3d46980955bfff687b9d61d52ed1413f313cad..0000000000000000000000000000000000000000 --- a/arch/arm/boot/compressed/sdhi-shmobile.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * SuperH Mobile SDHI - * - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2010 Kuninori Morimoto - * Copyright (C) 2010 Simon Horman - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Parts inspired by u-boot - */ - -#include -#include -#include -#include -#include -#include -#include - -#define OCR_FASTBOOT (1<<29) -#define OCR_HCS (1<<30) -#define OCR_BUSY (1<<31) - -#define RESP_CMD12 0x00000030 - -static inline u16 sd_ctrl_read16(void __iomem *base, int addr) -{ - return __raw_readw(base + addr); -} - -static inline u32 sd_ctrl_read32(void __iomem *base, int addr) -{ - return __raw_readw(base + addr) | - __raw_readw(base + addr + 2) << 16; -} - -static inline void sd_ctrl_write16(void __iomem *base, int addr, u16 val) -{ - __raw_writew(val, base + addr); -} - -static inline void sd_ctrl_write32(void __iomem *base, int addr, u32 val) -{ - __raw_writew(val, base + addr); - __raw_writew(val >> 16, base + addr + 2); -} - -#define ALL_ERROR (TMIO_STAT_CMD_IDX_ERR | TMIO_STAT_CRCFAIL | \ - TMIO_STAT_STOPBIT_ERR | TMIO_STAT_DATATIMEOUT | \ - TMIO_STAT_RXOVERFLOW | TMIO_STAT_TXUNDERRUN | \ - TMIO_STAT_CMDTIMEOUT | TMIO_STAT_ILL_ACCESS | \ - TMIO_STAT_ILL_FUNC) - -static int sdhi_intr(void __iomem *base) -{ - unsigned long state = sd_ctrl_read32(base, CTL_STATUS); - - if (state & ALL_ERROR) { - sd_ctrl_write32(base, CTL_STATUS, ~ALL_ERROR); - sd_ctrl_write32(base, CTL_IRQ_MASK, - ALL_ERROR | - sd_ctrl_read32(base, CTL_IRQ_MASK)); - return -EINVAL; - } - if (state & TMIO_STAT_CMDRESPEND) { - sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND); - sd_ctrl_write32(base, CTL_IRQ_MASK, - TMIO_STAT_CMDRESPEND | - sd_ctrl_read32(base, CTL_IRQ_MASK)); - return 0; - } - if (state & TMIO_STAT_RXRDY) { - sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_RXRDY); - sd_ctrl_write32(base, CTL_IRQ_MASK, - TMIO_STAT_RXRDY | TMIO_STAT_TXUNDERRUN | - sd_ctrl_read32(base, CTL_IRQ_MASK)); - return 0; - } - if (state & TMIO_STAT_DATAEND) { - sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_DATAEND); - sd_ctrl_write32(base, CTL_IRQ_MASK, - TMIO_STAT_DATAEND | - sd_ctrl_read32(base, CTL_IRQ_MASK)); - return 0; - } - - return -EAGAIN; -} - -static int sdhi_boot_wait_resp_end(void __iomem *base) -{ - int err = -EAGAIN, timeout = 10000000; - - while (timeout--) { - err = sdhi_intr(base); - if (err != -EAGAIN) - break; - udelay(1); - } - - return err; -} - -/* SDHI_CLK_CTRL */ -#define CLK_MMC_ENABLE (1 << 8) -#define CLK_MMC_INIT (1 << 6) /* clk / 256 */ - -static void sdhi_boot_mmc_clk_stop(void __iomem *base) -{ - sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, 0x0000); - msleep(10); - sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, ~CLK_MMC_ENABLE & - sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL)); - msleep(10); -} - -static void sdhi_boot_mmc_clk_start(void __iomem *base) -{ - sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, CLK_MMC_ENABLE | - sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL)); - msleep(10); - sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, CLK_MMC_ENABLE); - msleep(10); -} - -static void sdhi_boot_reset(void __iomem *base) -{ - sd_ctrl_write16(base, CTL_RESET_SD, 0x0000); - msleep(10); - sd_ctrl_write16(base, CTL_RESET_SD, 0x0001); - msleep(10); -} - -/* Set MMC clock / power. - * Note: This controller uses a simple divider scheme therefore it cannot - * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as - * MMC wont run that fast, it has to be clocked at 12MHz which is the next - * slowest setting. - */ -static int sdhi_boot_mmc_set_ios(void __iomem *base, struct mmc_ios *ios) -{ - if (sd_ctrl_read32(base, CTL_STATUS) & TMIO_STAT_CMD_BUSY) - return -EBUSY; - - if (ios->clock) - sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, - ios->clock | CLK_MMC_ENABLE); - - /* Power sequence - OFF -> ON -> UP */ - switch (ios->power_mode) { - case MMC_POWER_OFF: /* power down SD bus */ - sdhi_boot_mmc_clk_stop(base); - break; - case MMC_POWER_ON: /* power up SD bus */ - break; - case MMC_POWER_UP: /* start bus clock */ - sdhi_boot_mmc_clk_start(base); - break; - } - - switch (ios->bus_width) { - case MMC_BUS_WIDTH_1: - sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x80e0); - break; - case MMC_BUS_WIDTH_4: - sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x00e0); - break; - } - - /* Let things settle. delay taken from winCE driver */ - udelay(140); - - return 0; -} - -/* These are the bitmasks the tmio chip requires to implement the MMC response - * types. Note that R1 and R6 are the same in this scheme. */ -#define RESP_NONE 0x0300 -#define RESP_R1 0x0400 -#define RESP_R1B 0x0500 -#define RESP_R2 0x0600 -#define RESP_R3 0x0700 -#define DATA_PRESENT 0x0800 -#define TRANSFER_READ 0x1000 - -static int sdhi_boot_request(void __iomem *base, struct mmc_command *cmd) -{ - int err, c = cmd->opcode; - - switch (mmc_resp_type(cmd)) { - case MMC_RSP_NONE: c |= RESP_NONE; break; - case MMC_RSP_R1: c |= RESP_R1; break; - case MMC_RSP_R1B: c |= RESP_R1B; break; - case MMC_RSP_R2: c |= RESP_R2; break; - case MMC_RSP_R3: c |= RESP_R3; break; - default: - return -EINVAL; - } - - /* No interrupts so this may not be cleared */ - sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND); - - sd_ctrl_write32(base, CTL_IRQ_MASK, TMIO_STAT_CMDRESPEND | - sd_ctrl_read32(base, CTL_IRQ_MASK)); - sd_ctrl_write32(base, CTL_ARG_REG, cmd->arg); - sd_ctrl_write16(base, CTL_SD_CMD, c); - - - sd_ctrl_write32(base, CTL_IRQ_MASK, - ~(TMIO_STAT_CMDRESPEND | ALL_ERROR) & - sd_ctrl_read32(base, CTL_IRQ_MASK)); - - err = sdhi_boot_wait_resp_end(base); - if (err) - return err; - - cmd->resp[0] = sd_ctrl_read32(base, CTL_RESPONSE); - - return 0; -} - -static int sdhi_boot_do_read_single(void __iomem *base, int high_capacity, - unsigned long block, unsigned short *buf) -{ - int err, i; - - /* CMD17 - Read */ - { - struct mmc_command cmd; - - cmd.opcode = MMC_READ_SINGLE_BLOCK | \ - TRANSFER_READ | DATA_PRESENT; - if (high_capacity) - cmd.arg = block; - else - cmd.arg = block * TMIO_BBS; - cmd.flags = MMC_RSP_R1; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - } - - sd_ctrl_write32(base, CTL_IRQ_MASK, - ~(TMIO_STAT_DATAEND | TMIO_STAT_RXRDY | - TMIO_STAT_TXUNDERRUN) & - sd_ctrl_read32(base, CTL_IRQ_MASK)); - err = sdhi_boot_wait_resp_end(base); - if (err) - return err; - - sd_ctrl_write16(base, CTL_SD_XFER_LEN, TMIO_BBS); - for (i = 0; i < TMIO_BBS / sizeof(*buf); i++) - *buf++ = sd_ctrl_read16(base, RESP_CMD12); - - err = sdhi_boot_wait_resp_end(base); - if (err) - return err; - - return 0; -} - -int sdhi_boot_do_read(void __iomem *base, int high_capacity, - unsigned long offset, unsigned short count, - unsigned short *buf) -{ - unsigned long i; - int err = 0; - - for (i = 0; i < count; i++) { - err = sdhi_boot_do_read_single(base, high_capacity, offset + i, - buf + (i * TMIO_BBS / - sizeof(*buf))); - if (err) - return err; - } - - return 0; -} - -#define VOLTAGES (MMC_VDD_32_33 | MMC_VDD_33_34) - -int sdhi_boot_init(void __iomem *base) -{ - bool sd_v2 = false, sd_v1_0 = false; - unsigned short cid; - int err, high_capacity = 0; - - sdhi_boot_mmc_clk_stop(base); - sdhi_boot_reset(base); - - /* mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 0 timing 0 */ - { - struct mmc_ios ios; - ios.power_mode = MMC_POWER_ON; - ios.bus_width = MMC_BUS_WIDTH_1; - ios.clock = CLK_MMC_INIT; - err = sdhi_boot_mmc_set_ios(base, &ios); - if (err) - return err; - } - - /* CMD0 */ - { - struct mmc_command cmd; - msleep(1); - cmd.opcode = MMC_GO_IDLE_STATE; - cmd.arg = 0; - cmd.flags = MMC_RSP_NONE; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - msleep(2); - } - - /* CMD8 - Test for SD version 2 */ - { - struct mmc_command cmd; - cmd.opcode = SD_SEND_IF_COND; - cmd.arg = (VOLTAGES != 0) << 8 | 0xaa; - cmd.flags = MMC_RSP_R1; - err = sdhi_boot_request(base, &cmd); /* Ignore error */ - if ((cmd.resp[0] & 0xff) == 0xaa) - sd_v2 = true; - } - - /* CMD55 - Get OCR (SD) */ - { - int timeout = 1000; - struct mmc_command cmd; - - cmd.arg = 0; - - do { - cmd.opcode = MMC_APP_CMD; - cmd.flags = MMC_RSP_R1; - cmd.arg = 0; - err = sdhi_boot_request(base, &cmd); - if (err) - break; - - cmd.opcode = SD_APP_OP_COND; - cmd.flags = MMC_RSP_R3; - cmd.arg = (VOLTAGES & 0xff8000); - if (sd_v2) - cmd.arg |= OCR_HCS; - cmd.arg |= OCR_FASTBOOT; - err = sdhi_boot_request(base, &cmd); - if (err) - break; - - msleep(1); - } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout); - - if (!err && timeout) { - if (!sd_v2) - sd_v1_0 = true; - high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS; - } - } - - /* CMD1 - Get OCR (MMC) */ - if (!sd_v2 && !sd_v1_0) { - int timeout = 1000; - struct mmc_command cmd; - - do { - cmd.opcode = MMC_SEND_OP_COND; - cmd.arg = VOLTAGES | OCR_HCS; - cmd.flags = MMC_RSP_R3; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - - msleep(1); - } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout); - - if (!timeout) - return -EAGAIN; - - high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS; - } - - /* CMD2 - Get CID */ - { - struct mmc_command cmd; - cmd.opcode = MMC_ALL_SEND_CID; - cmd.arg = 0; - cmd.flags = MMC_RSP_R2; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - } - - /* CMD3 - * MMC: Set the relative address - * SD: Get the relative address - * Also puts the card into the standby state - */ - { - struct mmc_command cmd; - cmd.opcode = MMC_SET_RELATIVE_ADDR; - cmd.arg = 0; - cmd.flags = MMC_RSP_R1; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - cid = cmd.resp[0] >> 16; - } - - /* CMD9 - Get CSD */ - { - struct mmc_command cmd; - cmd.opcode = MMC_SEND_CSD; - cmd.arg = cid << 16; - cmd.flags = MMC_RSP_R2; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - } - - /* CMD7 - Select the card */ - { - struct mmc_command cmd; - cmd.opcode = MMC_SELECT_CARD; - //cmd.arg = rca << 16; - cmd.arg = cid << 16; - //cmd.flags = MMC_RSP_R1B; - cmd.flags = MMC_RSP_R1; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - } - - /* CMD16 - Set the block size */ - { - struct mmc_command cmd; - cmd.opcode = MMC_SET_BLOCKLEN; - cmd.arg = TMIO_BBS; - cmd.flags = MMC_RSP_R1; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - } - - return high_capacity; -} diff --git a/arch/arm/boot/compressed/sdhi-shmobile.h b/arch/arm/boot/compressed/sdhi-shmobile.h deleted file mode 100644 index 92eaa09f985eecdd603a080f3650cea7d8836e63..0000000000000000000000000000000000000000 --- a/arch/arm/boot/compressed/sdhi-shmobile.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef SDHI_MOBILE_H -#define SDHI_MOBILE_H - -#include - -int sdhi_boot_do_read(void __iomem *base, int high_capacity, - unsigned long offset, unsigned short count, - unsigned short *buf); -int sdhi_boot_init(void __iomem *base); - -#endif diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a1c776b8dcec51554879d1e001f7f96bd653efd8..992736b5229ba7bd06497feb35ecff5fc36ab232 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1,5 +1,7 @@ ifeq ($(CONFIG_OF),y) +dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine-db.dtb dtb-$(CONFIG_MACH_ASM9260) += \ alphascale-asm9260-devkit.dtb # Keep at91 dtb files sorted alphabetically for each SoC @@ -42,6 +44,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ sama5d34ek.dtb \ sama5d35ek.dtb \ sama5d36ek.dtb \ + at91-sama5d4_xplained.dtb \ at91-sama5d4ek.dtb dtb-$(CONFIG_ARCH_ATLAS6) += \ atlas6-evb.dtb @@ -59,13 +62,15 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-netgear-r6300-v2.dtb \ bcm47081-asus-rt-n18u.dtb \ bcm47081-buffalo-wzr-600dhp2.dtb \ - bcm47081-buffalo-wzr-900dhp.dtb + bcm47081-buffalo-wzr-900dhp.dtb \ + bcm4709-netgear-r8000.dtb dtb-$(CONFIG_ARCH_BCM_63XX) += \ bcm963138dvt.dtb dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ bcm911360_entphn.dtb \ bcm911360k.dtb \ - bcm958300k.dtb + bcm958300k.dtb \ + bcm958305k.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ bcm28155-ap.dtb \ bcm21664-garnet.dtb @@ -165,6 +170,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-lsxhl.dtb \ kirkwood-mplcec4.dtb \ kirkwood-mv88f6281gtw-ge.dtb \ + kirkwood-nas2big.dtb \ kirkwood-net2big.dtb \ kirkwood-net5big.dtb \ kirkwood-netgear_readynas_duo_v2.dtb \ @@ -199,6 +205,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \ ea3250.dtb phy3250.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb +dtb-$(CONFIG_MACH_MESON8) += \ + meson8-minix-neo-x8.dtb dtb-$(CONFIG_ARCH_MMP) += \ pxa168-aspenite.dtb \ pxa910-dkb.dtb \ @@ -215,7 +223,7 @@ dtb-$(CONFIG_SOC_IMX25) += \ imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ imx25-karo-tx25.dtb \ imx25-pdk.dtb -dtb-$(CONFIG_SOC_IMX31) += \ +dtb-$(CONFIG_SOC_IMX27) += \ imx27-apf27.dtb \ imx27-apf27dev.dtb \ imx27-eukrea-mbimxsd27-baseboard.dtb \ @@ -299,9 +307,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ - imx6sl-evk.dtb + imx6sl-evk.dtb \ + imx6sl-warp.dtb dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sabreauto.dtb \ + imx6sx-sdb-reva.dtb \ imx6sx-sdb.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-qds.dtb \ @@ -386,6 +396,8 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ omap3-overo-storm-tobi.dtb \ omap3-overo-summit.dtb \ omap3-overo-tobi.dtb \ + omap3-pandora-600mhz.dtb \ + omap3-pandora-1ghz.dtb \ omap3-sbc-t3517.dtb \ omap3-sbc-t3530.dtb \ omap3-sbc-t3730.dtb \ @@ -401,7 +413,8 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-evmsk.dtb \ am335x-nano.dtb \ am335x-pepper.dtb \ - am335x-lxm.dtb + am335x-lxm.dtb \ + am335x-chiliboard.dtb dtb-$(CONFIG_ARCH_OMAP4) += \ omap4-duovero-parlor.dtb \ omap4-panda.dtb \ @@ -464,25 +477,23 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-smdkv210.dtb \ s5pv210-torbreck.dtb dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ - r8a73a4-ape6evm.dtb \ - r8a73a4-ape6evm-reference.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ r8a7778-bockw-reference.dtb \ r8a7779-marzen.dtb \ - sh7372-mackerel.dtb \ - sh73a0-kzm9g.dtb \ - sh73a0-kzm9g-reference.dtb + sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ emev2-kzm9d.dtb \ r7s72100-genmai.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ r8a7791-henninger.dtb \ r8a7791-koelsch.dtb \ - r8a7794-alt.dtb + r8a7794-alt.dtb \ + sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk.dtb \ @@ -577,6 +588,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ + tegra124-nyan-blaze.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_U300) += \ ste-u300.dtb @@ -624,11 +636,14 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-388-db.dtb \ armada-388-gp.dtb \ armada-388-rd.dtb +dtb-$(CONFIG_MACH_ARMADA_39X) += \ + armada-398-db.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ armada-xp-gp.dtb \ armada-xp-lenovo-ix4-300d.dtb \ + armada-xp-linksys-mamba.dtb \ armada-xp-matrix.dtb \ armada-xp-netgear-rn2120.dtb \ armada-xp-openblocks-ax3-4.dtb \ diff --git a/arch/arm/boot/dts/alpine-db.dts b/arch/arm/boot/dts/alpine-db.dts new file mode 100644 index 0000000000000000000000000000000000000000..dfb5a08022732ef629053bb85813e836e02d1d87 --- /dev/null +++ b/arch/arm/boot/dts/alpine-db.dts @@ -0,0 +1,35 @@ +/* + * Copyright 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * Alternatively, redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "alpine.dtsi" + +/ { + model = "Annapurna Labs Alpine Dev Board"; + /* no need for anything outside SOC */ +}; + diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..9af2d60e9a7f6edb33e0193b81f99d6cbefd134c --- /dev/null +++ b/arch/arm/boot/dts/alpine.dtsi @@ -0,0 +1,160 @@ +/* + * Copyright 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * Alternatively, redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include "skeleton64.dtsi" + +/ { + /* SOC compatibility */ + compatible = "al,alpine"; + + /* CPU Configuration */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "al,alpine-smp"; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <0>; /* Filled by loader */ + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + clock-frequency = <0>; /* Filled by loader */ + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + clock-frequency = <0>; /* Filled by loader */ + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + clock-frequency = <0>; /* Filled by loader */ + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + arch-timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = + , + , + , + ; + clock-frequency = <0>; /* Filled by loader */ + }; + + /* Interrupt Controller */ + gic: gic@fb001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfb001000 0x0 0x1000>, + <0x0 0xfb002000 0x0 0x2000>, + <0x0 0xfb004000 0x0 0x1000>, + <0x0 0xfb006000 0x0 0x2000>; + interrupts = + ; + }; + + /* CPU Resume registers */ + cpu-resume@fbff5ec0 { + compatible = "al,alpine-cpu-resume"; + reg = <0x0 0xfbff5ec0 0x0 0x30>; + }; + + /* North Bridge Service Registers */ + sysfabric-service@fb070000 { + compatible = "al,alpine-sysfabric-service", "syscon"; + reg = <0x0 0xfb070000 0x0 0x10000>; + }; + + /* Performance Monitor Unit */ + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + , + , + ; + }; + + uart0:uart@fd883000 { + compatible = "ns16550a"; + reg = <0x0 0xfd883000 0x0 0x1000>; + clock-frequency = <0>; /* Filled by loader */ + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1:uart@0xfd884000 { + compatible = "ns16550a"; + reg = <0x0 0xfd884000 0x0 0x1000>; + clock-frequency = <0>; /* Filled by loader */ + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + /* Internal PCIe Controller */ + pcie-internal@0xfbc00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + #interrupt-cells = <1>; + reg = <0x0 0xfbc00000 0x0 0x100000>; + interrupt-map-mask = <0xf800 0 0 7>; + /* Add legacy interrupts for SATA devices only */ + interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, + <0x4800 0 0 1 &gic 0 44 4>; + + /* 32 bit non prefetchable memory space */ + ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; + + bus-range = <0x00 0x00>; + }; + }; +}; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index c3255e0c90aa829fc792f02d1265d413f3c6e624..dbb3f4d2bf84ebf4565555949053c94619ea161d 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -223,6 +223,25 @@ tps: tps@24 { /include/ "tps65217.dtsi" &tps { + /* + * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only + * mode") at poweroff. Most BeagleBone versions do not support RTC-only + * mode and risk hardware damage if this mode is entered. + * + * For details, see linux-omap mailing list May 2015 thread + * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller + * In particular, messages: + * http://www.spinics.net/lists/linux-omap/msg118585.html + * http://www.spinics.net/lists/linux-omap/msg118615.html + * + * You can override this later with + * &tps { /delete-property/ ti,pmic-shutdown-controller; } + * if you want to use RTC-only mode and made sure you are not affected + * by the hardware problems. (Tip: double-check by performing a current + * measurement after shutdown: it should be less than 1 mA.) + */ + ti,pmic-shutdown-controller; + regulators { dcdc1_reg: regulator@0 { regulator-name = "vdds_dpr"; diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 5c42d259fa68fbf29c98439306badd1d44987ee0..901739fcb85a37abba32822463caea432637d274 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -80,7 +80,3 @@ hdmi { status = "okay"; }; }; - -&rtc { - system-power-controller; -}; diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts new file mode 100644 index 0000000000000000000000000000000000000000..310da20a8aa765f8a9e5a2d61c17c028b04263ff --- /dev/null +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Author: Rostislav Lisovy + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; +#include "am335x-chilisom.dtsi" + +/ { + model = "AM335x Chiliboard"; + compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", + "ti,am33xx"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_gpio_pins>; + + led0 { + label = "led0"; + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "led1"; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; +}; + +&am33xx_pinmux { + usb1_drvvbus: usb1_drvvbus { + pinctrl-single,pins = < + 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + >; + }; + + sd_pins: pinmux_sd_card { + pinctrl-single,pins = < + 0xf0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + 0xf4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + 0xf8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + 0xfc (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + led_gpio_pins: led_gpio_pins { + pinctrl-single,pins = < + 0x1e4 (PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */ + 0x1e8 (PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */ + >; + }; +}; + +&ldo4_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* Ethernet */ +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +/* USB */ +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_drvvbus>; + + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +/* microSD */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins>; + vmmc-supply = <&ldo4_reg>; + bus-width = <0x4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..7e9a34dffe2113c6bdff809d0ee23a1830062800 --- /dev/null +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Author: Rostislav Lisovy + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "am33xx.dtsi" + +/ { + model = "Grinn AM335x ChiliSOM"; + compatible = "grinn,am335x-chilisom", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* mdio_data.mdio_data */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) + /* mdio_clk.mdio_clk */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + nandflash_pins: nandflash_pins { + pinctrl-single,pins = < + 0x00 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x04 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x08 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0x0c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + +}; + +/include/ "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3d"; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +/* Ethernet MAC */ +&mac { + slaves = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +/* NAND Flash */ +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ + nand@0,0 { + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + }; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index df5fee6b6b4bcf7ac58d33fc1d25b58cb07890a8..156d05efcb70bf5af737cf67892691d41b84fb2b 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -15,6 +15,7 @@ #include "am33xx.dtsi" #include +#include / { model = "TI AM335x EVM-SK"; @@ -647,6 +648,16 @@ &mmc2 { cap-power-off-card; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */ + ref-clock-frequency = <38400000>; + }; }; &mcasp1 { diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index a3466455b17188eaafec7eab8b613550a264d3da..5ed4ca6eaf55b6ea0adeae9f0ea635fce453a6ef 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -213,7 +213,9 @@ &i2c0 { pinctrl-0 = <&i2c0_pins>; gpio@20 { - compatible = "mcp,mcp23017"; + compatible = "microchip,mcp23017"; + gpio-controller; + #gpio-cells = <2>; reg = <0x20>; }; @@ -222,7 +224,7 @@ tps: tps@24 { }; eeprom@53 { - compatible = "mcp,24c02"; + compatible = "microchip,24c02"; reg = <0x53>; pagesize = <8>; }; @@ -297,8 +299,8 @@ MTD partition table | |-->0x004FFFFF-> Kernel end | |-->0x00500000-> File system start | | - | |-->0x014FFFFF-> File system end - | |-->0x01500000-> User data start + | |-->0x01FFFFFF-> File system end + | |-->0x02000000-> User data start | | | |-->0x03FFFFFF-> User data end | |-->0x04000000-> Data storage start @@ -327,12 +329,12 @@ partition@3 { partition@4 { label = "rootfs"; - reg = <0x00500000 0x01000000>; /* 16MB */ + reg = <0x00500000 0x01b00000>; /* 27MB */ }; partition@5 { label = "user"; - reg = <0x01500000 0x02b00000>; /* 43MB */ + reg = <0x02000000 0x02000000>; /* 32MB */ }; partition@6 { @@ -343,7 +345,7 @@ partition@6 { }; &mac { - dual_emac = <1>; + dual_emac; status = "okay"; }; @@ -353,11 +355,13 @@ &davinci_mdio { &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; dual_emac_res_vlan = <2>; }; diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 071b56aa0c7e05fd18201b25ba75836edb9aed5e..afb4b3a7bab47b5e426e4e9a25f1a6dd4ec4f360 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -7,7 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { sys_clkin_ck: sys_clkin_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index acd37057bca94377e5f092a754ee9cece5dede8a..21fcc440fc1a9d886d408701a705ad4daabd2325 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -83,20 +83,6 @@ mpu { }; }; - am33xx_control_module: control_module@4a002000 { - compatible = "syscon"; - reg = <0x44e10000 0x7fc>; - }; - - am33xx_pinmux: pinmux@44e10800 { - compatible = "pinctrl-single"; - reg = <0x44e10800 0x0238>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7f>; - }; - /* * XXX: Use a flat representation of the AM33XX interconnect. * The real AM33XX interconnect network is quite complex. Since @@ -111,37 +97,58 @@ ocp { ranges; ti,hwmods = "l3_main"; - prcm: prcm@44e00000 { - compatible = "ti,am3-prcm"; - reg = <0x44e00000 0x4000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + l4_wkup: l4_wkup@44c00000 { + compatible = "ti,am3-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x44c00000 0x280000>; - prcm_clockdomains: clockdomains { - }; - }; + prcm: prcm@200000 { + compatible = "ti,am3-prcm"; + reg = <0x200000 0x4000>; - scrm: scrm@44e10000 { - compatible = "ti,am3-scrm"; - reg = <0x44e10000 0x2000>; + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; + prcm_clockdomains: clockdomains { + }; }; - scrm_clockdomains: clockdomains { + scm: scm@210000 { + compatible = "ti,am3-scm", "simple-bus"; + reg = <0x210000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x210000 0x2000>; + + am33xx_pinmux: pinmux@800 { + compatible = "pinctrl-single"; + reg = <0x800 0x238>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + }; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; }; }; - cm: syscon@44e10000 { - compatible = "ti,am33xx-controlmodule", "syscon"; - reg = <0x44e10000 0x800>; - }; - intc: interrupt-controller@48200000 { compatible = "ti,am33xx-intc"; interrupt-controller; @@ -350,7 +357,7 @@ dcan0: can@481cc000 { reg = <0x481cc000 0x2000>; clocks = <&dcan0_fck>; clock-names = "fck"; - syscon-raminit = <&am33xx_control_module 0x644 0>; + syscon-raminit = <&scm_conf 0x644 0>; interrupts = <52>; status = "disabled"; }; @@ -361,7 +368,7 @@ dcan1: can@481d0000 { reg = <0x481d0000 0x2000>; clocks = <&dcan1_fck>; clock-names = "fck"; - syscon-raminit = <&am33xx_control_module 0x644 1>; + syscon-raminit = <&scm_conf 0x644 1>; interrupts = <55>; status = "disabled"; }; @@ -720,7 +727,7 @@ mac: ethernet@4a100000 { */ interrupts = <40 41 42 43>; ranges; - syscon = <&cm>; + syscon = <&scm_conf>; status = "disabled"; davinci_mdio: mdio@4a101000 { diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index c90724bded1081b7ea6e22461451e39d48828cec..f164dce08755cc5866b79133050db9f808cafce9 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -31,7 +31,7 @@ davinci_emac: ethernet@0x5c000000 { status = "disabled"; reg = <0x5c000000 0x30000>; interrupts = <67 68 69 70>; - syscon = <&omap3_scm_general>; + syscon = <&scm_conf>; ti,davinci-ctrl-reg-offset = <0x10000>; ti,davinci-ctrl-mod-reg-offset = <0>; ti,davinci-ctrl-ram-offset = <0x20000>; diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi index df489d310b50aa0ad01f7750cb6fb17ea36da540..18cc826e9db534714a1b4d8a3cfc497e43ffcc85 100644 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -7,12 +7,12 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { emac_ick: emac_ick { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>; - reg = <0x059c>; + reg = <0x032c>; ti,bit-shift = <1>; }; @@ -20,7 +20,7 @@ emac_fck: emac_fck { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&rmii_ck>; - reg = <0x059c>; + reg = <0x032c>; ti,bit-shift = <9>; }; @@ -28,7 +28,7 @@ vpfe_ick: vpfe_ick { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>; - reg = <0x059c>; + reg = <0x032c>; ti,bit-shift = <2>; }; @@ -36,7 +36,7 @@ vpfe_fck: vpfe_fck { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&pclk_ck>; - reg = <0x059c>; + reg = <0x032c>; ti,bit-shift = <10>; }; @@ -44,7 +44,7 @@ hsotgusb_ick_am35xx: hsotgusb_ick_am35xx { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>; - reg = <0x059c>; + reg = <0x032c>; ti,bit-shift = <0>; }; @@ -52,7 +52,7 @@ hsotgusb_fck_am35xx: hsotgusb_fck_am35xx { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_ck>; - reg = <0x059c>; + reg = <0x032c>; ti,bit-shift = <8>; }; @@ -60,7 +60,7 @@ hecc_ck: hecc_ck { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&sys_ck>; - reg = <0x059c>; + reg = <0x032c>; ti,bit-shift = <3>; }; }; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 8a099bc10c1e4579e765819d2f87bd92bec8e4a5..c80a3e23379213f67fa92fa7a5ba62f3b44c01c2 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -66,22 +66,6 @@ l2-cache-controller@48242000 { cache-level = <2>; }; - am43xx_control_module: control_module@4a002000 { - compatible = "syscon"; - reg = <0x44e10000 0x7f4>; - }; - - am43xx_pinmux: pinmux@44e10800 { - compatible = "ti,am437-padconf", "pinctrl-single"; - reg = <0x44e10800 0x31c>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - ocp { compatible = "ti,am4372-l3-noc", "simple-bus"; #address-cells = <1>; @@ -93,29 +77,58 @@ ocp { interrupts = , ; - prcm: prcm@44df0000 { - compatible = "ti,am4-prcm"; - reg = <0x44df0000 0x11000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + l4_wkup: l4_wkup@44c00000 { + compatible = "ti,am4-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x44c00000 0x287000>; - prcm_clockdomains: clockdomains { - }; - }; + prcm: prcm@1f0000 { + compatible = "ti,am4-prcm"; + reg = <0x1f0000 0x11000>; - scrm: scrm@44e10000 { - compatible = "ti,am4-scrm"; - reg = <0x44e10000 0x2000>; + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; + prcm_clockdomains: clockdomains { + }; }; - scrm_clockdomains: clockdomains { + scm: scm@210000 { + compatible = "ti,am4-scm", "simple-bus"; + reg = <0x210000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x210000 0x4000>; + + am43xx_pinmux: pinmux@800 { + compatible = "ti,am437-padconf", + "pinctrl-single"; + reg = <0x800 0x31c>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; }; }; @@ -796,7 +809,7 @@ am43xx_control_usb2phy2: control-phy@0x44e10628 { }; ocp2scp0: ocp2scp@483a8000 { - compatible = "ti,omap-ocp2scp"; + compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -815,7 +828,7 @@ usb2_phy1: phy@483a8000 { }; ocp2scp1: ocp2scp@483e8000 { - compatible = "ti,omap-ocp2scp"; + compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -893,7 +906,7 @@ qspi: qspi@47900000 { }; hdq: hdq@48347000 { - compatible = "ti,am43xx-hdq"; + compatible = "ti,am4372-hdq"; reg = <0x48347000 0x1000>; interrupts = ; clocks = <&func_12m_clk>; @@ -942,7 +955,7 @@ dcan0: can@481cc000 { clocks = <&dcan0_fck>; clock-names = "fck"; reg = <0x481cc000 0x2000>; - syscon-raminit = <&am43xx_control_module 0x644 0>; + syscon-raminit = <&scm_conf 0x644 0>; interrupts = ; status = "disabled"; }; @@ -953,7 +966,7 @@ dcan1: can@481d0000 { clocks = <&dcan1_fck>; clock-names = "fck"; reg = <0x481d0000 0x2000>; - syscon-raminit = <&am43xx_control_module 0x644 1>; + syscon-raminit = <&scm_conf 0x644 1>; interrupts = ; status = "disabled"; }; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 0198f5a62b96cd8b8569d4ae5d6dfd2938fcd580..378344271746f20446cc8654c52fd2ef46c5cda2 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -133,6 +133,20 @@ i2c0_pins_sleep: i2c0_pins_sleep { >; }; + i2c2_pins_default: i2c2_pins_default { + pinctrl-single,pins = < + 0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ + 0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ + >; + }; + + i2c2_pins_sleep: i2c2_pins_sleep { + pinctrl-single,pins = < + 0x1e8 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1ec (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + mmc1_pins_default: pinmux_mmc1_pins_default { pinctrl-single,pins = < 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ @@ -263,6 +277,14 @@ tps: tps62362@60 { }; }; +&i2c2 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_default>; + pinctrl-1 = <&i2c2_pins_sleep>; + clock-frequency = <100000>; +}; + &epwmss0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 8ae29c955c11d7f83f4423184a8ed61412b515dd..c17097d2c167d4718f76200f51e599d6605d144e 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -49,7 +49,7 @@ matrix_keypad: matrix_keypad@0 { pinctrl-0 = <&matrix_keypad_pins>; debounce-delay-ms = <5>; - col-scan-delay-us = <1500>; + col-scan-delay-us = <5>; row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ @@ -473,7 +473,7 @@ edt-ft5306@38 { interrupt-parent = <&gpio0>; interrupts = <31 0>; - wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; touchscreen-size-x = <480>; touchscreen-size-y = <272>; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 1d7109196872299464ccfb5f3a1938b76e4f68ef..795d68af6df9dbcf9b09b71350e7816606f7994a 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -69,7 +69,48 @@ lcd_in: endpoint { }; }; - am43xx_pinmux: pinmux@44e10800 { + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ + &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ + &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ + &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ + + col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ + &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ + &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ + &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ + + linux,keymap = <0x00000201 /* P1 */ + 0x01000204 /* P4 */ + 0x02000207 /* P7 */ + 0x0300020a /* NUMERIC_STAR */ + 0x00010202 /* P2 */ + 0x01010205 /* P5 */ + 0x02010208 /* P8 */ + 0x03010200 /* P0 */ + 0x00020203 /* P3 */ + 0x01020206 /* P6 */ + 0x02020209 /* P9 */ + 0x0302020b /* NUMERIC_POUND */ + 0x00030067 /* UP */ + 0x0103006a /* RIGHT */ + 0x0203006c /* DOWN */ + 0x03030069>; /* LEFT */ + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; +}; + +&am43xx_pinmux { cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ @@ -279,47 +320,6 @@ vpfe1_pins_sleep: vpfe1_pins_sleep { 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) >; }; - }; - - matrix_keypad: matrix_keypad@0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ - &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ - &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ - &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ - - col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ - &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ - &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ - &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ - - linux,keymap = <0x00000201 /* P1 */ - 0x01000204 /* P4 */ - 0x02000207 /* P7 */ - 0x0300020a /* NUMERIC_STAR */ - 0x00010202 /* P2 */ - 0x01010205 /* P5 */ - 0x02010208 /* P8 */ - 0x03010200 /* P0 */ - 0x00020203 /* P3 */ - 0x01020206 /* P6 */ - 0x02020209 /* P9 */ - 0x0302020b /* NUMERIC_POUND */ - 0x00030067 /* UP */ - 0x0103006a /* RIGHT */ - 0x0203006c /* DOWN */ - 0x03030069>; /* LEFT */ - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; }; &mmc1 { diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index cfb49686ab6af02ba7086e344869ee9ad457a2aa..d0c0dfa4ec486e5927abda3d9f4189435a51d23e 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -7,7 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { sys_clkin_ck: sys_clkin_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index bd48dba1674865878049e7786e28c7b720feb0cf..7128fad991ac3459ac5349b0219e893fab1830c8 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -8,7 +8,6 @@ /dts-v1/; #include "dra74x.dtsi" -#include #include #include @@ -19,6 +18,7 @@ / { aliases { rtc0 = &mcp_rtc; rtc1 = &tps659038_rtc; + rtc2 = &rtc; }; memory { @@ -84,9 +84,10 @@ led@3 { gpio_fan: gpio_fan { /* Based on 5v 500mA AFB02505HHB */ compatible = "gpio-fan"; - gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>; + gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0>, <13000 1>; + #cooling-cells = <2>; }; extcon_usb1: extcon_usb1 { @@ -130,8 +131,8 @@ i2c3_pins_default: i2c3_pins_default { uart3_pins_default: uart3_pins_default { pinctrl-single,pins = < - 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */ - 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */ + 0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */ + 0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */ >; }; @@ -442,6 +443,7 @@ tmp102: tmp102@48 { pinctrl-0 = <&tmp102_pins_default>; interrupt-parent = <&gpio7>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; }; }; @@ -454,7 +456,7 @@ &i2c3 { mcp_rtc: rtc@6f { compatible = "microchip,mcp7941x"; reg = <0x6f>; - interrupts = ; /* IRQ_SYS_1N */ + interrupts = ; /* IRQ_SYS_1N */ pinctrl-names = "default"; pinctrl-0 = <&mcp79410_pins_default>; @@ -477,7 +479,7 @@ &cpu0 { &uart3 { status = "okay"; interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x248>; + <&dra7_pmx_core 0x3f8>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins_default>; @@ -548,6 +550,61 @@ &usb1 { pinctrl-0 = <&usb1_pins>; }; +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + &usb2 { dr_mode = "peripheral"; }; + +&cpu_trips { + cpu_alert1: cpu_alert1 { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; +}; + +&cpu_cooling_maps { + map1 { + trip = <&cpu_alert1>; + cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&thermal_zones { + board_thermal: board_thermal { + polling-delay-passive = <1250>; /* milliseconds */ + polling-delay = <1500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tmp102 0>; + + board_trips: trips { + board_alert0: board_alert { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + + board_crit: board_crit { + temperature = <105000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + board_cooling_maps: cooling-maps { + map0 { + trip = <&board_alert0>; + cooling-device = + <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index e993c46bd47273b247d80f49c0521c08e06767d5..19f3bf271915fc1dd843a7d10d50df353b4b52d2 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -45,6 +45,15 @@ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. */ /dts-v1/; @@ -55,7 +64,7 @@ / { compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { @@ -64,7 +73,7 @@ memory { }; soc { - ranges = ; internal-regs { diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index b10ceb488efe5d5aec3b8e91241ae6172e206564..0f40d5da28c3c30ec83a27bacbf9332d9ad23c41 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -51,7 +51,7 @@ / { compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 3f8cc3845a5e9423f0536ee3c201af4a1b8c5e51..a31207860f34ea385cee3d241c1c902a48d7d6a2 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -53,7 +53,7 @@ / { compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 99eb8a014ac631df0a26b992f571be829c467411..00540f292979c57e4107ca4b4b9ef51c89e28009 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -53,7 +53,7 @@ / { compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 6ae36a38beb25b8b1f9930f74dcb250173c627e7..19475e68b8e9246ef5220e0ec3857e5bee4b2192 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -64,7 +64,7 @@ / { compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts index 59f74e66963f164b7949f41dc6a520077e2d7fd8..b42b767763aaa41c5a96420e4415efc7683adb16 100644 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -67,8 +67,7 @@ / { "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 8a322ad57e5fbb0bd0ef15ca19f4387169abeb03..ec96f0b3634653a5976739688eca9fd791eaba0b 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -59,8 +59,8 @@ / { compatible = "marvell,armada-370-xp"; aliases { - eth0 = ð0; - eth1 = ð1; + serial0 = &uart0; + serial1 = &uart1; }; cpus { @@ -73,6 +73,11 @@ cpu@0 { }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + soc { #address-cells = <2>; #size-cells = <1>; @@ -223,7 +228,7 @@ mbusc: mbus-controller@20000 { <0x20250 0x8>; }; - mpic: interrupt-controller@20000 { + mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; #interrupt-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 27397f151def76d9560a6855c87f2ea7afc052bd..00b50db57c9c0f7ab4111bbdba06d3fd0bdc93ad 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -129,6 +129,7 @@ L2: l2-cache { compatible = "marvell,aurora-outer-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-level = <2>; cache-unified; wt-override; }; @@ -232,7 +233,7 @@ sscg@18330 { reg = <0x18330 0x4>; }; - interrupt-controller@20000 { + interrupt-controller@20a00 { reg = <0x20a00 0x1d0>, <0x21870 0x58>; }; diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts index 0440891425c0408723c6ea75db1518105328f2db..4eabc9c21f8dc1e84f399edb6e56a2bdf992a7ed 100644 --- a/arch/arm/boot/dts/armada-375-db.dts +++ b/arch/arm/boot/dts/armada-375-db.dts @@ -55,7 +55,7 @@ / { compatible = "marvell,a375-db", "marvell,armada375"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index ba3c57e0af72ac577d2e82fa3d9536569dd98e24..f076ff856d8b8223466f3ec8536caaa1974186ca 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -60,8 +60,8 @@ aliases { gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; - ethernet0 = ð0; - ethernet1 = ð1; + serial0 = &uart0; + serial1 = &uart1; }; clocks { @@ -69,7 +69,7 @@ clocks { mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <2000000000>; + clock-frequency = <1000000000>; }; /* 25 MHz reference crystal */ refclk: oscillator { @@ -96,6 +96,11 @@ cpu@1 { }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + soc { compatible = "marvell,armada375-mbus", "simple-bus"; #address-cells = <2>; @@ -276,7 +281,7 @@ i2c1: i2c@11100 { status = "disabled"; }; - serial@12000 { + uart0: serial@12000 { compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; @@ -286,7 +291,7 @@ serial@12000 { status = "disabled"; }; - serial@12100 { + uart1: serial@12100 { compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; @@ -394,7 +399,7 @@ mbusc: mbus-controller@20000 { reg = <0x20000 0x100>, <0x20180 0x20>; }; - mpic: interrupt-controller@20000 { + mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index 57b9119fb3e05e974ee8931286d2635ab57110fe..7219ac3a3d900743114fd7d9001748118695515e 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -49,8 +49,7 @@ / { compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x"; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart1; + stdout-path = "serial1:115200n8"; }; memory { @@ -126,6 +125,13 @@ uart1: serial@12100 { status = "okay"; }; + pinctrl@18000 { + xhci0_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + }; + ethernet@30000 { status = "okay"; phy = <&phy2>; @@ -150,6 +156,24 @@ ethernet@70000 { phy = <&phy0>; phy-mode = "rgmii-id"; }; + + nfc: flash@d0000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + + num-cs = <1>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; + + usb3@f0000 { + status = "okay"; + usb-phy = <&usb3_phy>; + }; }; pcie-controller { @@ -175,4 +199,20 @@ pcie@3,0 { }; }; }; + + usb3_phy: usb3_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_xhci0_vbus>; + }; + + reg_xhci0_vbus: xhci0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&xhci0_vbus_pins>; + regulator-name = "xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; }; diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts index 16512efcd32c091702a9a99c6ea93139598b8a5f..51d1623de53e6967750b6c602ccaeef40359a535 100644 --- a/arch/arm/boot/dts/armada-388-db.dts +++ b/arch/arm/boot/dts/armada-388-db.dts @@ -54,7 +54,7 @@ / { "marvell,armada385", "marvell,armada380"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { @@ -99,7 +99,7 @@ ethernet@30000 { phy-mode = "rgmii-id"; }; - usb@50000 { + usb@58000 { status = "ok"; }; diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts index 590b383db323a75a1041080951d32dbf27e3e9fa..78514ab0b47ace058f49b0da052d131374a8f5d2 100644 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -48,8 +48,7 @@ / { compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380"; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; memory { @@ -135,7 +134,7 @@ ethernet@30000 { }; /* CON4 */ - usb@50000 { + usb@58000 { vcc-supply = <®_usb2_0_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts index d99baac72081b6873532bec2d2587c769a581040..1dc6e2341cc2853829abb077441b27f2cfe4456e 100644 --- a/arch/arm/boot/dts/armada-388-rd.dts +++ b/arch/arm/boot/dts/armada-388-rd.dts @@ -55,7 +55,7 @@ / { "marvell,armada385","marvell,armada380"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { @@ -85,6 +85,16 @@ i2c@11000 { clock-frequency = <100000>; }; + sdhci@d8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + broken-cd; + no-1-8-v; + wp-inverted; + bus-width = <8>; + status = "okay"; + }; + serial@12000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 1dff30a81e247a12ecd88f1c37b2b8dd6a55d2c1..218a2acd36e509b0de8e22dc207e06253b1163fe 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -59,9 +59,13 @@ / { aliases { gpio0 = &gpio0; gpio1 = &gpio1; - ethernet0 = ð0; - ethernet1 = ð1; - ethernet2 = ð2; + serial0 = &uart0; + serial1 = &uart1; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; }; soc { @@ -216,7 +220,7 @@ uart0: serial@12000 { status = "disabled"; }; - serial@12100 { + uart1: serial@12100 { compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; @@ -368,7 +372,7 @@ mbusc: mbus-controller@20000 { reg = <0x20000 0x100>, <0x20180 0x20>; }; - mpic: interrupt-controller@20000 { + mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; @@ -435,7 +439,7 @@ eth2: ethernet@34000 { status = "disabled"; }; - usb@50000 { + usb@58000 { compatible = "marvell,orion-ehci"; reg = <0x58000 0x500>; interrupts = ; @@ -548,8 +552,11 @@ flash@d0000 { sdhci@d8000 { compatible = "marvell,armada-380-sdhci"; - reg = <0xd8000 0x1000>, <0xdc000 0x100>; - interrupts = <0 25 0x4>; + reg-names = "sdhci", "mbus", "conf-sdio3"; + reg = <0xd8000 0x1000>, + <0xdc000 0x100>, + <0x18454 0x4>; + interrupts = ; clocks = <&gateclk 17>; mrvl,clk-delay-cycles = <0x1F>; status = "disabled"; @@ -578,7 +585,7 @@ clocks { mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <2000000000>; + clock-frequency = <1000000000>; }; /* 25 MHz reference crystal */ diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..094e39c660390440501dce7e64dfdda4b8268a37 --- /dev/null +++ b/arch/arm/boot/dts/armada-390.dtsi @@ -0,0 +1,57 @@ +/* + * Device Tree Include file for Marvell Armada 390 SoC. + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armada-39x.dtsi" + +/ { + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6920-pinctrl"; + reg = <0x18000 0x20>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts new file mode 100644 index 0000000000000000000000000000000000000000..bbf83756c43c3b8fe9358de92ba6019221096f8c --- /dev/null +++ b/arch/arm/boot/dts/armada-398-db.dts @@ -0,0 +1,153 @@ +/* + * Device Tree Include file for Marvell Armada 398 Development Board + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-398.dtsi" + +/ { + model = "Marvell Armada 398 Development Board"; + compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = ; + + internal-regs { + spi@10680 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "n25q128a13"; + reg = <0>; + spi-max-frequency = <108000000>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0x1000000>; + }; + }; + }; + + i2c@11000 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = <100000>; + }; + + serial@12000 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + serial@12100 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + flash@d0000 { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + + pcie@2,0 { + status = "okay"; + }; + + pcie@3,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..fdc25914e3a3936a41e5421f4200040c06f5a83e --- /dev/null +++ b/arch/arm/boot/dts/armada-398.dtsi @@ -0,0 +1,60 @@ +/* + * Device Tree Include file for Marvell Armada 398 SoC. + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armada-39x.dtsi" + +/ { + compatible = "marvell,armada398", "marvell,armada390"; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6928-pinctrl"; + reg = <0x18000 0x20>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..ecd1318109bac8fb5d1e29c96f7c30779d217fda --- /dev/null +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -0,0 +1,508 @@ +/* + * Device Tree Include file for Marvell Armada 39x family of SoCs. + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" +#include +#include + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + model = "Marvell Armada 39x family SoC"; + compatible = "marvell,armada390"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-390-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&gic>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + L2: cache-controller@8000 { + compatible = "arm,pl310-cache"; + reg = <0x8000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + scu@c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc000 0x100>; + }; + + timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; + interrupts = ; + clocks = <&coreclk 2>; + }; + + gic: interrupt-controller@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + reg = <0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,orion-spi"; + reg = <0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c2: i2c@11200 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11200 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c3: i2c@11300 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11300 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + pinctrl@18000 { + i2c0_pins: i2c0-pins { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "i2c0"; + }; + + uart0_pins: uart0-pins { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "ua0"; + }; + + uart1_pins: uart1-pins { + marvell,pins = "mpp19", "mpp20"; + marvell,function = "ua1"; + }; + + spi1_pins: spi1-pins { + marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; + marvell,function = "spi1"; + }; + + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", + "mpp38", "mpp28", "mpp40", "mpp42", + "mpp35", "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + }; + + system-controller@18200 { + compatible = "marvell,armada-390-system-controller", + "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-390-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + coreclk: mvebu-sar@18600 { + compatible = "marvell,armada-390-core-clock"; + reg = <0x18600 0x04>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; + }; + + mpic: interrupt-controller@20a00 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + interrupts = ; + }; + + timer@20300 { + compatible = "marvell,armada-380-timer", + "marvell,armada-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <&mpic 5>, + <&mpic 6>; + clocks = <&coreclk 2>, <&coreclk 5>; + clock-names = "nbclk", "fixed"; + }; + + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x10>; + }; + + pmsu@22000 { + compatible = "marvell,armada-390-pmsu", + "marvell,armada-380-pmsu"; + reg = <0x22000 0x1000>; + }; + + xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor00 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor10 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + flash@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + clocks = <&coredivclk 0>; + status = "disabled"; + }; + + sdhci@d8000 { + compatible = "marvell,armada-380-sdhci"; + reg = <0xd8000 0x1000>, <0xdc000 0x100>; + interrupts = ; + clocks = <&gateclk 17>; + mrvl,clk-delay-cycles = <0x1F>; + status = "disabled"; + }; + + coredivclk: clock@e4250 { + compatible = "marvell,armada-390-corediv-clock", + "marvell,armada-380-corediv-clock"; + reg = <0xe4250 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; + + /* + * This port can be either x4 or x1. When + * configured in x4 by the bootloader, then + * pcie@4,0 is not available. + */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + /* x1 port */ + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + /* + * x1 port only available when pcie@1,0 is + * configured as a x1 port + */ + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + }; + }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index c1fbab2436095e28a72542abbe3111e1609e573d..dfd782b44e506b6fd34a8efbade76b9f94c001c6 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -59,7 +59,7 @@ / { compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 48bdafe17526ab7fa6960281cc2a7cdfdf2ee82e..1037824076189db621c58809ba539693be09e3e0 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -64,7 +64,7 @@ / { compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 206aebba01beea82a820163778bd4dc793cea05d..565227eacf06092d518d87cc2255a6e65093abaf 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -65,7 +65,7 @@ / { compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts index 5fb3c8b687cfad7100f7a1827197cb7811dca39e..06a6a6c1fdf709446ed713fd189a1471e6509fd3 100644 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts @@ -54,8 +54,7 @@ / { "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts new file mode 100644 index 0000000000000000000000000000000000000000..fdd187c55aa5f78b5ab61d15dc12c1ad001990d2 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -0,0 +1,398 @@ +/* + * Device Tree file for the Linksys WRT1900AC (Mamba). + * + * Note: this board is shipped with a new generation boot loader that + * remaps internal registers at 0xf1000000. Therefore, if earlyprintk + * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be + * used. + * + * Copyright (C) 2014 Imre Kaloz + * + * Based on armada-xp-axpwifiap.dts: + * + * Copyright (C) 2013 Marvell + * + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include +#include +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Linksys WRT1900AC"; + compatible = "linksys,mamba", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ + }; + + soc { + ranges = ; + + pcie-controller { + status = "okay"; + + /* Etron EJ168 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* First mini-PCIe port */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Second mini-PCIe port */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + }; + + internal-regs { + + rtc@10300 { + /* No crystal connected to the internal RTC */ + status = "disabled"; + }; + + /* J10: VCC, NC, RX, NC, TX, GND */ + serial@12000 { + status = "okay"; + }; + + sata@a0000 { + nr-ports = <1>; + status = "okay"; + }; + + ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + /* USB part of the eSATA/USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + tlc59116@68 { + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <2>; + compatible = "ti,tlc59116"; + reg = <0x68>; + + wan_amber@0 { + label = "mamba:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "mamba:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "mamba:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "mamba:white:wlan_5g"; + reg = <0x3>; + }; + + esata@4 { + label = "mamba:white:esata"; + reg = <0x4>; + }; + + usb2@5 { + label = "mamba:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "mamba:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "mamba:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "mamba:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "mamba:amber:wps"; + reg = <0x9>; + }; + }; + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; /* 1MB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x100000 0x40000>; /* 256KB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x140000 0x40000>; /* 256KB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MB */ + }; + + partition@d00000 { + label = "rootfs1"; + reg = <0xd00000 0x2500000>; /* 37MB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MB */ + }; + + partition@3500000 { + label = "rootfs2"; + reg = <0x3500000 0x2500000>; /* 37MB */ + }; + + /* + * 38MB, last MB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x180000 0x780000>; /* 7.5MB */ + }; + }; + + spi0: spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "everspin,mr25h256"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <40000000>; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&keys_pin>; + pinctrl-names = "default"; + + button@1 { + label = "WPS"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + + button@2 { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&power_led_pin>; + pinctrl-names = "default"; + + power { + label = "mamba:white:power"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio_fan { + /* SUNON HA4010V4-0000-C99 */ + compatible = "gpio-fan"; + gpios = <&gpio0 24 0>; + + gpio-fan,speed-map = <0 0 + 4500 1>; + }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0>; + dsa,mii-bus = <&mdio>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "internet"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; +}; + +&pinctrl { + + keys_pin: keys-pin { + marvell,pins = "mpp32", "mpp33"; + marvell,function = "gpio"; + }; + + power_led_pin: power-led-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + gpio_fan_pin: gpio-fan-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts index 56f958eb1ede07fb379f051ef12385ed5d1164d9..f894bc83e957554a55a8a155cc0cdb0c1d1d0d0e 100644 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ b/arch/arm/boot/dts/armada-xp-matrix.dts @@ -52,7 +52,7 @@ / { compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 4a7cbed79b0736f9c42670a6316bb4fadb37d398..8479fdc9e9c2468e072c3592528a263610c2acc1 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -57,7 +57,6 @@ aliases { gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; - eth3 = ð3; }; cpus { diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 36ce63a96cc9007bf18de678d117bbd99a78b739..661d54c815802d1bb1d2e1fa31cb255d90caf12e 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -57,7 +57,6 @@ aliases { gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; - eth3 = ð3; }; diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index 99cb9a8401b40737287ae15dbe7e67c0ffb2619d..1516fc2627f99f0d068fbc2d96c897c9112dc0e7 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -53,7 +53,7 @@ / { compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 0c76d9f05fd0c2e006df84f3fe7671a8ed29b52b..990e8a2100f0f3cff6c50989761d6b78838e4bd8 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -54,7 +54,7 @@ / { compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { @@ -105,6 +105,10 @@ pcie@1,0 { }; internal-regs { + rtc@10300 { + /* No crystal connected to the internal RTC */ + status = "disabled"; + }; serial@12000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index e9fb225169aaa7338e532006b7986779537da7ef..6063428fa6a0a8ca378d1a9f00b5689544947758 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -67,8 +67,7 @@ / { "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 82917236a2fbfe99426b5a70127255848a917d6a..013d63f69e361e60bbe96466bec1883388155889 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -57,7 +57,8 @@ / { compatible = "marvell,armadaxp", "marvell,armada-370-xp"; aliases { - eth2 = ð2; + serial2 = &uart2; + serial3 = &uart3; }; soc { @@ -78,6 +79,7 @@ L2: l2-cache { compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-level = <2>; cache-unified; wt-override; }; @@ -149,11 +151,11 @@ thermal@182b0 { cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,armada-xp-cpu-clock"; - reg = <0x18700 0xA0>, <0x1c054 0x10>; + reg = <0x18700 0x24>, <0x1c054 0x10>; clocks = <&coreclk 1>; }; - interrupt-controller@20000 { + interrupt-controller@20a00 { reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index fec1fca2ad66c80ad3ce949d82741b235790c1ed..9991240b7438663d184b6fa31eb04efb36fc3bdc 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -167,7 +167,13 @@ i2c2: i2c@f801c000 { macb1: ethernet@f802c000 { phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + }; }; dbgu: serial@ffffee00 { @@ -188,6 +194,11 @@ pinctrl_i2c2_pu: i2c2_pu { ; }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; + }; + pinctrl_mmc0_cd: mmc0_cd { atmel,pins = ; @@ -276,6 +287,9 @@ usb2: ehci@00700000 { gpio_keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + bp3 { label = "PB_USER"; gpios = <&pioE 29 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts new file mode 100644 index 0000000000000000000000000000000000000000..c740e1a2a3a5cac2c4d5bbe284815f2a705c8e17 --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -0,0 +1,241 @@ +/* + * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board + * + * Copyright (C) 2015 Atmel, + * 2015 Josh Wu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "sama5d4.dtsi" + +/ { + model = "Atmel SAMA5D4 Xplained"; + compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5"; + + chosen { + bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk"; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + spi0: spi@f8010000 { + cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; + status = "okay"; + m25p80@0 { + compatible = "atmel,at25df321a"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + i2c0: i2c@f8014000 { + status = "okay"; + }; + + macb0: ethernet@f8020000 { + phy-mode = "rmii"; + status = "okay"; + + phy0: ethernet-phy@1 { + interrupt-parent = <&pioE>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + reg = <1>; + }; + }; + + mmc1: mmc@fc000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 3 0>; + }; + }; + + usart3: serial@fc00c000 { + status = "okay"; + }; + + usart4: serial@fc010000 { + status = "okay"; + }; + + adc0: adc@fc034000 { + atmel,adc-vref = <3300>; + status = "okay"; + }; + + watchdog@fc068640 { + status = "okay"; + }; + + pinctrl@fc06a000 { + board { + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + ; + }; + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; + }; + }; + }; + }; + + usb0: gadget@00400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 11 GPIO_ACTIVE_HIGH + &pioE 14 GPIO_ACTIVE_HIGH + >; + status = "okay"; + }; + + usb2: ehci@00600000 { + status = "okay"; + }; + + nand0: nand@80000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + atmel,has-pmecc; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + d8 { + label = "d8"; + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + d10 { + label = "d10"; + gpios = <&pioE 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index 9198b719d0ef24d0ab4bef18ca7fd67a61dfd1df..89ef4a540db583015c2825d453e867afd9195852 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -115,6 +115,10 @@ slot@1 { }; }; + ssc0: ssc@f8008000 { + status = "okay"; + }; + spi0: spi@f8010000 { cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; status = "okay"; @@ -127,6 +131,13 @@ m25p80@0 { i2c0: i2c@f8014000 { status = "okay"; + + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck2>; + clock-names = "mclk"; + }; }; macb0: ethernet@f8020000 { @@ -171,6 +182,10 @@ pinctrl_mmc1_cd: mmc1_cd { atmel,pins = ; }; + pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { + atmel,pins = + ; + }; pinctrl_usba_vbus: usba_vbus { atmel,pins = ; @@ -244,8 +259,6 @@ rootfs@800000 { gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio>; @@ -257,4 +270,42 @@ pb_user1 { gpio-key,wakeup; }; }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + d8 { + label = "d8"; + /* PE28, conflicts with usart4 rts pin */ + gpios = <&pioE 28 GPIO_ACTIVE_LOW>; + }; + + d9 { + label = "d9"; + gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; + }; + + d10 { + label = "d10"; + gpios = <&pioE 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D4EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN1L", "Line In Jack", + "IN1R", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; }; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 21c2b504f977d16088ce290386ba73ddb4333b6b..4fb333bd1f85f10dcce81e953cf232f1ab14c74f 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -356,9 +356,13 @@ macb0_clk: macb0_clk { }; st: timer@fffffd00 { - compatible = "atmel,at91rm9200-st"; + compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; reg = <0xfffffd00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + + watchdog { + compatible = "atmel,at91rm9200-wdt"; + }; }; rtc: rtc@fffffe00 { @@ -830,7 +834,7 @@ pioD: gpio@fffffa00 { }; dbgu: serial@fffff200 { - compatible = "atmel,at91rm9200-usart"; + compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; reg = <0xfffff200 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 62d25b14deb8a6916ddbeb6116b25ba71a7e31ba..d88fe62a2b2e12e41aaeb8058d028b7fa89cd788 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -753,7 +753,7 @@ pioC: gpio@fffff800 { }; dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-usart"; + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index d55fdf2487ef53f7a3c68cded4e78fe42039f538..bf8d1856a55a55a3668bd69879df1ef2c8d1dd26 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -276,7 +276,7 @@ aic: interrupt-controller@fffff000 { }; dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-usart"; + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index e4f61a979a5700a067c9795d370dc841450d713b..111889b556cf1e2f52ce002995c20a0e00db8914 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -762,7 +762,7 @@ pioE: gpio@fffffa00 { }; dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-usart"; + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi index 17b879990914c8643bfc63cb98b634c112f4f454..a7da0dd0c98fa0af8d05ad545660aba426962c30 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/at91sam9g25.dtsi @@ -7,6 +7,7 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_isi.dtsi" #include "at91sam9x5_usart3.dtsi" #include "at91sam9x5_macb0.dtsi" diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index 1e4c49c584d38a5115b817efc57f3934681e011e..707fd4ea58f5d425bce8df2f2097f31ca0c2ae20 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts @@ -16,10 +16,28 @@ / { ahb { apb { + spi0: spi@f0000000 { + status = "disabled"; + }; + + mmc1: mmc@f000c000 { + status = "disabled"; + }; + + i2c0: i2c@f8010000 { + ov2640: camera@0x30 { + status = "okay"; + }; + }; + macb0: ethernet@f802c000 { phy-mode = "rmii"; status = "okay"; }; + + isi: isi@f8048000 { + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 8ec05b11298a536b07c2c48586d6badcdcfaf9cd..70e59c5ceb2f7a56c5bd7e35d0cc9b34cf6a06a4 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -893,7 +893,7 @@ pioE: gpio@fffffa00 { }; dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-usart"; + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 0c53a375ba99d214c1c0b5eabd85e77ec0cc72e6..a9e35dfc12d9d5a763e4484f8a331806da13ad63 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -757,7 +757,7 @@ pioD: gpio@fffffa00 { }; dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-usart"; + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; @@ -912,6 +912,15 @@ pwm0: pwm@f8034000 { clocks = <&pwm_clk>; status = "disabled"; }; + + usb1: gadget@f803c000 { + compatible = "atmel,at91sam9260-udc"; + reg = <0xf803c000 0x4000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&udpck>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 9575c0d895c919e0da00288192981ea299713f3e..6e067c8a350252de0d2cd66fd580d94aba0bda59 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -108,6 +108,13 @@ pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { ; }; }; + + usb1 { + pinctrl_usb1_vbus_sense: usb1_vbus_sense { + atmel,pins = + ; /* PB16 gpio usb vbus sense, no pull up and deglitch */ + }; + }; }; spi0: spi@f0000000 { @@ -120,9 +127,20 @@ m25p80@0 { }; }; + usb1: gadget@f803c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus_sense>; + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + watchdog@fffffe40 { status = "okay"; }; + + rtc@fffffeb0 { + status = "okay"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 40f645b8fe25699d51904e5bdcaba8251375686a..ebfd5ce9cb3867d52c821ca075906b57be86abe8 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -377,7 +377,7 @@ aic: interrupt-controller@fffff000 { }; dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-usart"; + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index d221179d0f1aad8aaccde552f74962a3009c6274..3aa56ae3410a5f96692df4d0f9f04238e2c06469 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -860,7 +860,7 @@ mmc1: mmc@f000c000 { }; dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-usart"; + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi index 98bc877a68ef0d697f46f3e43fe83fef6c1d7d0a..8fc45ca4dcb58a0d8d2e7a086e7437df330b6259 100644 --- a/arch/arm/boot/dts/at91sam9x5_isi.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi @@ -13,6 +13,37 @@ / { ahb { apb { + pinctrl@fffff400 { + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* ISI_VSYNC, conflicts with LCDDAT13 */ + }; + + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* ISI_D9, conflicts with LCDDAT9 */ + }; + + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* ISI_D11, conflicts with LCDDAT11 */ + }; + }; + }; + pmc: pmc@fffffc00 { periphck { isi_clk: isi_clk { @@ -21,6 +52,21 @@ isi_clk: isi_clk { }; }; }; + + isi: isi@f8048000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf8048000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 229d6c24a9c408c37d5dcb46b279d457768b173d..26112ebd15fc4e896d576932b330b846fc4cc397 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi @@ -42,6 +42,10 @@ pinctrl_1wire_cm: 1wire_cm-0 { }; }; }; + + rtc@fffffeb0 { + status = "okay"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index bd16bd360272ae212cc0a86c10dde6b697c3c31b..cc83a37a7311ba55e2e717ad789d040f65fe98f1 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -59,6 +59,16 @@ usb2: gadget@f803c000 { status = "okay"; }; + isi: isi@f8048000 { + status = "disabled"; + port { + isi_0: endpoint@0 { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + }; + }; + }; + i2c0: i2c@f8010000 { status = "okay"; @@ -66,9 +76,47 @@ wm8731: wm8731@1a { compatible = "wm8731"; reg = <0x1a>; }; + + ov2640: camera@0x30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; + clocks = <&pck0>; + clock-names = "xvclk"; + assigned-clocks = <&pck0>; + assigned-clock-rates = <25000000>; + status = "disabled"; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; }; pinctrl@fffff400 { + camera_sensor { + pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 { + atmel,pins = + ; /* ISI_MCK */ + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + ; + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + ; + }; + }; + mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index ff5fb6ab0b9748dbecd27fd7432c4f8306f5221d..7b52c33ea69aedefa667a9a96460a6d5cb4fefc4 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -54,6 +54,42 @@ cpu@0 { /include/ "bcm-cygnus-clock.dtsi" + pinctrl: pinctrl@0x0301d0c8 { + compatible = "brcm,cygnus-pinmux"; + reg = <0x0301d0c8 0x30>, + <0x0301d24c 0x2c>; + }; + + gpio_crmu: gpio@03024800 { + compatible = "brcm,cygnus-crmu-gpio"; + reg = <0x03024800 0x50>, + <0x03024008 0x18>; + #gpio-cells = <2>; + gpio-controller; + }; + + gpio_ccm: gpio@1800a000 { + compatible = "brcm,cygnus-ccm-gpio"; + reg = <0x1800a000 0x50>, + <0x0301d164 0x20>; + #gpio-cells = <2>; + gpio-controller; + interrupts = ; + interrupt-controller; + }; + + gpio_asiu: gpio@180a5000 { + compatible = "brcm,cygnus-asiu-gpio"; + reg = <0x180a5000 0x668>; + #gpio-cells = <2>; + gpio-controller; + + pinmux = <&pinctrl>; + + interrupt-controller; + interrupts = ; + }; + amba { #address-cells = <1>; #size-cells = <1>; @@ -90,6 +126,48 @@ i2c1: i2c@1800b000 { status = "disabled"; }; + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000 + 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + + status = "disabled"; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000 + 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + + status = "disabled"; + }; + uart0: serial@18020000 { compatible = "snps,dw-apb-uart"; reg = <0x18020000 0x100>; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index f18c9d9b2f2c78c616e859574626fa62489e7aa1..2ed9e5794785fb9a8f3e08228fb999e245c4d8de 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -45,13 +45,13 @@ logo { power0 { label = "bcm53xx:green:power"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; + linux,default-trigger = "default-on"; }; power1 { label = "bcm53xx:amber:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; + linux,default-trigger = "default-off"; }; usb { diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts new file mode 100644 index 0000000000000000000000000000000000000000..ea26dd3ec03a099a7a62d7b1659550da2df88e3a --- /dev/null +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -0,0 +1,77 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Netgear R8000 + * + * Copyright (C) 2015 Rafał Miłecki + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708"; + model = "Netgear R8000 (BCM4709)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + power0 { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 5ghz-1 { + label = "bcm53xx:white:5ghz-1"; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index 0ca0f4e523d0adf4d6d2eac08482544f60dcbd67..39ac7840d7eebfafd5be58dc2b3fa5c5b9d6c63b 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -76,7 +76,7 @@ serial@40ab00 { reg-shift = <2>; reg-io-width = <4>; interrupts = ; - clock-frequency = <0x4d3f640>; + clock-frequency = <81000000>; }; sun_top_ctrl: syscon@404000 { @@ -96,6 +96,18 @@ hif_continuation: syscon@452000 { "syscon"; reg = <0x452000 0x100>; }; + + irq0_intc: interrupt-controller@40a780 { + compatible = "brcm,bcm7120-l2-intc"; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + reg = <0x40a780 0x8>; + interrupt-controller; + interrupts = , + ; + brcm,int-map-mask = <0x25c>, <0x7000000>; + brcm,int-fwd-mask = <0x70000>; + }; }; smpboot { diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts index d2ee952805488df5c410fad41ccbf2d66d4d45e7..7db484323fd62dc7ed9a988e6a3008597f59467f 100644 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -33,6 +33,7 @@ /dts-v1/; #include "bcm-cygnus.dtsi" +#include "dt-bindings/input/input.h" / { model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; @@ -50,4 +51,16 @@ chosen { uart3: serial@18023000 { status = "okay"; }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + hook { + label = "HOOK"; + linux,code = ; + gpios = <&gpio_asiu 48 0>; + }; + }; }; diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts index f1bb36f3975ca3c356639d3c58424a613eab5257..c9eb8565eac5be2b3d0299218919b4a8a918bd94 100644 --- a/arch/arm/boot/dts/bcm958300k.dts +++ b/arch/arm/boot/dts/bcm958300k.dts @@ -47,6 +47,14 @@ chosen { bootargs = "console=ttyS0,115200"; }; + pcie0: pcie@18012000 { + status = "okay"; + }; + + pcie1: pcie@18013000 { + status = "okay"; + }; + uart3: serial@18023000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts new file mode 100644 index 0000000000000000000000000000000000000000..56b429abbedb9c1139d85dec79c5b1baf49ffd73 --- /dev/null +++ b/arch/arm/boot/dts/bcm958305k.dts @@ -0,0 +1,53 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" + +/ { + model = "Cygnus Wireless Audio (BCM958305K)"; + compatible = "brcm,bcm58305", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS0,115200"; + }; + + uart3: serial@18023000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index afe678f6d2e950308b74e403d26a3cc326c2b760..169a85578fc93e31927c10ce381b9407a484fe38 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -29,10 +29,10 @@ vmmcsd_fixed: fixedregulator@0 { &dm816x_pinmux { mcspi1_pins: pinmux_mcspi1_pins { pinctrl-single,pins = < - DM816X_IOPAD(0x0a94, PIN_INPUT | MUX_MODE0) /* SPI_SCLK */ - DM816X_IOPAD(0x0a98, PIN_OUTPUT | MUX_MODE0) /* SPI_SCS0 */ - DM816X_IOPAD(0x0aa8, PIN_INPUT | MUX_MODE0) /* SPI_D0 */ - DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */ + DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ + DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ + DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */ + DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ >; }; @@ -52,13 +52,13 @@ DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ usb0_pins: pinmux_usb0_pins { pinctrl-single,pins = < - DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */ + DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ >; }; - usb1_pins: pinmux_usb0_pins { + usb1_pins: pinmux_usb1_pins { pinctrl-single,pins = < - DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB1_DRVVBUS */ + DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ >; }; }; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index f35715bc69922591577299730ecf1a105c6642de..289806adb343806aefce22e63b6caa1d558741fb 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -382,7 +382,7 @@ usb: usb_otg_hs@47401000 { ti,hwmods = "usb_otg_hs"; usb0: usb@47401000 { - compatible = "ti,musb-am33xx"; + compatible = "ti,musb-dm816"; reg = <0x47401400 0x400 0x47401000 0x200>; reg-names = "mc", "control"; @@ -396,10 +396,33 @@ usb0: usb@47401000 { mentor,num-eps = <16>; mentor,ram-bits = <12>; mentor,power = <500>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 4 0 &cppi41dma 5 0 + &cppi41dma 6 0 &cppi41dma 7 0 + &cppi41dma 8 0 &cppi41dma 9 0 + &cppi41dma 10 0 &cppi41dma 11 0 + &cppi41dma 12 0 &cppi41dma 13 0 + &cppi41dma 14 0 &cppi41dma 0 1 + &cppi41dma 1 1 &cppi41dma 2 1 + &cppi41dma 3 1 &cppi41dma 4 1 + &cppi41dma 5 1 &cppi41dma 6 1 + &cppi41dma 7 1 &cppi41dma 8 1 + &cppi41dma 9 1 &cppi41dma 10 1 + &cppi41dma 11 1 &cppi41dma 12 1 + &cppi41dma 13 1 &cppi41dma 14 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; }; usb1: usb@47401800 { - compatible = "ti,musb-am33xx"; + compatible = "ti,musb-dm816"; reg = <0x47401c00 0x400 0x47401800 0x200>; reg-names = "mc", "control"; @@ -413,6 +436,43 @@ usb1: usb@47401800 { mentor,num-eps = <16>; mentor,ram-bits = <12>; mentor,power = <500>; + + dmas = <&cppi41dma 15 0 &cppi41dma 16 0 + &cppi41dma 17 0 &cppi41dma 18 0 + &cppi41dma 19 0 &cppi41dma 20 0 + &cppi41dma 21 0 &cppi41dma 22 0 + &cppi41dma 23 0 &cppi41dma 24 0 + &cppi41dma 25 0 &cppi41dma 26 0 + &cppi41dma 27 0 &cppi41dma 28 0 + &cppi41dma 29 0 &cppi41dma 15 1 + &cppi41dma 16 1 &cppi41dma 17 1 + &cppi41dma 18 1 &cppi41dma 19 1 + &cppi41dma 20 1 &cppi41dma 21 1 + &cppi41dma 22 1 &cppi41dma 23 1 + &cppi41dma 24 1 &cppi41dma 25 1 + &cppi41dma 26 1 &cppi41dma 27 1 + &cppi41dma 28 1 &cppi41dma 29 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + cppi41dma: dma-controller@47402000 { + compatible = "ti,am3359-cppi41"; + reg = <0x47400000 0x1000 + 0x47402000 0x1000 + 0x47403000 0x1000 + 0x47404000 0x4000>; + reg-names = "glue", "controller", "scheduler", "queuemgr"; + interrupts = <17>; + interrupt-names = "glue"; + #dma-cells = <2>; + #dma-channels = <30>; + #dma-requests = <256>; }; }; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index aae7efc09b0bd1ecd66e72193c6aefe107008b9e..e6fa251e17b93b54f67bcd39b8da57476ddda519 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -87,6 +87,7 @@ si5351: clock-generator { /* connect xtal input to 25MHz reference */ clocks = <&ref25>; + clock-names = "xtal"; /* connect xtal input as source of pll0 and pll1 */ silabs,pll-source = <0 0>, <1 0>; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index a5441d5482a63a0a9203f3333b96c87ec1912b11..9ad829523a1350d59bcc795286459d8dfc6c133e 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -1,5 +1,8 @@ /include/ "skeleton.dtsi" +#include +#include + #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { @@ -61,7 +64,7 @@ pcie: pcie-controller { 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ - pcie-port@0 { + pcie0: pcie-port@0 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; @@ -79,7 +82,7 @@ pcie-port@0 { interrupt-map = <0 0 0 0 &intc 16>; }; - pcie-port@1 { + pcie1: pcie-port@1 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; @@ -154,7 +157,7 @@ uart1: serial@12100 { uart2: serial@12200 { compatible = "ns16550a"; - reg = <0x12000 0x100>; + reg = <0x12200 0x100>; reg-shift = <2>; interrupts = <9>; clocks = <&core_clk 0>; @@ -163,7 +166,7 @@ uart2: serial@12200 { uart3: serial@12300 { compatible = "ns16550a"; - reg = <0x12100 0x100>; + reg = <0x12300 0x100>; reg-shift = <2>; interrupts = <10>; clocks = <&core_clk 0>; @@ -448,6 +451,11 @@ pmx_gpio_9: pmx-gpio-9 { marvell,function = "gpio"; }; + pmx_pcie1_clkreq: pmx-pcie1-clkreq { + marvell,pins = "mpp9"; + marvell,function = "pex1"; + }; + pmx_gpio_10: pmx-gpio-10 { marvell,pins = "mpp10"; marvell,function = "gpio"; @@ -458,6 +466,11 @@ pmx_gpio_11: pmx-gpio-11 { marvell,function = "gpio"; }; + pmx_pcie0_clkreq: pmx-pcie0-clkreq { + marvell,pins = "mpp11"; + marvell,function = "pex0"; + }; + pmx_gpio_12: pmx-gpio-12 { marvell,pins = "mpp12"; marvell,function = "gpio"; @@ -563,6 +576,18 @@ pmx_spi0_gpio: pmx-spi0-gpio { marvell,function = "gpio"; }; + pmx_spi1_4_7: pmx-spi1-4-7 { + marvell,pins = "mpp4", "mpp5", + "mpp6", "mpp7"; + marvell,function = "spi1"; + }; + + pmx_spi1_20_23: pmx-spi1-20-23 { + marvell,pins = "mpp20", "mpp21", + "mpp22", "mpp23"; + marvell,function = "spi1"; + }; + pmx_uart1: pmx-uart1 { marvell,pins = "mpp_uart1"; marvell,function = "uart1"; @@ -582,6 +607,36 @@ pmx_nand_gpo: pmx-nand-gpo { marvell,pins = "mpp_nand"; marvell,function = "gpo"; }; + + pmx_i2c1: pmx-i2c1 { + marvell,pins = "mpp17", "mpp19"; + marvell,function = "twsi"; + }; + + pmx_i2c2: pmx-i2c2 { + marvell,pins = "mpp_audio1"; + marvell,function = "twsi"; + }; + + pmx_ssp_i2c2: pmx-ssp-i2c2 { + marvell,pins = "mpp_audio1"; + marvell,function = "ssp/twsi"; + }; + + pmx_i2cmux_0: pmx-i2cmux-0 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt1"; + }; + + pmx_i2cmux_1: pmx-i2cmux-1 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt2"; + }; + + pmx_i2cmux_2: pmx-i2cmux-2 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt3"; + }; }; core_clk: core-clocks@d0214 { diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index b1bd06c6c2a801ee9c647cb63483430b8be60c44..aa465904f6cc420ecad93f006bc5e622d8e70b36 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -541,6 +541,14 @@ partition@9 { }; }; +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + &usb1 { dr_mode = "peripheral"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index a0afce7ad482cab69ce4c3935ef59536dd41c9d2..f03a091cd0766b606d0f3a61a4ab03c870f3dfcf 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -102,17 +102,101 @@ ocp { interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - prm: prm@4ae06000 { - compatible = "ti,dra7-prm"; - reg = <0x4ae06000 0x3000>; - interrupts = ; + l4_cfg: l4@4a000000 { + compatible = "ti,dra7-l4-cfg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a000000 0x22c000>; - prm_clocks: clocks { + scm: scm@2000 { + compatible = "ti,dra7-scm-core", "simple-bus"; + reg = <0x2000 0x2000>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x1400>; + #address-cells = <1>; + #size-cells = <1>; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0xe00 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + + dra7_pmx_core: pinmux@1400 { + compatible = "ti,dra7-padconf", + "pinctrl-single"; + reg = <0x1400 0x0464>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x3fffffff>; + }; + }; + + cm_core_aon: cm_core_aon@5000 { + compatible = "ti,dra7-cm-core-aon"; + reg = <0x5000 0x2000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; + + cm_core: cm_core@8000 { + compatible = "ti,dra7-cm-core"; + reg = <0x8000 0x3000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; }; + }; - prm_clockdomains: clockdomains { + l4_wkup: l4@4ae00000 { + compatible = "ti,dra7-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4ae00000 0x3f000>; + + counter32k: counter@4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x40>; + ti,hwmods = "counter_32k"; + }; + + prm: prm@6000 { + compatible = "ti,dra7-prm"; + reg = <0x6000 0x3000>; + interrupts = ; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; }; }; @@ -185,36 +269,16 @@ pcie2_intc: interrupt-controller { }; }; - cm_core_aon: cm_core_aon@4a005000 { - compatible = "ti,dra7-cm-core-aon"; - reg = <0x4a005000 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - - cm_core: cm_core@4a008000 { - compatible = "ti,dra7-cm-core"; - reg = <0x4a008000 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - - counter32k: counter@4ae04000 { - compatible = "ti,omap-counter32k"; - reg = <0x4ae04000 0x40>; - ti,hwmods = "counter_32k"; + bandgap: bandgap@4a0021e0 { + reg = <0x4a0021e0 0xc + 0x4a00232c 0xc + 0x4a002380 0x2c + 0x4a0023C0 0x3c + 0x4a002564 0x8 + 0x4a002574 0x50>; + compatible = "ti,dra752-bandgap"; + interrupts = ; + #thermal-sensor-cells = <1>; }; dra7_ctrl_core: ctrl_core@4a002000 { @@ -227,28 +291,6 @@ dra7_ctrl_general: tisyscon@4a002e00 { reg = <0x4a002e00 0x7c>; }; - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0 0x4>; - syscon = <&dra7_ctrl_general>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - - dra7_pmx_core: pinmux@4a003400 { - compatible = "ti,dra7-padconf", "pinctrl-single"; - reg = <0x4a003400 0x0464>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x3fffffff>; - }; - sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -666,7 +708,6 @@ timer5: timer@48820000 { reg = <0x48820000 0x80>; interrupts = ; ti,hwmods = "timer5"; - ti,timer-dsp; }; timer6: timer@48822000 { @@ -674,8 +715,6 @@ timer6: timer@48822000 { reg = <0x48822000 0x80>; interrupts = ; ti,hwmods = "timer6"; - ti,timer-dsp; - ti,timer-pwm; }; timer7: timer@48824000 { @@ -683,7 +722,6 @@ timer7: timer@48824000 { reg = <0x48824000 0x80>; interrupts = ; ti,hwmods = "timer7"; - ti,timer-dsp; }; timer8: timer@48826000 { @@ -691,8 +729,6 @@ timer8: timer@48826000 { reg = <0x48826000 0x80>; interrupts = ; ti,hwmods = "timer8"; - ti,timer-dsp; - ti,timer-pwm; }; timer9: timer@4803e000 { @@ -714,7 +750,6 @@ timer11: timer@48088000 { reg = <0x48088000 0x80>; interrupts = ; ti,hwmods = "timer11"; - ti,timer-pwm; }; timer13: timer@48828000 { @@ -876,7 +911,7 @@ abb_mpu: regulator-abb-mpu { ti,clock-cycles = <16>; reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, - <0x4ae06014 0x4>, <0x4a003b20 0x8>, + <0x4ae06014 0x4>, <0x4a003b20 0xc>, <0x4ae0c158 0x4>; reg-names = "setup-address", "control-address", "int-address", "efuse-address", @@ -909,7 +944,7 @@ abb_ivahd: regulator-abb-ivahd { ti,clock-cycles = <16>; reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, - <0x4ae06010 0x4>, <0x4a0025cc 0x8>, + <0x4ae06010 0x4>, <0x4a0025cc 0xc>, <0x4a002470 0x4>; reg-names = "setup-address", "control-address", "int-address", "efuse-address", @@ -942,7 +977,7 @@ abb_dspeve: regulator-abb-dspeve { ti,clock-cycles = <16>; reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, - <0x4ae06010 0x4>, <0x4a0025e0 0x8>, + <0x4ae06010 0x4>, <0x4a0025e0 0xc>, <0x4a00246c 0x4>; reg-names = "setup-address", "control-address", "int-address", "efuse-address", @@ -975,7 +1010,7 @@ abb_gpu: regulator-abb-gpu { ti,clock-cycles = <16>; reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, - <0x4ae06010 0x4>, <0x4a003b08 0x8>, + <0x4ae06010 0x4>, <0x4a003b08 0xc>, <0x4ae0c154 0x4>; reg-names = "setup-address", "control-address", "int-address", "efuse-address", @@ -1168,7 +1203,7 @@ omap_control_pcie2phy: control-pcie@0x4a003c44 { status = "disabled"; }; - rtc@48838000 { + rtc: rtc@48838000 { compatible = "ti,am3352-rtc"; reg = <0x48838000 0x100>; interrupts = , @@ -1419,7 +1454,7 @@ dcan1: can@481cc000 { compatible = "ti,dra7-d_can"; ti,hwmods = "dcan1"; reg = <0x4ae3c000 0x2000>; - syscon-raminit = <&dra7_ctrl_core 0x558 0>; + syscon-raminit = <&scm_conf 0x558 0>; interrupts = ; clocks = <&dcan1_sys_clk_mux>; status = "disabled"; @@ -1429,12 +1464,23 @@ dcan2: can@481d0000 { compatible = "ti,dra7-d_can"; ti,hwmods = "dcan2"; reg = <0x48480000 0x2000>; - syscon-raminit = <&dra7_ctrl_core 0x558 1>; + syscon-raminit = <&scm_conf 0x558 1>; interrupts = ; clocks = <&sys_clkin1>; status = "disabled"; }; }; + + thermal_zones: thermal-zones { + #include "omap4-cpu-thermal.dtsi" + #include "omap5-gpu-thermal.dtsi" + #include "omap5-core-thermal.dtsi" + }; + +}; + +&cpu_thermal { + polling-delay = <500>; /* milliseconds */ }; /include/ "dra7xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index daf28110d4872224be02ef57de5c61de06a7f55a..ce0390f081d92ff6966657a5a45713fa7c32c309 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -377,6 +377,14 @@ &usb2_phy2 { phy-supply = <&ldo4_reg>; }; +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + &usb1 { dr_mode = "peripheral"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index f7fb0d0ef25a5400b5738ba8b8afad955cded5f5..03d742f8d572f10a42e426055f28e550ca8bd7a5 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -20,6 +20,11 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <2>; + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 00eeed789b4b74a306137f82d6fb70ebea831fe7..cc560a70926f003155474d9956652c6fe09718e7 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -31,6 +31,11 @@ cpu0: cpu@0 { clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <2>; + #cooling-cells = <2>; /* min followed by max */ }; cpu@1 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 99b09a44e2694129ece5426f8df2227719255a37..3b933f74d000cd039b3ecf441928c114dca0e124 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1493,6 +1493,14 @@ l3init_60m_fclk: l3init_60m_fclk { ti,dividers = <1>, <8>; }; + clkout2_clk: clkout2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkoutmux2_clk_mux>; + ti,bit-shift = <8>; + reg = <0x06b0>; + }; + l3init_960m_gfclk: l3init_960m_gfclk { #clock-cells = <0>; compatible = "ti,gate-clock"; diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 667d323e80a3e17616aec13cd0faab9f5a638a89..19446273e4a7f83242bf8ead39735462d2b649e7 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -94,3 +94,16 @@ lan9220@20000000 { vdd33a-supply = <®_3p3v>; }; }; + +&pfc { + uart1_pins: uart@e1030000 { + renesas,groups = "uart1_ctrl", "uart1_data"; + renesas,function = "uart1"; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index cc7bfe0ba40af9a90ac8756c74e45865e0c68b0a..bb45694d91bc1e6c4557085287235613b52f16d3 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -169,12 +169,18 @@ uart3: serial@e1050000 { clock-names = "sclk"; }; + pfc: pfc@e0140200 { + compatible = "renesas,pfc-emev2"; + reg = <0xe0140200 0x100>; + }; + gpio0: gpio@e0050000 { compatible = "renesas,em-gio"; reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>, <0 68 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&pfc 0 0 32>; #gpio-cells = <2>; ngpios = <32>; interrupt-controller; @@ -186,6 +192,7 @@ gpio1: gpio@e0050080 { interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>, <0 70 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&pfc 0 32 32>; #gpio-cells = <2>; ngpios = <32>; interrupt-controller; @@ -197,6 +204,7 @@ gpio2: gpio@e0050100 { interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, <0 72 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&pfc 0 64 32>; #gpio-cells = <2>; ngpios = <32>; interrupt-controller; @@ -208,6 +216,7 @@ gpio3: gpio@e0050180 { interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, <0 74 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&pfc 0 96 32>; #gpio-cells = <2>; ngpios = <32>; interrupt-controller; @@ -219,6 +228,7 @@ gpio4: gpio@e0050200 { interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>, <0 76 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&pfc 0 128 31>; #gpio-cells = <2>; ngpios = <31>; interrupt-controller; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 14ab515aa83cd1a1f02918563b769657fe8c472c..e3bfb11c6ef82c3194c22f449e5d1c31ac642631 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -176,6 +176,10 @@ cmu: clock-controller@10030000 { compatible = "samsung,exynos3250-cmu"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, + <&cmu CLK_MOUT_ACLK_266_SUB>; + assigned-clock-parents = <&cmu CLK_FIN_PLL>, + <&cmu CLK_FIN_PLL>; }; cmu_dmc: clock-controller@105C0000 { diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index adb4f6a97a1d5b19d67d486e7d36dd386884d1fd..d6b49e5b32e9f35ed2a1378e1f7933997c5d4e85 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -9,6 +9,7 @@ #include #include +#include #include "exynos4412.dtsi" / { @@ -75,10 +76,18 @@ link0_codec: simple-audio-card,codec { }; }; + emmc_pwrseq: pwrseq { + pinctrl-0 = <&sd1_cd>; + pinctrl-names = "default"; + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpk1 2 1>; + }; + mmc@12550000 { pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; vmmc-supply = <&ldo20_reg &buck8_reg>; + mmc-pwrseq = <&emmc_pwrseq>; status = "okay"; num-slots = <1>; @@ -97,6 +106,8 @@ watchdog@10060000 { rtc@10070000 { status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; }; g2d@10800000 { @@ -472,6 +483,12 @@ i2c@138E0000 { }; }; +/* RSTN signal for eMMC */ +&sd1_cd { + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; +}; + &pinctrl_1 { gpio_power_key: power_key { samsung,pins = "gpx1-3"; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 173ffa479ad3cb03eb6e6742663fafaccacf9d53..792394dd0f2ab3ebf347af1e3f08d7ad330ee997 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -736,7 +736,7 @@ panel@0 { display-timings { timing-0 { - clock-frequency = <0>; + clock-frequency = <57153600>; hactive = <720>; vactive = <1280>; hfront-porch = <5>; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index b9aeec430527e3afd5aeb2c2b1af8f3a1b102682..1eca97ee4bd6320a3a3a44ede264e269041cd088 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -29,6 +29,7 @@ memory { chosen { bootargs = "console=tty1"; + stdout-path = "serial3:115200n8"; }; gpio-keys { @@ -183,7 +184,20 @@ ptn3460: lvds-bridge@20 { powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; edid-emulation = <5>; - panel = <&panel>; + + ports { + port@0 { + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; }; }; @@ -228,6 +242,20 @@ panel: panel { compatible = "auo,b116xw03"; power-supply = <&fet6>; backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + mmc3_pwrseq: mmc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */ + <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "ext_clock"; }; }; @@ -242,7 +270,14 @@ &dp { samsung,link-rate = <0x0a>; samsung,lane-count = <2>; samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>; - bridge = <&ptn3460>; + + ports { + port@0 { + dp_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; }; &ehci { @@ -531,17 +566,34 @@ &mmc_3 { status = "okay"; num-slots = <1>; broken-cd; + cap-sdio-irq; + keep-power-in-suspend; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4 &wifi_en &wifi_rst>; bus-width = <4>; cap-sd-highspeed; + mmc-pwrseq = <&mmc3_pwrseq>; }; &pinctrl_0 { + wifi_en: wifi-en { + samsung,pins = "gpx0-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + wifi_rst: wifi-rst { + samsung,pins = "gpx0-2"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + power_key_irq: power-key-irq { samsung,pins = "gpx1-3"; samsung,pin-function = <0xf>; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index f02775487cd4d3d20925afb84da693f92ad13e1e..d03f9b8d376d082308fa9e06c515f69ae83386c2 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -25,6 +25,7 @@ memory { chosen { bootargs = "console=tty1"; + stdout-path = "serial3:115200n8"; }; gpio-keys { @@ -429,7 +430,6 @@ &mfc { &mmc_0 { status = "okay"; num-slots = <1>; - supports-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; @@ -437,11 +437,8 @@ &mmc_0 { samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; /* @@ -451,7 +448,6 @@ slot@0 { &mmc_1 { status = "okay"; num-slots = <1>; - supports-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; @@ -459,11 +455,8 @@ &mmc_1 { samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-sd-highspeed; }; &pinctrl_0 { @@ -490,7 +483,7 @@ trackpad_irq: trackpad-irq { power_key_irq: power-key-irq { samsung,pins = "gpx1-3"; - samsung,pin-function = <0>; + samsung,pin-function = <0xf>; samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; @@ -518,7 +511,7 @@ s5m8767_irq: s5m8767-irq { lid_irq: lid-irq { samsung,pins = "gpx3-5"; - samsung,pin-function = <0>; + samsung,pin-function = <0xf>; samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 77f656eb8e6b87fe19182b72e66c2ae9160f4e59..257e2f10525de14fb8eee4ca5b4ecd630da18cf7 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -143,7 +143,7 @@ mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; interrupt-controller; - #interrups-cells = <2>; + #interrupt-cells = <2>; interrupt-parent = <&mct_map>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index db2c1c4cd90076b5c7bb47d12737e46bf4938264..b82b6fa15f4861d21087dbe82b578a3c66ff3f4e 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -55,7 +55,7 @@ mmc@12200000 { samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; vmmc-supply = <&ldo10_reg>; bus-width = <8>; cap-mmc-highspeed; @@ -68,7 +68,7 @@ mmc@12220000 { samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; vmmc-supply = <&ldo19_reg>; vqmmc-supply = <&ldo13_reg>; bus-width = <4>; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index c47bb70665c1652c6b907e8d3d05cea077781079..146e71118a72b4eef98faf47f644c0216bbb5894 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -43,6 +43,10 @@ backlight: backlight { pinctrl-names = "default"; }; + chosen { + stdout-path = "serial3:115200n8"; + }; + fixed-rate-clocks { oscclk { compatible = "samsung,exynos5420-oscclk"; @@ -118,6 +122,19 @@ panel: panel { compatible = "auo,b116xw03"; power-supply = <&tps65090_fet6>; backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + mmc1_pwrseq: mmc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + clocks = <&max77802 MAX77802_CLK_32K_CP>; + clock-names = "ext_clock"; }; }; @@ -137,7 +154,14 @@ &dp { samsung,link-rate = <0x06>; samsung,lane-count = <2>; samsung,hpd-gpio = <&gpx2 6 0>; - bridge = <&ps8625>; + + ports { + port@0 { + dp_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; }; &fimd { @@ -581,6 +605,8 @@ max98090: codec@10 { interrupt-parent = <&gpx0>; pinctrl-names = "default"; pinctrl-0 = <&max98090_irq>; + clocks = <&pmu_system_controller 0>; + clock-names = "mclk"; }; light-sensor@44 { @@ -595,8 +621,22 @@ ps8625: lvds-bridge@48 { sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; lane-count = <2>; - panel = <&panel>; use-external-pwm; + + ports { + port@0 { + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; + }; }; @@ -659,11 +699,33 @@ &mmc_0 { samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; }; +&mmc_1 { + status = "okay"; + num-slots = <1>; + broken-cd; + cap-sdio-irq; + keep-power-in-suspend; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, + <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; + bus-width = <4>; + cap-sd-highspeed; + mmc-pwrseq = <&mmc1_pwrseq>; + vqmmc-supply = <&buck10_reg>; +}; + &mmc_2 { status = "okay"; num-slots = <1>; @@ -674,7 +736,7 @@ &mmc_2 { samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; }; @@ -683,6 +745,13 @@ &pinctrl_0 { pinctrl-names = "default"; pinctrl-0 = <&mask_tpm_reset>; + wifi_en: wifi-en { + samsung,pins = "gpx0-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + max98090_irq: max98090-irq { samsung,pins = "gpx0-2"; samsung,pin-function = <0>; @@ -770,6 +839,29 @@ pmic_dvs_1: pmic-dvs-1 { }; }; +&pinctrl_1 { + /* Adjust WiFi drive strengths lower for EMI */ + sd1_clk: sd1-clk { + samsung,pin-drv = <2>; + }; + + sd1_cmd: sd1-cmd { + samsung,pin-drv = <2>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pin-drv = <2>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pin-drv = <2>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pin-drv = <2>; + }; +}; + &pinctrl_2 { pmic_dvs_2: pmic-dvs-2 { samsung,pins = "gpj4-2"; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index ba686e40eac7965942555a1f5eca9a81bb57ef39..8b153166ebdb430e6c827ab1a80d5bd9da316e47 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -201,6 +201,13 @@ sd1_clk: sd1-clk { samsung,pin-drv = <3>; }; + sd0_rclk: sd0-rclk { + samsung,pins = "gpc0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + sd1_cmd: sd1-cmd { samsung,pins = "gpc1-1"; samsung,pin-function = <2>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 8be3d7b489ff3585dad03e38f8177a300cbef00f..9103f2381a6d7ccefd22a429758fd7e3a4755820 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -80,8 +80,11 @@ mmc@12200000 { samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 + &sd0_rclk>; bus-width = <8>; cap-mmc-highspeed; }; @@ -93,7 +96,7 @@ mmc@12220000 { samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; }; diff --git a/arch/arm/boot/dts/exynos5420-trip-points.dtsi b/arch/arm/boot/dts/exynos5420-trip-points.dtsi index 5d31fc14082360b41cc742ad3f549dc5d4f9013c..2180a0152c9bf9d78b8772af284d6445ad0b6ebd 100644 --- a/arch/arm/boot/dts/exynos5420-trip-points.dtsi +++ b/arch/arm/boot/dts/exynos5420-trip-points.dtsi @@ -28,7 +28,7 @@ cpu-alert-2 { type = "active"; }; cpu-crit-0 { - temperature = <1200000>; /* millicelsius */ + temperature = <120000>; /* millicelsius */ hysteresis = <0>; /* millicelsius */ type = "critical"; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b3d2d53820e3d57005b6fb89d0f9e7dae72c3fa4..45317538bbaeb48309d1b16c0e18beb8a7376639 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -221,7 +221,7 @@ mct: mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; interrupt-controller; - #interrups-cells = <1>; + #interrupt-cells = <1>; interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>; @@ -251,6 +251,8 @@ gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; #power-domain-cells = <0>; + clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; + clock-names = "asb0", "asb1"; }; isp_pd: power-domain@10044020 { @@ -283,9 +285,11 @@ disp_pd: power-domain@100440C0 { <&clock CLK_MOUT_SW_ACLK300>, <&clock CLK_MOUT_USER_ACLK300_DISP1>, <&clock CLK_MOUT_SW_ACLK400>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>; + <&clock CLK_MOUT_USER_ACLK400_DISP1>, + <&clock CLK_FIMD1>, <&clock CLK_MIXER>; clock-names = "oscclk", "pclk0", "clk0", - "pclk1", "clk1", "pclk2", "clk2"; + "pclk1", "clk1", "pclk2", "clk2", + "asb0", "asb1"; }; pinctrl_0: pinctrl@13400000 { @@ -532,6 +536,7 @@ dp: dp-controller@145B0000 { clock-names = "dp"; phys = <&dp_phy>; phy-names = "dp"; + power-domains = <&disp_pd>; }; mipi_phy: video-phy@10040714 { diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index a519c863248d85f79a24d4fa918c53827819ca90..edc25cf1d71754d230912f16393333e51574e1a1 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -264,6 +264,13 @@ buck10_reg: BUCK10 { }; }; + emmc_pwrseq: pwrseq { + pinctrl-0 = <&emmc_nrst_pin>; + pinctrl-names = "default"; + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpd1 0 1>; + }; + i2c_2: i2c@12C80000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; @@ -298,13 +305,14 @@ &mfc { &mmc_0 { status = "okay"; + mmc-pwrseq = <&emmc_pwrseq>; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; bus-width = <8>; cap-mmc-highspeed; }; @@ -316,7 +324,7 @@ &mmc_2 { samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; }; @@ -330,6 +338,15 @@ hdmi_hpd_irq: hdmi-hpd-irq { }; }; +&pinctrl_1 { + emmc_nrst_pin: emmc-nrst { + samsung,pins = "gpd1-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/exynos5440-trip-points.dtsi b/arch/arm/boot/dts/exynos5440-trip-points.dtsi index 48adfa8f4300b5c17d6bd43377568952c01b9593..356e963edf11e58f95c57f70be0661a6277cddd8 100644 --- a/arch/arm/boot/dts/exynos5440-trip-points.dtsi +++ b/arch/arm/boot/dts/exynos5440-trip-points.dtsi @@ -18,7 +18,7 @@ cpu-alert-0 { type = "active"; }; cpu-crit-0 { - temperature = <1050000>; /* millicelsius */ + temperature = <105000>; /* millicelsius */ hysteresis = <0>; /* millicelsius */ type = "critical"; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 06737c60d33366b78eb74f16df8e0c113091a2bd..02eb8b15374f3c84ef4b215f4d7da85d2e9f342a 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -42,6 +42,10 @@ backlight: backlight { pinctrl-names = "default"; }; + chosen { + stdout-path = "serial3:115200n8"; + }; + fixed-rate-clocks { oscclk { compatible = "samsung,exynos5420-oscclk"; @@ -119,6 +123,13 @@ panel: panel { power-supply = <&tps65090_fet6>; backlight = <&backlight>; }; + + mmc1_pwrseq: mmc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + clocks = <&max77802 MAX77802_CLK_32K_CP>; + clock-names = "ext_clock"; + }; }; &adc { @@ -581,6 +592,8 @@ max98091: codec@10 { interrupt-parent = <&gpx0>; pinctrl-names = "default"; pinctrl-0 = <&max98091_irq>; + clocks = <&pmu_system_controller 0>; + clock-names = "mclk"; }; light-sensor@44 { @@ -641,18 +654,41 @@ &mmc_0 { num-slots = <1>; broken-cd; mmc-hs200-1_8v; + mmc-hs400-1_8v; cap-mmc-highspeed; non-removable; card-detect-delay = <200>; - clock-frequency = <400000000>; + clock-frequency = <800000000>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; }; +&mmc_1 { + status = "okay"; + num-slots = <1>; + broken-cd; + cap-sdio-irq; + keep-power-in-suspend; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, + <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; + bus-width = <4>; + cap-sd-highspeed; + mmc-pwrseq = <&mmc1_pwrseq>; + vqmmc-supply = <&buck10_reg>; +}; + &mmc_2 { status = "okay"; num-slots = <1>; @@ -663,7 +699,7 @@ &mmc_2 { samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; }; @@ -672,6 +708,13 @@ &pinctrl_0 { pinctrl-names = "default"; pinctrl-0 = <&mask_tpm_reset>; + wifi_en: wifi-en { + samsung,pins = "gpx0-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + max98091_irq: max98091-irq { samsung,pins = "gpx0-2"; samsung,pin-function = <0>; @@ -759,6 +802,29 @@ pmic_dvs_1: pmic-dvs-1 { }; }; +&pinctrl_1 { + /* Adjust WiFi drive strengths lower for EMI */ + sd1_clk: sd1-clk { + samsung,pin-drv = <2>; + }; + + sd1_cmd: sd1-cmd { + samsung,pin-drv = <2>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pin-drv = <2>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pin-drv = <2>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pin-drv = <2>; + }; +}; + &pinctrl_2 { pmic_dvs_2: pmic-dvs-2 { samsung,pins = "gpj4-2"; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 238814596a8787b5135df02f592306a823a1319e..44044f2751151c6a244036de3d665da9da4bd32f 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -275,7 +275,6 @@ etb@0,e3c42000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0 0xe3c42000 0 0x1000>; - coresight-default-sink; clocks = <&clk_375m>; clock-names = "apb_pclk"; port { diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 7e6eef2488e807c12c36aaebfd3e64b076f7622f..82045398bf1fabdf47664290d636d78a38b23b14 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -12,6 +12,7 @@ */ /dts-v1/; +#include #include "imx23.dtsi" / { @@ -93,6 +94,7 @@ usbphy0: usbphy@8007c000 { ahb@80080000 { usb0: usb@80080000 { + dr_mode = "host"; vbus-supply = <®_usb0_vbus>; status = "okay"; }; @@ -122,7 +124,7 @@ leds { user { label = "green"; - gpios = <&gpio2 1 1>; + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 9c21b15837627fcf2a98032183d77e2a8be153db..dd45e6971bc35061a3b9d5b4579c6e6697ca9eca 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -75,6 +75,27 @@ sound { mux-int-port = <1>; mux-ext-port = <4>; }; + + wvga: display { + model = "CLAA057VC01CW"; + bits-per-pixel = <16>; + fsl,pcr = <0xfa208b80>; + bus-width = <18>; + native-mode = <&wvga_timings>; + display-timings { + wvga_timings: 640x480 { + hactive = <640>; + vactive = <480>; + hback-porch = <45>; + hfront-porch = <114>; + hsync-len = <1>; + vback-porch = <33>; + vfront-porch = <11>; + vsync-len = <1>; + clock-frequency = <25200000>; + }; + }; + }; }; &audmux { @@ -190,6 +211,33 @@ MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 >; }; + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX25_PAD_LD0__LD0 0xe0 + MX25_PAD_LD1__LD1 0xe0 + MX25_PAD_LD2__LD2 0xe0 + MX25_PAD_LD3__LD3 0xe0 + MX25_PAD_LD4__LD4 0xe0 + MX25_PAD_LD5__LD5 0xe0 + MX25_PAD_LD6__LD6 0xe0 + MX25_PAD_LD7__LD7 0xe0 + MX25_PAD_LD8__LD8 0xe0 + MX25_PAD_LD9__LD9 0xe0 + MX25_PAD_LD10__LD10 0xe0 + MX25_PAD_LD11__LD11 0xe0 + MX25_PAD_LD12__LD12 0xe0 + MX25_PAD_LD13__LD13 0xe0 + MX25_PAD_LD14__LD14 0xe0 + MX25_PAD_LD15__LD15 0xe0 + MX25_PAD_GPIO_E__LD16 0xe0 + MX25_PAD_GPIO_F__LD17 0xe0 + MX25_PAD_HSYNC__HSYNC 0xe0 + MX25_PAD_VSYNC__VSYNC 0xe0 + MX25_PAD_LSCLK__LSCLK 0xe0 + MX25_PAD_OE_ACD__OE_ACD 0xe0 + MX25_PAD_CONTRAST__CONTRAST 0xe0 + >; + }; pinctrl_uart1: uart1grp { fsl,pins = < @@ -202,6 +250,16 @@ MX25_PAD_UART1_RXD__UART1_RXD 0xc0 }; }; +&lcdc { + display = <&wvga>; + fsl,lpccr = <0x00a903ff>; + fsl,lscr1 = <0x00120300>; + fsl,dmacr = <0x00020010>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; +}; + &nfc { nand-on-flash-bbt; status = "okay"; diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index 88eebb15da6a9ed45586e2ddfba37e9e28d85336..7c4b9f2f9aad8a31214ba2627be1fcb180884220 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -17,48 +17,69 @@ * */ +#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000 + #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 +#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000 +#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x16 0x000 +#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x17 0x000 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000 #define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000 +#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x16 0x000 +#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x17 0x000 #define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000 #define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000 +#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x16 0x000 +#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x17 0x000 #define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000 #define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000 +#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x16 0x000 +#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x17 0x000 #define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000 #define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000 +#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x16 0x000 #define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000 #define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000 -#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000 #define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000 +#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x16 0x000 +#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x17 0x000 #define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000 #define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000 +#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x16 0x000 #define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000 #define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000 #define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000 +#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x16 0x000 #define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000 #define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000 #define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000 +#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000 +#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x16 0x000 +#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000 #define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000 #define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000 +#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x16 0x000 +#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x17 0x000 #define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000 #define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000 +#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x16 0x000 #define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000 #define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000 @@ -133,20 +154,25 @@ #define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 #define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 #define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 +#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000 #define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 #define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 #define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 +#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000 #define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 #define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 #define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 +#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000 #define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 #define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 +#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000 #define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 #define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 +#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000 #define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000 #define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000 @@ -212,26 +238,33 @@ #define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000 #define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000 +#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000 #define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000 #define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001 +#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 #define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000 -#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001 +#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x15 0x001 #define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000 #define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001 +#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 #define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000 +#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 #define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001 #define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000 +#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000 #define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000 #define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000 +#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000 #define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000 #define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000 +#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000 #define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001 #define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000 @@ -244,6 +277,7 @@ #define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000 #define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000 +#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000 #define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 #define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 @@ -257,26 +291,31 @@ #define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000 #define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001 +#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 #define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000 #define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 #define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 #define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000 +#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000 #define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 #define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 #define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000 #define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001 +#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000 #define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000 #define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 #define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 -#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001 +#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x000 +#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000 #define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 #define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 #define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 +#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 #define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 @@ -284,32 +323,32 @@ #define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 #define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 -#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001 +#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x000 #define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 #define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000 #define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 -#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001 +#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x000 #define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 #define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000 #define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 -#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001 +#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x000 #define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001 #define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 -#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001 +#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x000 #define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001 #define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 -#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001 +#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x000 #define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001 #define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 -#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001 +#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x000 #define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 @@ -369,8 +408,8 @@ #define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000 #define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 -#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002 #define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000 +#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002 #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 #define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 @@ -392,11 +431,11 @@ #define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000 #define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000 -#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002 +#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x12 0x002 #define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000 #define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000 -#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002 +#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x12 0x002 #define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000 #define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000 @@ -410,7 +449,7 @@ #define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000 #define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000 -#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002 +#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x13 0x002 #define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000 #define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000 @@ -455,9 +494,18 @@ #define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000 #define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000 +/* + * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, + * 01/2011) this is CAN1_TX but that's wrong. + */ +#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x14 0x000 #define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000 #define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000 +/* + * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, + * 01/2011) this is CAN1_RX but that's wrong. + */ #define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000 #define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000 @@ -471,30 +519,34 @@ #define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000 #define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000 -#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000 - #define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000 #define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000 #define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000 #define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000 -#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001 #define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001 +#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001 #define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000 +#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x11 0x000 +#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x12 0x001 +#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x13 0x001 #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 #define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 +#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x12 0x001 #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 #define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 #define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002 #define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000 #define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 +#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x16 0x002 #define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 #define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000 #define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 +#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x16 0x000 #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 #define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000 @@ -505,6 +557,7 @@ #define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000 #define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000 #define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000 + #define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000 #define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000 @@ -517,6 +570,7 @@ #define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 #define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 + #define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 #define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index e4d3aecc4ed2c0fd61b1c68a93f20a24b808bd8c..677f81d9dcd529f92b6cf856464ec6595ef00509 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -428,6 +428,7 @@ slcdc@53fc0000 { pwm4: pwm@53fc8000 { compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; + #pwm-cells = <2>; reg = <0x53fc8000 0x4000>; clocks = <&clks 108>, <&clks 52>; clock-names = "ipg", "per"; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 4b063b68db44cbd1f99c3b63bcdb5463a0236baa..bc215e4b75fd52c6e5b2e271b4a9e6265d442205 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -488,6 +488,7 @@ usbh1: usb@10024200 { interrupts = <54>; clocks = <&clks IMX27_CLK_USB_IPG_GATE>; fsl,usbmisc = <&usbmisc 1>; + dr_mode = "host"; status = "disabled"; }; @@ -497,6 +498,7 @@ usbh2: usb@10024400 { interrupts = <55>; clocks = <&clks IMX27_CLK_USB_IPG_GATE>; fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; status = "disabled"; }; @@ -531,7 +533,7 @@ iim: iim@10028000 { fec: ethernet@1002b000 { compatible = "fsl,imx27-fec"; - reg = <0x1002b000 0x4000>; + reg = <0x1002b000 0x1000>; interrupts = <50>; clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, <&clks IMX27_CLK_FEC_AHB_GATE>; diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts index 7198fe3798c62b52c2c86f5d2f895cc5179571fe..070e59cbdd8b76659506cf45a078a1e302bbe942 100644 --- a/arch/arm/boot/dts/imx28-apf28.dts +++ b/arch/arm/boot/dts/imx28-apf28.dts @@ -78,7 +78,7 @@ mac0: ethernet@800f0000 { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 0>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index 1f38a052ad4b0d8767b712994d3c97ca110ca8ff..7ac4f1af16ac856d243674c630b9207da71d8335 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -110,6 +110,13 @@ timing0: timing0 { }; }; }; + + can0: can@80032000 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + xceiver-supply = <®_can0_vcc>; + status = "okay"; + }; }; apbx@80040000 { @@ -130,6 +137,13 @@ pwm: pwm@80064000 { status = "okay"; }; + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + fsl,uart-has-rtscts; + status = "okay"; + }; + usbphy0: usbphy@8007c000 { status = "okay"; }; @@ -143,7 +157,8 @@ usbphy1: usbphy@8007e000 { ahb@80080000 { usb0: usb@80080000 { pinctrl-names = "default"; - pinctrl-0 = <&usb0_otg_apf28dev>; + pinctrl-0 = <&usb0_otg_apf28dev + &usb0_id_pins_b>; vbus-supply = <®_usb0_vbus>; status = "okay"; }; @@ -156,7 +171,7 @@ mac1: ethernet@800f4000 { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac1_pins_a>; - phy-reset-gpios = <&gpio0 23 0>; + phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; status = "okay"; }; }; @@ -175,6 +190,14 @@ reg_usb0_vbus: regulator@0 { gpio = <&gpio1 23 1>; enable-active-high; }; + + reg_can0_vcc: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "can0_vcc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; }; leds { @@ -200,8 +223,9 @@ gpio-keys { user-button { label = "User button"; - gpios = <&gpio0 17 0>; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; linux,code = <0x100>; + gpio-key,wakeup; }; }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 47f68ac868d4b6ab20751d5d2d457a31f10a7ef6..4e073e8547425ee189a6c91331ade03052e1d999 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -829,6 +829,19 @@ MX28_PAD_SSP3_SS0__SSP3_D3 fsl,pull-up = ; }; + spi3_pins_b: spi3@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SSP3_SCK__SSP3_SCK + MX28_PAD_SSP3_MOSI__SSP3_CMD + MX28_PAD_SSP3_MISO__SSP3_D0 + MX28_PAD_SSP3_SS0__SSP3_D3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + usb0_pins_a: usb0@0 { reg = <0>; fsl,pinmux-ids = < @@ -900,7 +913,7 @@ dma_apbx: dma-apbx@80024000 { 80 81 68 69 70 71 72 73 74 75 76 77>; - interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", + interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", "saif0", "saif1", "i2c0", "i2c1", "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; @@ -1197,6 +1210,7 @@ usb1: usb@80090000 { interrupts = <92>; clocks = <&clks 61>; fsl,usbphy = <&usbphy1>; + dr_mode = "host"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 6932928f3b45c99cc4d807edacf9475e55650056..b6478e97d6a7eb8cbb6478470d4a5e10794afaff 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -318,6 +318,7 @@ usbhost1: usb@53ff4400 { clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 1>; fsl,usbphy = <&usbphy1>; + dr_mode = "host"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 620b0f030591209f26dc0ad19af226b9a8310ed8..e2457138311f8661fd063da8be351a84cef49ced 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -197,6 +197,7 @@ usbh1: usb@53f80200 { reg = <0x53f80200 0x0200>; interrupts = <14>; clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; + dr_mode = "host"; status = "disabled"; }; @@ -205,6 +206,7 @@ usbh2: usb@53f80400 { reg = <0x53f80400 0x0200>; interrupts = <16>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; + dr_mode = "host"; status = "disabled"; }; @@ -213,6 +215,7 @@ usbh3: usb@53f80600 { reg = <0x53f80600 0x0200>; interrupts = <17>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; + dr_mode = "host"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index c0116cffc513436d54584ee9d1c9d8ad933ebb83..f46fe9bf0bcb37a903d7ee05d67cc3289516acac 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -265,6 +265,7 @@ usbh1: usb@73f80200 { interrupts = <14>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 1>; + dr_mode = "host"; status = "disabled"; }; @@ -274,6 +275,7 @@ usbh2: usb@73f80400 { interrupts = <16>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; status = "disabled"; }; @@ -283,6 +285,7 @@ usbh3: usb@73f80600 { interrupts = <17>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 3>; + dr_mode = "host"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index ff4fa7ecacd86ef1ddc7f4a63f23e32af5d2808c..c3e3ca9362fbb78b6b2ecb8ec0125b83abdb7352 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -309,6 +309,7 @@ usbh1: usb@53f80200 { clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 1>; fsl,usbphy = <&usbphy1>; + dr_mode = "host"; status = "disabled"; }; @@ -318,6 +319,7 @@ usbh2: usb@53f80400 { interrupts = <16>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; status = "disabled"; }; @@ -327,6 +329,7 @@ usbh3: usb@53f80600 { interrupts = <17>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 3>; + dr_mode = "host"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index 9cd06e5e59f00e35b579c07118eed164872330b9..d4c4a22db4888269c26a2294add2421dd4349c7e 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -83,3 +83,7 @@ &i2c2 { &ipu1_di0_disp0 { remote-endpoint = <&display0_in>; }; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts index b413e24288dcb08b5ba5b73d461eaf67c3e2b175..15203f0e9725cb775dac06399ab212d12479e536 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts @@ -72,3 +72,7 @@ &i2c2 { &ipu1_di0_disp0 { remote-endpoint = <&display0_in>; }; + +&pwm3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts index 58aa8f2b0f260f7613da2890cfce01a0fac25096..e0b7fe8e18f886608e7dd302409f0d045e1ebb29 100644 --- a/arch/arm/boot/dts/imx6dl-cubox-i.dts +++ b/arch/arm/boot/dts/imx6dl-cubox-i.dts @@ -1,5 +1,43 @@ /* * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts index 44a0e6736bb1217369b3c45e32ad4dbb007cea03..7369d2d7da3e545904d84175f353e220d267fef0 100644 --- a/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts @@ -1,6 +1,44 @@ /* * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts index 9efd8b0c8011fea501c0033e3da5dd5cfed3e849..670bd8c4c847514f11bc3118f2b561b86fc8099d 100644 --- a/arch/arm/boot/dts/imx6q-cubox-i.dts +++ b/arch/arm/boot/dts/imx6q-cubox-i.dts @@ -1,5 +1,43 @@ /* * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts index c2bf8476ce45f8c496ea18e389bebc7839cb0d85..0f6044553a2490106c413b86bba4c5bbf515f6c9 100644 --- a/arch/arm/boot/dts/imx6q-hummingboard.dts +++ b/arch/arm/boot/dts/imx6q-hummingboard.dts @@ -1,6 +1,44 @@ /* * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 93ec79bb6b35c54b451ff8ccb9775387f8574aa4..399103b8e2c948110154fa0b109e917a192061b0 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -294,19 +294,21 @@ lvds1_mux_3: endpoint { }; &mipi_dsi { - port@2 { - reg = <2>; + ports { + port@2 { + reg = <2>; - mipi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_mipi>; + mipi_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_mipi>; + }; }; - }; - port@3 { - reg = <3>; + port@3 { + reg = <3>; - mipi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_mipi>; + mipi_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_mipi>; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index 6a524ca011e70df048939fbc5ef0659c88a660e9..d033bb1820602773c9c0beaf661f779381344221 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -1,8 +1,48 @@ /* * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include "imx6qdl-microsom.dtsi" #include "imx6qdl-microsom-ar8035.dtsi" +#include +#include / { ir_recv: ir-receiver { @@ -66,6 +106,18 @@ sound-spdif { spdif-controller = <&spdif>; spdif-out; }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio_key>; + pinctrl-names = "default"; + + button_0 { + label = "Button 0"; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; }; &hdmi { @@ -170,9 +222,19 @@ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 >; }; + + pinctrl_gpio_key: gpio-key { + fsl,pins = < + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 + >; + }; }; }; +&pwm1 { + status = "okay"; +}; + &spdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_spdif>; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi index 62841e85a91e45d38e71c6e7a65d2d8f8b024154..151a3db2aea957f39d4437812e06a46455e117cb 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -1,5 +1,43 @@ /* * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include "imx6qdl-microsom.dtsi" #include "imx6qdl-microsom-ar8035.dtsi" @@ -50,6 +88,19 @@ reg_usbotg_vbus: usb-otg-vbus { }; }; + sound-sgtl5000 { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "On-board Codec"; + mux-ext-port = <5>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; + sound-spdif { compatible = "fsl,imx-audio-spdif"; model = "On-board SPDIF"; @@ -59,6 +110,10 @@ sound-spdif { }; }; +&audmux { + status = "okay"; +}; + &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; @@ -75,16 +130,24 @@ &hdmi { &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_i2c1>; - - /* - * Not fitted on Carrier-1 board... yet status = "okay"; + /* Pro baseboard model */ rtc: pcf8523@68 { compatible = "nxp,pcf8523"; reg = <0x68>; }; - */ + + /* Pro baseboard model */ + sgtl5000: sgtl5000@0a { + clocks = <&clks IMX6QDL_CLK_CKO>; + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; }; &i2c2 { @@ -129,6 +192,20 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 >; }; + pinctrl_hummingboard_pwm1: pwm1grp { + fsl,pins = ; + }; + + pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + pinctrl_hummingboard_spdif: hummingboard-spdif { fsl,pins = ; }; @@ -168,12 +245,28 @@ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 }; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + status = "okay"; +}; + &spdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_spdif>; status = "okay"; }; +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + &usbh1 { disable-over-current; vbus-supply = <®_usbh1_vbus>; diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi index db9f45b2c57304603a78db4c20ca50a0f133c247..4a1820309cdb82e1ac0c9dcdb8fd5b11aa306a02 100644 --- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi +++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi @@ -3,6 +3,44 @@ * * This describes the hookup for an AR8035 to the iMX6 on the SolidRun * MicroSOM. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ &fec { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi index 79eac6849d4c9d8964882d1e64435d868c2c7c01..349f82be816eb77c0119cdeeba4eb424711b9bb0 100644 --- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi +++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi @@ -1,5 +1,43 @@ /* * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ &iomuxc { diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 19cc269a08d4d7acdc3572821b32399ee584f824..1ce6133b67f5c65fefd2fe85d368ac455b199950 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -31,6 +31,7 @@ reg_usb_otg_vbus: regulator@0 { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio4 15 0>; + enable-active-high; }; reg_usb_h1_vbus: regulator@1 { @@ -40,6 +41,7 @@ reg_usb_h1_vbus: regulator@1 { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 0 0>; + enable-active-high; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 009abd69385d854c15c4b35bc98aca87a1ef8d84..3b24b12651b2b86ee1a74d5baccca435778ddd3e 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -182,6 +182,33 @@ vgen6_reg: vgen6 { }; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + max7310_a: gpio@30 { + compatible = "maxim,max7310"; + reg = <0x30>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_b: gpio@32 { + compatible = "maxim,max7310"; + reg = <0x32>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_c: gpio@34 { + compatible = "maxim,max7310"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -265,6 +292,13 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_pwm3: pwm1grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index d6c69ec443149da28012034ceea65ac2ba522539..f74a8ded515f22b9985b8d48b370a45c34e9d88e 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -53,6 +53,7 @@ intc: interrupt-controller@00a01000 { interrupt-controller; reg = <0x00a01000 0x1000>, <0x00a00100 0x100>; + interrupt-parent = <&intc>; }; clocks { @@ -82,7 +83,7 @@ soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - interrupt-parent = <&intc>; + interrupt-parent = <&gpc>; ranges; dma_apbh: dma-apbh@00110000 { @@ -122,6 +123,7 @@ timer@00a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; interrupts = <1 13 0xf01>; + interrupt-parent = <&intc>; clocks = <&clks IMX6QDL_CLK_TWD>; }; @@ -357,6 +359,7 @@ pwm1: pwm@02080000 { clocks = <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_PWM1>; clock-names = "ipg", "per"; + status = "disabled"; }; pwm2: pwm@02084000 { @@ -367,6 +370,7 @@ pwm2: pwm@02084000 { clocks = <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_PWM2>; clock-names = "ipg", "per"; + status = "disabled"; }; pwm3: pwm@02088000 { @@ -377,6 +381,7 @@ pwm3: pwm@02088000 { clocks = <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_PWM3>; clock-names = "ipg", "per"; + status = "disabled"; }; pwm4: pwm@0208c000 { @@ -387,6 +392,7 @@ pwm4: pwm@0208c000 { clocks = <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_PWM4>; clock-names = "ipg", "per"; + status = "disabled"; }; can1: flexcan@02090000 { @@ -598,7 +604,7 @@ reg_pu: regulator-vddpu@140 { regulator-name = "vddpu"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; - regulator-always-on; + regulator-enable-ramp-delay = <150>; anatop-reg-offset = <0x140>; anatop-vol-bit-shift = <9>; anatop-vol-bit-width = <5>; @@ -658,7 +664,7 @@ snvs@020cc000 { #size-cells = <1>; ranges = <0 0x020cc000 0x4000>; - snvs-rtc-lp@34 { + snvs_rtc: snvs-rtc-lp@34 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; reg = <0x34 0x58>; interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, @@ -693,8 +699,19 @@ src: src@020d8000 { gpc: gpc@020dc000 { compatible = "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, <0 90 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + pu-supply = <®_pu>; + clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU2D_AXI>, + <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_VPU_AXI>; + #power-domain-cells = <1>; }; gpr: iomuxc-gpr@020e0000 { @@ -845,6 +862,7 @@ usbh1: usb@02184200 { clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; + dr_mode = "host"; status = "disabled"; }; @@ -854,6 +872,7 @@ usbh2: usb@02184400 { interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; status = "disabled"; }; @@ -863,6 +882,7 @@ usbh3: usb@02184600 { interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 3>; + dr_mode = "host"; status = "disabled"; }; @@ -1022,19 +1042,24 @@ mipi_dsi: mipi@021e0000 { reg = <0x021e0000 0x4000>; status = "disabled"; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; - mipi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_mipi>; + mipi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_mipi>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - mipi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_mipi>; + mipi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_mipi>; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts new file mode 100644 index 0000000000000000000000000000000000000000..64f7decf1fdcb5b2593377105521a0ff9aa3fb78 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-warp.dts @@ -0,0 +1,262 @@ +/* + * Copyright 2014, 2015 O.S. Systems Software LTDA. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include "imx6sl.dtsi" + +/ { + model = "WaRP Board"; + compatible = "warp,imx6sl-warp", "fsl,imx6sl"; + + memory { + reg = <0x80000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 0>; + enable-active-high; + }; + + reg_1p8v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ + <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ + <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ + <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + mmc-pwrseq = <&usdhc3_pwrseq>; + status = "okay"; +}; + +&iomuxc { + imx6sl-warp { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1 + MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1 + MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1 + MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 + MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 36ab8e054cee0a8ff5fcc1fb6938dc1d62a1e09f..a78e715e3982f7f821d01f386cc592e046e172f5 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -72,6 +72,7 @@ intc: interrupt-controller@00a01000 { interrupt-controller; reg = <0x00a01000 0x1000>, <0x00a00100 0x100>; + interrupt-parent = <&intc>; }; clocks { @@ -95,7 +96,7 @@ soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - interrupt-parent = <&intc>; + interrupt-parent = <&gpc>; ranges; ocram: sram@00900000 { @@ -568,7 +569,7 @@ snvs@020cc000 { #size-cells = <1>; ranges = <0 0x020cc000 0x4000>; - snvs-rtc-lp@34 { + snvs_rtc: snvs-rtc-lp@34 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; reg = <0x34 0x58>; interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, @@ -603,7 +604,14 @@ src: src@020d8000 { gpc: gpc@020dc000 { compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + pu-supply = <®_pu>; + clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, + <&clks IMX6SL_CLK_GPU2D_PODF>; + #power-domain-cells = <1>; }; gpr: iomuxc-gpr@020e0000 { @@ -699,6 +707,7 @@ usbh: usb@02184400 { interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts new file mode 100644 index 0000000000000000000000000000000000000000..c76b87cba275fcb043289bc5eede363e6ab3c90c --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dtsi" + +/ { + model = "Freescale i.MX6 SoloX SDB RevA Board"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2>; + status = "okay"; + + flash0: s25fl128s@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl128s"; + spi-max-frequency = <66000000>; + }; + + flash1: s25fl128s@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl128s"; + spi-max-frequency = <66000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 32f07d6b404239afd3c58c43ae2cb032478a37b5..0bfc4e7865b2995fcd009fe6abc9f83f5129cb5d 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -1,197 +1,40 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/dts-v1/; - -#include -#include -#include "imx6sx.dtsi" +#include "imx6sx-sdb.dtsi" / { - model = "Freescale i.MX6 SoloX SDB Board"; - compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x80000000 0x40000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - volume-up { - label = "Volume Up"; - gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vcc_sd3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_sd3>; - regulator-name = "VCC_SD3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_psu_5v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "PSU-5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_lcd_3v3: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "lcd-3v3"; - gpio = <&gpio3 27 0>; - enable-active-high; - }; - - reg_peri_3v3: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_peri_3v3>; - regulator-name = "peri_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_enet_3v3: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_3v3>; - regulator-name = "enet_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - }; - }; - - sound { - compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <6>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; + model = "Freescale i.MX6 SoloX SDB RevB Board"; }; -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-supply = <®_enet_3v3>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - }; - }; +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; }; -&fec2 { +&i2c1 { + clock-frequency = <100000>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; - phy-handle = <ðphy2>; + pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; + compatible = "fsl,pfuze200"; reg = <0x08>; regulators { @@ -203,14 +46,6 @@ sw1a_reg: sw1ab { regulator-ramp-delay = <6250>; }; - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - sw2_reg: sw2 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; @@ -232,11 +67,6 @@ sw3b_reg: sw3b { regulator-always-on; }; - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - swbst_reg: swbst { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5150000>; @@ -292,401 +122,24 @@ vgen6_reg: vgen6 { }; }; -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6SX_CLK_AUDIO>; - DCVDD-supply = <&vgen4_reg>; - DBVDD-supply = <&vgen4_reg>; - AVDD-supply = <&vgen4_reg>; - CPVDD-supply = <&vgen4_reg>; - MICVDD-supply = <&vgen3_reg>; - PLLVDD-supply = <&vgen4_reg>; - SPKVDD1-supply = <®_psu_5v>; - SPKVDD2-supply = <®_psu_5v>; - }; -}; - -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hback-porch = <89>; - hfront-porch = <164>; - vback-porch = <23>; - vfront-porch = <10>; - hsync-len = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - &qspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; - flash0: s25fl128s@0 { - reg = <0>; + flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spansion,s25fl128s"; - spi-max-frequency = <66000000>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <0>; }; - flash1: s25fl128s@1 { - reg = <1>; + flash1: n25q256a@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spansion,s25fl128s"; - spi-max-frequency = <66000000>; - }; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart5 { /* for bluetooth */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - fsl,uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - enable-sdio-wakeup; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - enable-sdio-wakeup; - vmmc-supply = <&vcc_sd3>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - imx6x-sdb { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 - MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 - MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 - MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 - MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 - MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 - >; - }; - - pinctrl_enet_3v3: enet3v3grp { - fsl,pins = < - MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 - MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 - MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - >; - }; - - pinctrl_peri_3v3: peri3v3grp { - fsl,pins = < - MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 - >; - }; - - pinctrl_pwm3: pwm3grp-1 { - fsl,pins = < - MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 - >; - }; - - pinctrl_qspi2: qspi2grp { - fsl,pins = < - MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 - MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 - MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 - MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 - MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 - MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 - MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 - MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 - MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 - MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 - MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 - MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 - >; - }; - - pinctrl_vcc_sd3: vccsd3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 - MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usb_otg2: usbot2ggrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ - >; - }; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <1>; }; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cef04cef3a807f44efdc6a44fb754e0eb4b40b1e --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -0,0 +1,562 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX SDB Board"; + compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vcc_sd3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_sd3>; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_psu_5v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "PSU-5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_lcd_3v3: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-3v3"; + gpio = <&gpio3 27 0>; + enable-active-high; + }; + + reg_peri_3v3: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_peri_3v3>; + regulator-name = "peri_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_enet_3v3: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_3v3>; + regulator-name = "enet_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <6>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-supply = <®_enet_3v3>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rgmii"; + phy-handle = <ðphy2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SX_CLK_AUDIO>; + DCVDD-supply = <&vgen4_reg>; + DBVDD-supply = <&vgen4_reg>; + AVDD-supply = <&vgen4_reg>; + CPVDD-supply = <&vgen4_reg>; + MICVDD-supply = <&vgen3_reg>; + PLLVDD-supply = <&vgen4_reg>; + SPKVDD1-supply = <®_psu_5v>; + SPKVDD2-supply = <®_psu_5v>; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart5 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <&vcc_sd3>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + imx6x-sdb { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + + pinctrl_enet_3v3: enet3v3grp { + fsl,pins = < + MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 + MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + + pinctrl_peri_3v3: peri3v3grp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 + >; + }; + + pinctrl_pwm3: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_qspi2: qspi2grp { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 + >; + }; + + pinctrl_vcc_sd3: vccsd3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg2: usbot2ggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ + MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 7a24fee1e7aecf7bc16df8c241e42a5ba5e5e561..708175d59b9c31085877da68ad378765fe701369 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -88,6 +88,7 @@ intc: interrupt-controller@00a01000 { interrupt-controller; reg = <0x00a01000 0x1000>, <0x00a00100 0x100>; + interrupt-parent = <&intc>; }; clocks { @@ -131,7 +132,7 @@ soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - interrupt-parent = <&intc>; + interrupt-parent = <&gpc>; ranges; pmu { @@ -666,7 +667,7 @@ snvs: snvs@020cc000 { #size-cells = <1>; ranges = <0 0x020cc000 0x4000>; - snvs-rtc-lp@34 { + snvs_rtc: snvs-rtc-lp@34 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; reg = <0x34 0x58>; interrupts = , ; @@ -700,7 +701,10 @@ src: src@020d8000 { gpc: gpc@020dc000 { compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; interrupts = ; + interrupt-parent = <&intc>; }; iomuxc: iomuxc@020e0000 { @@ -763,6 +767,7 @@ usbh: usb@02184400 { fsl,usbmisc = <&usbmisc 2>; phy_type = "hsic"; fsl,anatop = <&anatop>; + dr_mode = "host"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/kirkwood-nas2big.dts new file mode 100644 index 0000000000000000000000000000000000000000..7427ec50b8290790e299b52547910b1db67d39ee --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nas2big.dts @@ -0,0 +1,143 @@ +/* + * Device Tree file for LaCie 2Big NAS + * + * Copyright (C) 2015 Seagate + * + * Author: Simon Guinot + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/dts-v1/; + +#include "kirkwood-netxbig.dtsi" + +/ { + model = "LaCie 2Big NAS"; + compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + rtc@10300 { + /* The on-chip RTC is not powered (no supercap). */ + status = "disabled"; + }; + spi@10600 { + /* + * A NAND flash is used instead of an SPI flash for + * the other netxbig-compatible boards. + */ + status = "disabled"; + }; + }; + + fan { + /* + * An I2C fan controller (GMT G762) is used but alarm is + * wired to a separate GPIO. + */ + compatible = "gpio-fan"; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + regulators: regulators { + status = "okay"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + + /* + * An external I2C RTC (Dallas DS1337S+) is used. This allows + * to power-up the board on an RTC alarm. The external RTC can + * be kept powered, even when the SoC is off. + */ + rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + interrupts = <43>; + }; + g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; + }; +}; + +&nand { + chip-delay = <50>; + status = "okay"; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x1000000>; + }; + + partition@1100000 { + label = "root"; + reg = <0x1100000 0x8000000>; + }; + + partition@9100000 { + label = "unused"; + reg = <0x9100000 0x6f00000>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts index 53dc37a3b6875dd10fcbe9babee959de4f5a95bd..13a44773b6dfa39fe02d4ce86f3344808e498d1b 100644 --- a/arch/arm/boot/dts/kirkwood-net2big.dts +++ b/arch/arm/boot/dts/kirkwood-net2big.dts @@ -27,6 +27,11 @@ memory { device_type = "memory"; reg = <0x00000000 0x10000000>; }; + + fan { + compatible = "gpio-fan"; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; }; ®ulators { diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index b67ede515bcdeb9decd615aac0a7b30b0951a30d..548441384d2a39488d7daffef79ed6c707576a86 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -150,5 +150,25 @@ ir_receiver: ir-receiver@c8100480 { interrupts = <0 15 1>; status = "disabled"; }; + + spifc: spi@c1108c80 { + compatible = "amlogic,meson6-spifc"; + reg = <0xc1108c80 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk81>; + status = "disabled"; + }; + + ethmac: ethernet@c9410000 { + compatible = "amlogic,meson6-dwmac", "snps,dwmac"; + reg = <0xc9410000 0x10000 + 0xc1108108 0x4>; + interrupts = <0 8 1>; + interrupt-names = "macirq"; + clocks = <&clk81>; + clock-names = "stmmaceth"; + status = "disabled"; + }; }; }; /* end of / */ diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts index d7d351a689447ea6449951200c632e19febf3b3b..1237faa63ce636d5c8c85d65b4cc9e32d9a5eab7 100644 --- a/arch/arm/boot/dts/meson6-atv1200.dts +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -64,3 +64,7 @@ memory { &uart_AO { status = "okay"; }; + +ðmac { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts new file mode 100644 index 0000000000000000000000000000000000000000..4f536bb1f0024a445a7b289988d62bcb39e70af7 --- /dev/null +++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts @@ -0,0 +1,128 @@ +/* + * Copyright 2014 Beniamino Galvani + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include +#include "meson8.dtsi" + +/ { + model = "MINIX NEO-X8"; + compatible = "minix,neo-x8", "amlogic,meson8"; + + aliases { + serial0 = &uart_AO; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue { + label = "x8:blue:power"; + gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_pins>; + pinctrl-names = "default"; + + pmic@32 { + compatible = "ricoh,rn5t618"; + reg = <0x32>; + + regulators { + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&spifc { + status = "okay"; + pinctrl-0 = <&spi_nor_pins>; + pinctrl-names = "default"; + + spi-flash@0 { + compatible = "mxicy,mx25l1606e"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <30000000>; + + partition@0 { + label = "boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "env"; + reg = <0x100000 0x10000>; + }; + }; +}; + +&ir_receiver { + status = "okay"; + pinctrl-0 = <&ir_recv_pins>; + pinctrl-names = "default"; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_pins>; + pnictrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 1f442a7fe03b758905205630ce3409105a88625a..a2ddcb8c545a01ebdcc86d3c011e348f5295619b 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -43,6 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include /include/ "meson.dtsi" / { @@ -89,4 +90,71 @@ clk81: clk@0 { compatible = "fixed-clock"; clock-frequency = <141666666>; }; + + pinctrl: pinctrl@c1109880 { + compatible = "amlogic,meson8-pinctrl"; + reg = <0xc1109880 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio: banks@c11080b0 { + reg = <0xc11080b0 0x28>, + <0xc11080e8 0x18>, + <0xc1108120 0x18>, + <0xc1108030 0x30>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_ao: ao-bank@c1108030 { + reg = <0xc8100014 0x4>, + <0xc810002c 0x4>, + <0xc8100024 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; + }; + + i2c_ao_pins: i2c_mst_ao { + mux { + groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; + function = "i2c_mst_ao"; + }; + }; + + spi_nor_pins: nor { + mux { + groups = "nor_d", "nor_q", "nor_c", "nor_cs"; + function = "nor"; + }; + }; + + ir_recv_pins: remote { + mux { + groups = "remote_input"; + function = "remote"; + }; + }; + + eth_pins: ethernet { + mux { + groups = "eth_tx_clk_50m", "eth_tx_en", + "eth_txd1", "eth_txd0", + "eth_rx_clk_in", "eth_rx_dv", + "eth_rxd1", "eth_rxd0", "eth_mdio", + "eth_mdc"; + function = "ethernet"; + }; + }; + }; + }; /* end of / */ diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 106b61b1003032e88ca8a679ed1d2d56da561f10..88b3cb128698fb9d2e0abf9cfc46134b4538477e 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -138,5 +138,10 @@ uart3: serial@11009000 { clocks = <&uart_clk>; status = "disabled"; }; + + wdt: watchdog@010000000 { + compatible = "mediatek,mt6589-wdt"; + reg = <0x10000000 0x44>; + }; }; }; diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi index 9565199bce7a0986e3641d0c5e421a6cfefef12c..4907c5085d4bd3c4947b4be2ae7d65611e0d79f9 100644 --- a/arch/arm/boot/dts/nspire-classic.dtsi +++ b/arch/arm/boot/dts/nspire-classic.dtsi @@ -51,6 +51,11 @@ &ahb_clk { compatible = "lsi,nspire-classic-ahb-divider"; }; + +&vbus_reg { + gpio = <&gpio 5 0>; +}; + / { memory { device_type = "memory"; diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts index 375b924f60d80326833c13e7fbfa5f54c87d37aa..08e0b81b338527463623244d91798364e20905f7 100644 --- a/arch/arm/boot/dts/nspire-cx.dts +++ b/arch/arm/boot/dts/nspire-cx.dts @@ -69,6 +69,10 @@ &keypad { 0x0709001d 0x070a0033 >; }; +&vbus_reg { + gpio = <&gpio 2 0>; +}; + / { model = "TI-NSPIRE CX"; compatible = "ti,nspire-cx"; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index a22ffe633b49b36a3f0d49a243ef7e04841f1af2..390c91aea16d479e1b7cc10b6a82a278d2732c8f 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -54,6 +54,20 @@ apb_pclk: apb_pclk { clocks = <&ahb_clk>; }; + usb_phy: usb_phy { + compatible = "usb-nop-xceiv"; + }; + + vbus_reg: vbus_reg { + compatible = "regulator-fixed"; + + regulator-name = "USB VBUS output"; + regulator-type = "voltage"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -65,8 +79,12 @@ spi: spi@A9000000 { }; usb0: usb@B0000000 { + compatible = "lsi,zevio-usb"; reg = <0xB0000000 0x1000>; interrupts = <8>; + + usb-phy = <&usb_phy>; + vbus-supply = <&vbus_reg>; }; usb1: usb@B4000000 { @@ -105,8 +123,11 @@ apb@90000000 { ranges; gpio: gpio@90000000 { + compatible = "lsi,zevio-gpio"; reg = <0x90000000 0x1000>; interrupts = <7>; + gpio-controller; + #gpio-cells = <2>; }; fast_timer: timer@90010000 { diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index e2b2e93d7b6160f364bcb4832cc593c09f9627ac..5b9a376cc31eee01e38a0cbd8a5cb16b8bf6c04f 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -14,47 +14,65 @@ / { compatible = "ti,omap2420", "ti,omap2"; ocp { - prcm: prcm@48008000 { - compatible = "ti,omap2-prcm"; - reg = <0x48008000 0x1000>; + l4: l4@48000000 { + compatible = "ti,omap2-l4", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x100000>; - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + prcm: prcm@8000 { + compatible = "ti,omap2-prcm"; + reg = <0x8000 0x1000>; - prcm_clockdomains: clockdomains { - }; - }; + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - scrm: scrm@48000000 { - compatible = "ti,omap2-scrm"; - reg = <0x48000000 0x1000>; + prcm_clockdomains: clockdomains { + }; + }; - scrm_clocks: clocks { + scm: scm@0 { + compatible = "ti,omap2-scm", "simple-bus"; + reg = <0x0 0x1000>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges = <0 0x0 0x1000>; + + omap2420_pmx: pinmux@30 { + compatible = "ti,omap2420-padconf", + "pinctrl-single"; + reg = <0x30 0x0113>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; }; - scrm_clockdomains: clockdomains { + counter32k: counter@4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x20>; + ti,hwmods = "counter_32k"; }; }; - counter32k: counter@48004000 { - compatible = "ti,omap-counter32k"; - reg = <0x48004000 0x20>; - ti,hwmods = "counter_32k"; - }; - - omap2420_pmx: pinmux@48000030 { - compatible = "ti,omap2420-padconf", "pinctrl-single"; - reg = <0x48000030 0x0113>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; - gpio1: gpio@48018000 { compatible = "ti,omap2-gpio"; reg = <0x48018000 0x200>; diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi index 805f75df1cf2011474a8fa119c95523acaffb163..93fed68839b9f66f8112713b28c92e7df86ea14a 100644 --- a/arch/arm/boot/dts/omap2430-clocks.dtsi +++ b/arch/arm/boot/dts/omap2430-clocks.dtsi @@ -8,12 +8,12 @@ * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { mcbsp3_mux_fck: mcbsp3_mux_fck { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; - reg = <0x02e8>; + reg = <0x78>; }; mcbsp3_fck: mcbsp3_fck { @@ -27,7 +27,7 @@ mcbsp4_mux_fck: mcbsp4_mux_fck { compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x02e8>; + reg = <0x78>; }; mcbsp4_fck: mcbsp4_fck { @@ -41,7 +41,7 @@ mcbsp5_mux_fck: mcbsp5_mux_fck { compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <4>; - reg = <0x02e8>; + reg = <0x78>; }; mcbsp5_fck: mcbsp5_fck { diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 0dc8de2782b1871772150b3a62ab7a92685da56a..11a7963be0035a002fa77c2bec6809b34444e584 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -14,60 +14,73 @@ / { compatible = "ti,omap2430", "ti,omap2"; ocp { - prcm: prcm@49006000 { - compatible = "ti,omap2-prcm"; - reg = <0x49006000 0x1000>; + l4_wkup: l4_wkup@49000000 { + compatible = "ti,omap2-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x49000000 0x31000>; - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + prcm: prcm@6000 { + compatible = "ti,omap2-prcm"; + reg = <0x6000 0x1000>; - prcm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@49002000 { - compatible = "ti,omap2-scrm"; - reg = <0x49002000 0x1000>; + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; + prcm_clockdomains: clockdomains { + }; }; - scrm_clockdomains: clockdomains { + scm: scm@2000 { + compatible = "ti,omap2-scm", "simple-bus"; + reg = <0x2000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x1000>; + + omap2430_pmx: pinmux@30 { + compatible = "ti,omap2430-padconf", + "pinctrl-single"; + reg = <0x30 0x0154>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x240>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x230 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap2430 { + regulator-name = "pbias_mmc_omap2430"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + + scm_clockdomains: clockdomains { + }; }; - }; - - counter32k: counter@49020000 { - compatible = "ti,omap-counter32k"; - reg = <0x49020000 0x20>; - ti,hwmods = "counter_32k"; - }; - - omap2430_pmx: pinmux@49002030 { - compatible = "ti,omap2430-padconf", "pinctrl-single"; - reg = <0x49002030 0x0154>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; - - omap2_scm_general: tisyscon@49002270 { - compatible = "syscon"; - reg = <0x49002270 0x240>; - }; - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0x230 0x4>; - syscon = <&omap2_scm_general>; - pbias_mmc_reg: pbias_mmc_omap2430 { - regulator-name = "pbias_mmc_omap2430"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + counter32k: counter@20000 { + compatible = "ti,omap-counter32k"; + reg = <0x20000 0x20>; + ti,hwmods = "counter_32k"; }; }; diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi index a1365ca926eb6a4bcd52f1099e7c1e5c882f8664..63965b8769732f7e2e30708c30b50ad3f9ee6968 100644 --- a/arch/arm/boot/dts/omap24xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi @@ -7,13 +7,13 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { mcbsp1_mux_fck: mcbsp1_mux_fck { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x0274>; + reg = <0x4>; }; mcbsp1_fck: mcbsp1_fck { @@ -27,7 +27,7 @@ mcbsp2_mux_fck: mcbsp2_mux_fck { compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <6>; - reg = <0x0274>; + reg = <0x4>; }; mcbsp2_fck: mcbsp2_fck { diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 25f7b0a22114ee6928e58e27ceeb61cf07b04c79..7c4dca122a91d99a9848a691ce96a917294f59eb 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -60,7 +60,6 @@ sound { ti,model = "omap3beagle"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; gpio_keys { @@ -150,7 +149,6 @@ etb@5401b000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0x5401b000 0x1000>; - coresight-default-sink; clocks = <&emu_src_ck>; clock-names = "apb_pclk"; port { diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index c792391ef090f11a77add8041f6c9e63ec3340e3..a5474113cd50647f4b945b8db7ea3ff3a7643c83 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -71,7 +71,6 @@ sound { ti,model = "omap3beagle"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; gpio_keys { @@ -145,7 +144,6 @@ etb@540000000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0x5401b000 0x1000>; - coresight-default-sink; clocks = <&emu_src_ck>; clock-names = "apb_pclk"; port { @@ -379,3 +377,55 @@ venc_out: endpoint { }; }; }; + +&gpmc { + status = "ok"; + ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ + + /* Chip select 0 */ + nand@0,0 { + reg = <0 0 4>; /* NAND I/O window, 4 bytes */ + interrupts = <20>; + ti,nand-ecc-opt = "ham1"; + nand-bus-width = <16>; + #address-cells = <1>; + #size-cells = <1>; + + gpmc,device-width = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <36>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <24>; + gpmc,adv-wr-off-ns = <36>; + gpmc,oe-on-ns = <6>; + gpmc,oe-off-ns = <48>; + gpmc,we-on-ns = <6>; + gpmc,we-off-ns = <30>; + gpmc,rd-cycle-ns = <72>; + gpmc,wr-cycle-ns = <72>; + gpmc,access-ns = <54>; + gpmc,wr-access-ns = <30>; + + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + partition@1c0000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + partition@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + partition@780000 { + label = "Filesystem"; + reg = <0x680000 0xf980000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts index 0ab748cf7749f18d90ad225a5d0aabac564fc53f..f5b5a1d96cd740920ab215f2a7b3fc2fdaa9136e 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts @@ -133,6 +133,16 @@ &mmc2 { non-removable; bus-width = <4>; cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 145 */ + ref-clock-frequency = <38400000>; + }; }; &dss { diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index 46eadb21b5ef5e97882e581f6e29f33bda2cd209..2294f5b0aa102d9195aa93b33a9e298ac91cba26 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -73,6 +73,16 @@ &mmc2 { non-removable; bus-width = <4>; cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */ + ref-clock-frequency = <38400000>; + }; }; &dss { diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi index d9e92b654f851e879fe8fb4d74bfdf66c4cd7af9..046cd7733c4f9afac93d5f5382b61fd228759b8c 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi @@ -16,7 +16,6 @@ sound { ti,model = "cm-t35"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; }; diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index 169037e5ff53cd83da50cfb16e70edfcc2c7d6ed..921de6605f075d878f407d925a5652195bd2b41d 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -48,7 +48,6 @@ sound { ti,model = "devkit8000"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; ti,audio-routing = "Ext Spk", "PREDRIVEL", "Ext Spk", "PREDRIVER", @@ -111,6 +110,8 @@ &gpmc { nand@0,0 { reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "sw"; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index 127f3e7c10c4fcade6d95a201ffeccf4b66d9297..346552b94d9f7705a80642dc8ce86ea6bad800d6 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -106,6 +106,16 @@ &mmc2 { non-removable; bus-width = <4>; cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */ + ref-clock-frequency = <38400000>; + }; }; &twl_gpio { diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index fb3a69604ed5ccebff4f90257c76ddfaad58a555..b9f68817bd6e636d5f1e657a3916de26c3aafcba 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -46,7 +46,6 @@ sound { ti,model = "gta04"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; spi_lcd { diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 8a63ad2286aa26eaadf6162a12a98e24437acf28..d5e5cd449b16757d269836609b16b35d34ecc039 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -22,7 +22,6 @@ sound { compatible = "ti,omap-twl4030"; ti,model = "igep2"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; vdd33: regulator-vdd33 { diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts index cc8bd0cd8cf83d47deaa18ea29cbe3a08675e19b..72f7cdc091fba03ca51b223ec4f49cc810be88f4 100644 --- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts +++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts @@ -42,4 +42,13 @@ &mmc2 { vmmc-supply = <&lbep5clwmc_wlen>; bus-width = <4>; non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 177 */ + }; }; diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts index 9326b282c94ab92aadc681cf362cddf8a575e98f..b899e341874a3dc84e9e898748fea314be0b84e4 100644 --- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts +++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts @@ -64,4 +64,13 @@ &mmc2 { vmmc-supply = <&lbep5clwmc_wlen>; bus-width = <4>; non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */ + }; }; diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index e81fb651d5d0f04a6a90a6abca434cd64dc5d21e..e63133304a341a3d7b2d3401003b351b2c821b32 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -38,7 +38,6 @@ sound { ti,model = "lilly-a83x"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; reg_vcc3: vcc3 { diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts index 9938b5dc1909c00f01e587f15a4a1c1d2a6bc665..f2e213931e09a21ed24f7e50b28a74d50eeca735 100644 --- a/arch/arm/boot/dts/omap3-n9.dts +++ b/arch/arm/boot/dts/omap3-n9.dts @@ -16,3 +16,40 @@ / { model = "Nokia N9"; compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3"; }; + +&i2c2 { + smia_1: camera@10 { + compatible = "nokia,smia"; + reg = <0x10>; + /* No reset gpio */ + vana-supply = <&vaux3>; + clocks = <&isp 0>; + clock-frequency = <9600000>; + nokia,nvm-size = <(16 * 64)>; + port { + smia_1_1: endpoint { + link-frequencies = /bits/ 64 <199200000 210000000 499200000>; + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi2a_ep>; + }; + }; + }; +}; + +&isp { + vdd-csiphy1-supply = <&vaux2>; + vdd-csiphy2-supply = <&vaux2>; + ports { + port@2 { + reg = <2>; + csi2a_ep: endpoint { + remote-endpoint = <&smia_1_1>; + clock-lanes = <2>; + data-lanes = <1 3>; + crc = <1>; + lane-polarities = <1 1 1>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index db80f9d376fadf569655fc9660526b16b0c10739..5f5e0f3d5b64fcb2283f72b9df923c793be7f75c 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -9,9 +9,23 @@ /dts-v1/; -#include "omap34xx-hs.dtsi" +#include "omap34xx.dtsi" #include +/* + * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall + * for omap AES HW crypto support. When linux kernel try to access memory of AES + * blocks then kernel receive "Unhandled fault: external abort on non-linefetch" + * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no + * crash anymore) omap AES support will be disabled for all Nokia N900 devices. + * There is "unofficial" version of bootloader which enables AES in L3 firewall + * but it is not widely used and to prevent kernel crash rather AES is disabled. + * There is also no runtime detection code if AES is disabled in L3 firewall... + */ +&aes { + status = "disabled"; +}; + / { model = "Nokia N900"; compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; @@ -484,6 +498,8 @@ tlv320aic3x: tlv320aic3x@18 { DRVDD-supply = <&vmmc2>; IOVDD-supply = <&vio>; DVDD-supply = <&vio>; + + ai3x-micbias-vg = <1>; }; tlv320aic3x_aux: tlv320aic3x@19 { @@ -495,6 +511,8 @@ tlv320aic3x_aux: tlv320aic3x@19 { DRVDD-supply = <&vmmc2>; IOVDD-supply = <&vio>; DVDD-supply = <&vio>; + + ai3x-micbias-vg = <2>; }; tsl2563: tsl2563@29 { @@ -609,6 +627,58 @@ &i2c3 { pinctrl-0 = <&i2c3_pins>; clock-frequency = <400000>; + + lis302dl: lis3lv02d@1d { + compatible = "st,lis3lv02d"; + reg = <0x1d>; + + Vdd-supply = <&vaux1>; + Vdd_IO-supply = <&vio>; + + interrupt-parent = <&gpio6>; + interrupts = <21 20>; /* 181 and 180 */ + + /* click flags */ + st,click-single-x; + st,click-single-y; + st,click-single-z; + + /* Limits are 0.5g * value */ + st,click-threshold-x = <8>; + st,click-threshold-y = <8>; + st,click-threshold-z = <10>; + + /* Click must be longer than time limit */ + st,click-time-limit = <9>; + + /* Kind of debounce filter */ + st,click-latency = <50>; + + /* Interrupt line 2 for click detection */ + st,irq2-click; + + st,wakeup-x-hi; + st,wakeup-y-hi; + st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ + + st,wakeup2-z-hi; + st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */ + + st,hipass1-disable; + st,hipass2-disable; + + st,axis-x = <1>; /* LIS3_DEV_X */ + st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ + st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ + + st,min-limit-x = <(-32)>; + st,min-limit-y = <3>; + st,min-limit-z = <3>; + + st,max-limit-x = <(-3)>; + st,max-limit-y = <32>; + st,max-limit-z = <32>; + }; }; &mmc1 { @@ -762,8 +832,8 @@ tsc2005@0 { touchscreen-fuzz-x = <4>; touchscreen-fuzz-y = <7>; touchscreen-fuzz-pressure = <2>; - touchscreen-max-x = <4096>; - touchscreen-max-y = <4096>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; touchscreen-max-pressure = <2048>; ti,x-plate-ohms = <280>; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index c41db94ee9c2749c34a99df9915f7da03ed7a020..800b379d368d54ca901fa25c1ab789287d6a30a0 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ -#include "omap36xx-hs.dtsi" +#include "omap36xx.dtsi" / { cpus { diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index 261c5589bfa3170e76cc8f469ac1d6ca07a02765..0885b34d5d7da252953c3aaef287a1e20b9dda63 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -16,3 +16,40 @@ / { model = "Nokia N950"; compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3"; }; + +&i2c2 { + smia_1: camera@10 { + compatible = "nokia,smia"; + reg = <0x10>; + /* No reset gpio */ + vana-supply = <&vaux3>; + clocks = <&isp 0>; + clock-frequency = <9600000>; + nokia,nvm-size = <(16 * 64)>; + port { + smia_1_1: endpoint { + link-frequencies = /bits/ 64 <210000000 333600000 398400000>; + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi2a_ep>; + }; + }; + }; +}; + +&isp { + vdd-csiphy1-supply = <&vaux2>; + vdd-csiphy2-supply = <&vaux2>; + ports { + port@2 { + reg = <2>; + csi2a_ep: endpoint { + remote-endpoint = <&smia_1_1>; + clock-lanes = <2>; + data-lanes = <3 1>; + crc = <1>; + lane-polarities = <1 1 1>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index d36bf0250a055427b595ee090b0cf56b6f03311b..18e1649681c1cdada8faf1673a8ac73c50bff288 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -27,7 +27,6 @@ sound { ti,model = "overo"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; /* HS USB Port 2 Power */ diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts new file mode 100644 index 0000000000000000000000000000000000000000..9619a28dfd7d694dfb2b4dd425d7094ff043751d --- /dev/null +++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2015 + * Nikolaus Schaller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * device tree for OpenPandora 1GHz with DM3730 + */ + +/dts-v1/; + +#include "omap36xx.dtsi" +#include "omap3-pandora-common.dtsi" + +/ { + model = "Pandora Handheld Console 1GHz"; + + compatible = "ti,omap36xx", "ti,omap3"; +}; + +&omap3_pmx_core2 { + + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + &control_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ + >; + }; + + control_pins: pinmux_control_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ + OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ + OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ + OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ + OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4) /* reserved.gpio_127 = MMC2_WP */ + OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 = MMC1_WP */ + OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_128 = LED_MMC1 */ + OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_129 = LED_MMC2 */ + + >; + }; +}; diff --git a/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/omap3-pandora-600mhz.dts new file mode 100644 index 0000000000000000000000000000000000000000..fb803a70a2bbd1c81f6bf136119541a862609120 --- /dev/null +++ b/arch/arm/boot/dts/omap3-pandora-600mhz.dts @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2015 + * Nikolaus Schaller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * device tree for OpenPandora with OMAP3530 + */ + +/dts-v1/; + +#include "omap34xx.dtsi" +#include "omap3-pandora-common.dtsi" + +/ { + model = "Pandora Handheld Console"; + + compatible = "ti,omap3"; +}; + +&omap3_pmx_core2 { + + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + &control_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ + OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ + OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ + OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ + >; + }; + + control_pins: pinmux_control_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ + OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ + OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ + OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ + OMAP3430_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ + >; + }; +}; diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..782ab1ff1d089eeac52214c7b18f77eab412eb14 --- /dev/null +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -0,0 +1,640 @@ +/* + * Copyright (C) 2015 + * Nikolaus Schaller + * + * Common device tree include for OpenPandora devices. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + aliases { + display0 = &lcd; + }; + + tv: connector@1 { + compatible = "connector-analog-tv"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; + + gpio-leds { + + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led@1 { + label = "pandora::sd1"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */ + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@2 { + label = "pandora::sd2"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* GPIO_129 */ + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led@3 { + label = "pandora::bluetooth"; + gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; /* GPIO_158 */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@4 { + label = "pandora::wifi"; + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; /* GPIO_159 */ + linux,default-trigger = "mmc2"; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + + up-button { + label = "up"; + linux,code = ; + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* GPIO_110 */ + gpio-key,wakeup; + }; + + down-button { + label = "down"; + linux,code = ; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* GPIO_103 */ + gpio-key,wakeup; + }; + + left-button { + label = "left"; + linux,code = ; + gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; /* GPIO_96 */ + gpio-key,wakeup; + }; + + right-button { + label = "right"; + linux,code = ; + gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; /* GPIO_98 */ + gpio-key,wakeup; + }; + + pageup-button { + label = "game 1"; + linux,code = ; + gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* GPIO_109 */ + gpio-key,wakeup; + }; + + pagedown-button { + label = "game 3"; + linux,code = ; + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* GPIO_106 */ + gpio-key,wakeup; + }; + + home-button { + label = "game 4"; + linux,code = ; + gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* GPIO_101 */ + gpio-key,wakeup; + }; + + end-button { + label = "game 2"; + linux,code = ; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* GPIO_111 */ + gpio-key,wakeup; + }; + + right-shift { + label = "l"; + linux,code = ; + gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* GPIO_102 */ + gpio-key,wakeup; + }; + + kp-plus { + label = "l2"; + linux,code = ; + gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* GPIO_97 */ + gpio-key,wakeup; + }; + + right-ctrl { + label = "r"; + linux,code = ; + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* GPIO_105 */ + gpio-key,wakeup; + }; + + kp-minus { + label = "r2"; + linux,code = ; + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* GPIO_107 */ + gpio-key,wakeup; + }; + + left-ctrl { + label = "ctrl"; + linux,code = ; + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* GPIO_104 */ + gpio-key,wakeup; + }; + + menu { + label = "menu"; + linux,code = ; + gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; /* GPIO_99 */ + gpio-key,wakeup; + }; + + hold { + label = "hold"; + linux,code = ; + gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* GPIO_176 */ + gpio-key,wakeup; + }; + + left-alt { + label = "alt"; + linux,code = ; + gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; /* GPIO_100 */ + gpio-key,wakeup; + }; + + lid { + label = "lid"; + linux,code = <0x00>; /* SW_LID lid shut */ + linux,input-type = <0x05>; /* EV_SW */ + gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; /* GPIO_108 */ + }; + }; +}; + +&omap3_pmx_core { + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dirdat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dirdat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dircmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* GPIO_157 = lcd reset */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + led_pins: pinmux_leds_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4) /* GPIO_128 */ + OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* GPIO_129 */ + OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4) /* GPIO_158 */ + OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4) /* GPIO_159 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4) /* GPIO_96 */ + OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4) /* GPIO_97 */ + OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* GPIO_98 */ + OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4) /* GPIO_99 */ + OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4) /* GPIO_100 */ + OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* GPIO_101 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* GPIO_102 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* GPIO_103 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* GPIO_104 */ + OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* GPIO_105 */ + OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* GPIO_106 */ + OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* GPIO_107 */ + OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* GPIO_108 */ + OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* GPIO_109 */ + OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4) /* GPIO_110 */ + OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* GPIO_111 */ + OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* GPIO_176 */ + >; + }; + + penirq_pins: pinmux_penirq_pins { + pinctrl-single,pins = < + /* here we could enable to wakeup the cpu from suspend by a pen touch */ + OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4) /* GPIO_94 */ + >; + }; + +}; + +&omap3_pmx_core2 { + /* define in CPU specific file that includes this one + * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD() + */ +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_power: power { + compatible = "ti,twl4030-power-reset"; + ti,use_poweroff; + }; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + + codec { + ti,ramp_delay_value = <3>; + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&twl_keypad { + keypad,num-rows = <8>; + keypad,num-columns = <6>; + linux,keymap = < + MATRIX_KEY(0, 0, KEY_9) + MATRIX_KEY(0, 1, KEY_8) + MATRIX_KEY(0, 2, KEY_I) + MATRIX_KEY(0, 3, KEY_J) + MATRIX_KEY(0, 4, KEY_N) + MATRIX_KEY(0, 5, KEY_M) + MATRIX_KEY(1, 0, KEY_0) + MATRIX_KEY(1, 1, KEY_7) + MATRIX_KEY(1, 2, KEY_U) + MATRIX_KEY(1, 3, KEY_H) + MATRIX_KEY(1, 4, KEY_B) + MATRIX_KEY(1, 5, KEY_SPACE) + MATRIX_KEY(2, 0, KEY_BACKSPACE) + MATRIX_KEY(2, 1, KEY_6) + MATRIX_KEY(2, 2, KEY_Y) + MATRIX_KEY(2, 3, KEY_G) + MATRIX_KEY(2, 4, KEY_V) + MATRIX_KEY(2, 5, KEY_FN) + MATRIX_KEY(3, 0, KEY_O) + MATRIX_KEY(3, 1, KEY_5) + MATRIX_KEY(3, 2, KEY_T) + MATRIX_KEY(3, 3, KEY_F) + MATRIX_KEY(3, 4, KEY_C) + MATRIX_KEY(4, 0, KEY_P) + MATRIX_KEY(4, 1, KEY_4) + MATRIX_KEY(4, 2, KEY_R) + MATRIX_KEY(4, 3, KEY_D) + MATRIX_KEY(4, 4, KEY_X) + MATRIX_KEY(5, 0, KEY_K) + MATRIX_KEY(5, 1, KEY_3) + MATRIX_KEY(5, 2, KEY_E) + MATRIX_KEY(5, 3, KEY_S) + MATRIX_KEY(5, 4, KEY_Z) + MATRIX_KEY(6, 0, KEY_L) + MATRIX_KEY(6, 1, KEY_2) + MATRIX_KEY(6, 2, KEY_W) + MATRIX_KEY(6, 3, KEY_A) + MATRIX_KEY(6, 4, KEY_RIGHTBRACE) + MATRIX_KEY(7, 0, KEY_ENTER) + MATRIX_KEY(7, 1, KEY_1) + MATRIX_KEY(7, 2, KEY_Q) + MATRIX_KEY(7, 3, KEY_LEFTSHIFT) + MATRIX_KEY(7, 4, KEY_LEFTBRACE ) + >; +}; + +/* backup battery charger */ +&charger { + ti,bb-uvolt = <3200000>; + ti,bb-uamp = <150>; +}; + +/* MMC2 */ +&vmmc2 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <3150000>; +}; + +/* LCD */ +&vaux1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +/* USB Host PHY */ +&vaux2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +/* available on expansion connector */ +&vaux3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +/* ADS7846 and nubs */ +&vaux4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +/* power audio DAC and LID sensor */ +&vsim { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; +}; + +&i2c2 { + clock-frequency = <100000>; + /* no clients so we should disable clock */ +}; + +&i2c3 { + clock-frequency = <100000>; + + bq27500@55 { + compatible = "ti,bq27500"; + reg = <0x55>; + }; + +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; /* GPIO_126 */ +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vmmc2>; + bus-width = <4>; + cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* GPIO_127 */ +}; + +/* bluetooth*/ +&uart1 { +}; + +/* spare (expansion connector) */ +&uart2 { +}; + +/* console (expansion connector) */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "sw"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + + #address-cells = <1>; + #size-cells = <1>; + + /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */ + + x-loader@0 { + label = "xloader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "uboot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "uboot-env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "boot"; + reg = <0x280000 0xa00000>; + }; + + filesystem@680000 { + label = "rootfs"; + reg = <0xc80000 0>; /* 0 = MTDPART_SIZ_FULL */ + }; + }; +}; + +&mcspi1 { + tsc2046@0 { + reg = <0>; /* CS0 */ + compatible = "ti,tsc2046"; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&penirq_pins>; + interrupt-parent = <&gpio3>; + interrupts = <30 0>; /* GPIO_94 */ + pendown-gpio = <&gpio3 30 0>; + vcc-supply = <&vaux4>; + + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <8000>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <4800>; + ti,x-plate-ohms = /bits/ 16 <40>; + ti,pressure-max = /bits/ 16 <255>; + + linux,wakeup; + }; + + lcd: lcd@1 { + reg = <1>; /* CS1 */ + compatible = "omapdss,tpo,td043mtea1"; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + + label = "lcd"; + reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; /* GPIO_157 */ + vcc-supply = <&vaux1>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + +}; + +/* n/a - used as GPIOs */ +&mcbsp1 { +}; + +/* audio DAC */ +&mcbsp2 { +}; + +/* bluetooth */ +&mcbsp3 { +}; + +/* to twl4030*/ +&mcbsp4 { +}; + +&venc { + status = "ok"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = < &dss_dpi_pins >; + + status = "ok"; + vdds_dsi-supply = <&vpll2>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index e89820a6776ef2d5628e85e681e1b998aadbfdce..7bd8d9a4f67fbaece7239df36f5c141126c62a50 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -8,7 +8,16 @@ */ /dts-v1/; -#include "omap34xx-hs.dtsi" +#include "omap34xx.dtsi" + +/* Secure omaps have some devices inaccessible depending on the firmware */ +&aes { + status = "disabled"; +}; + +&sham { + status = "disabled"; +}; / { cpus { @@ -45,7 +54,6 @@ sound { /* McBSP2 is used for onboard sound, same as on beagle */ ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; /* Regulator to enable/switch the vcc of the Wifi module */ diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index 6644f516a42bd9de5f5fb52a707051ad502e18a8..131448d86e67bdd4bff337529d01a35e232c6326 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -195,6 +195,16 @@ &mmc3 { cap-power-off-card; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 162 */ + ref-clock-frequency = <26000000>; + }; }; &uart1 { diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 3fdc84fddb70d06a2ae26db02fc2c9c9f6d8ee63..69a40cfc1f29dddbd515b4f821459442787d401a 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -87,6 +87,60 @@ ocp { ranges; ti,hwmods = "l3_main"; + l4_core: l4@48000000 { + compatible = "ti,omap3-l4-core", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x1000000>; + + scm: scm@2000 { + compatible = "ti,omap3-scm", "simple-bus"; + reg = <0x2000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + omap3_pmx_core: pinmux@30 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0x30 0x238>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x330>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; + + omap3_pmx_wkup: pinmux@a00 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0xa00 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + }; + }; + aes: aes@480c5000 { compatible = "ti,omap3-aes"; ti,hwmods = "aes"; @@ -123,19 +177,6 @@ cm_clockdomains: clockdomains { }; }; - scrm: scrm@48002000 { - compatible = "ti,omap3-scrm"; - reg = <0x48002000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - counter32k: counter@48320000 { compatible = "ti,omap-counter32k"; reg = <0x48320000 0x20>; @@ -161,37 +202,10 @@ sdma: dma-controller@48056000 { dma-requests = <96>; }; - omap3_pmx_core: pinmux@48002030 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x48002030 0x0238>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - omap3_pmx_wkup: pinmux@48002a00 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x48002a00 0x5c>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - omap3_scm_general: tisyscon@48002270 { - compatible = "syscon"; - reg = <0x48002270 0x2f0>; - }; - pbias_regulator: pbias_regulator { compatible = "ti,pbias-omap"; reg = <0x2b0 0x4>; - syscon = <&omap3_scm_general>; + syscon = <&scm_conf>; pbias_mmc_reg: pbias_mmc_omap2430 { regulator-name = "pbias_mmc_omap2430"; regulator-min-microvolt = <1800000>; @@ -442,6 +456,7 @@ mmc3: mmc@480ad000 { }; mmu_isp: mmu@480bd400 { + #iommu-cells = <0>; compatible = "ti,omap2-iommu"; reg = <0x480bd400 0x80>; interrupts = <24>; @@ -450,6 +465,7 @@ mmu_isp: mmu@480bd400 { }; mmu_iva: mmu@5d000000 { + #iommu-cells = <0>; compatible = "ti,omap2-iommu"; reg = <0x5d000000 0x80>; interrupts = <28>; diff --git a/arch/arm/boot/dts/omap34xx-hs.dtsi b/arch/arm/boot/dts/omap34xx-hs.dtsi deleted file mode 100644 index 1ff626489546cc570e8c6ad00207225ed1f81f41..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/omap34xx-hs.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/* Disabled modules for secure omaps */ - -#include "omap34xx.dtsi" - -/* Secure omaps have some devices inaccessible depending on the firmware */ -&aes { - status = "disabled"; -}; - -&sham { - status = "disabled"; -}; - -&timer12 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 3819c1e915915b2ad79395ce97323fbaa52ae439..4f6b2d5b1902e96114f12b1f8bd7d15ba0b9819e 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -8,6 +8,8 @@ * kind, whether express or implied. */ +#include + #include "omap3.dtsi" / { @@ -37,6 +39,21 @@ omap3_pmx_core2: pinmux@480025d8 { pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; + + isp: isp@480bc000 { + compatible = "ti,omap3-isp"; + reg = <0x480bc000 0x12fc + 0x480bd800 0x017c>; + interrupts = <24>; + iommus = <&mmu_isp>; + syscon = <&scm_conf 0xdc>; + ti,phy-type = ; + #clock-cells = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/omap36xx-hs.dtsi b/arch/arm/boot/dts/omap36xx-hs.dtsi deleted file mode 100644 index 2c7febb0e016cbfea1375d23892d184d243b60de..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/omap36xx-hs.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/* Disabled modules for secure omaps */ - -#include "omap36xx.dtsi" - -/* Secure omaps have some devices inaccessible depending on the firmware */ -&aes { - status = "disabled"; -}; - -&sham { - status = "disabled"; -}; - -&timer12 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 541704a59a5adcac655c7a23ea49123c6a4fe9de..86253de5a97a99ddb12ea5f41c72f3c59279fced 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -8,6 +8,8 @@ * kind, whether express or implied. */ +#include + #include "omap3.dtsi" / { @@ -69,6 +71,21 @@ omap3_pmx_core2: pinmux@480025a0 { pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; + + isp: isp@480bc000 { + compatible = "ti,omap3-isp"; + reg = <0x480bc000 0x12fc + 0x480bd800 0x0600>; + interrupts = <24>; + iommus = <&mmu_isp>; + syscon = <&scm_conf 0x2f0>; + ti,phy-type = ; + #clock-cells = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 5c375003bad106216109b5626264300433dabd1d..bbba5bdc4bc946d5cb9b179283c65f27ecdef1d9 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -79,13 +79,14 @@ wkup_l4_ick: wkup_l4_ick { clock-div = <1>; }; }; -&scrm_clocks { + +&scm_clocks { mcbsp5_mux_fck: mcbsp5_mux_fck { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <4>; - reg = <0x02d8>; + reg = <0x68>; }; mcbsp5_fck: mcbsp5_fck { @@ -99,7 +100,7 @@ mcbsp1_mux_fck: mcbsp1_mux_fck { compatible = "ti,composite-mux-clock"; clocks = <&core_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x0274>; + reg = <0x04>; }; mcbsp1_fck: mcbsp1_fck { @@ -113,7 +114,7 @@ mcbsp2_mux_fck: mcbsp2_mux_fck { compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <6>; - reg = <0x0274>; + reg = <0x04>; }; mcbsp2_fck: mcbsp2_fck { @@ -126,7 +127,7 @@ mcbsp3_mux_fck: mcbsp3_mux_fck { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; - reg = <0x02d8>; + reg = <0x68>; }; mcbsp3_fck: mcbsp3_fck { @@ -140,7 +141,7 @@ mcbsp4_mux_fck: mcbsp4_mux_fck { compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x02d8>; + reg = <0x68>; }; mcbsp4_fck: mcbsp4_fck { diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi index cb9458feb2e36fe3c2ff95b1e857bd6ea5e52dbb..ab7f87ae96f099e5fbb53ee786602ea5492ba698 100644 --- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi @@ -18,7 +18,7 @@ cpu_thermal: cpu_thermal { /* sensor ID */ thermal-sensors = <&bandgap 0>; - trips { + cpu_trips: trips { cpu_alert0: cpu_alert { temperature = <100000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ @@ -31,7 +31,7 @@ cpu_crit: cpu_crit { }; }; - cooling-maps { + cpu_cooling_maps: cooling-maps { map0 { trip = <&cpu_alert0>; cooling-device = diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 7c15fb2e2fe4098a7393bb7fa1239e37a4ebab3d..f1507bc8737ee61031d0166b915317c3bf16b238 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -448,6 +448,16 @@ &mmc5 { non-removable; bus-width = <4>; cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ + ref-clock-frequency = <38400000>; + }; }; &emif1 { diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 8aca8dae968ad276f193a3b3c969082a23dcc7e7..dac86ed7481f477ba315f67aef7dd7de17a67408 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -485,6 +485,17 @@ &mmc5 { non-removable; bus-width = <4>; cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1281"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; }; &emif1 { diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi index cc66af4192366fda0a1110a1770b3722b7579b2f..9bceeb7e1f0315d91d7aa8fe77bed9fdf5652064 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi @@ -65,4 +65,14 @@ &mmc4 { bus-width = <4>; cap-power-off-card; status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */ + ref-clock-frequency = <38400000>; + }; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index f2091d1c9c36c2995e08a4d63929df6c2679d243..f884d6adb71e8ed28371afd54c04528403ad29ba 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -124,99 +124,141 @@ ocp { interrupts = , ; - cm1: cm1@4a004000 { - compatible = "ti,omap4-cm1"; - reg = <0x4a004000 0x2000>; - - cm1_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + l4_cfg: l4@4a000000 { + compatible = "ti,omap4-l4-cfg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a000000 0x1000000>; - cm1_clockdomains: clockdomains { - }; - }; + cm1: cm1@4000 { + compatible = "ti,omap4-cm1"; + reg = <0x4000 0x2000>; - prm: prm@4a306000 { - compatible = "ti,omap4-prm"; - reg = <0x4a306000 0x3000>; - interrupts = ; + cm1_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; + cm1_clockdomains: clockdomains { + }; }; - prm_clockdomains: clockdomains { - }; - }; + cm2: cm2@8000 { + compatible = "ti,omap4-cm2"; + reg = <0x8000 0x3000>; - cm2: cm2@4a008000 { - compatible = "ti,omap4-cm2"; - reg = <0x4a008000 0x3000>; + cm2_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - cm2_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; + cm2_clockdomains: clockdomains { + }; }; - cm2_clockdomains: clockdomains { + omap4_scm_core: scm@2000 { + compatible = "ti,omap4-scm-core", "simple-bus"; + reg = <0x2000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x1000>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + }; }; - }; - - scrm: scrm@4a30a000 { - compatible = "ti,omap4-scrm"; - reg = <0x4a30a000 0x2000>; - scrm_clocks: clocks { + omap4_padconf_core: scm@100000 { + compatible = "ti,omap4-scm-padconf-core", + "simple-bus"; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges = <0 0x100000 0x1000>; + + omap4_pmx_core: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap4_padconf_global: omap4_padconf_global@5a0 { + compatible = "syscon"; + reg = <0x5a0 0x170>; + #address-cells = <1>; + #size-cells = <1>; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap4_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap4 { + regulator-name = "pbias_mmc_omap4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; }; - scrm_clockdomains: clockdomains { - }; - }; - - counter32k: counter@4a304000 { - compatible = "ti,omap-counter32k"; - reg = <0x4a304000 0x20>; - ti,hwmods = "counter_32k"; - }; - - omap4_pmx_core: pinmux@4a100040 { - compatible = "ti,omap4-padconf", "pinctrl-single"; - reg = <0x4a100040 0x0196>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - omap4_pmx_wkup: pinmux@4a31e040 { - compatible = "ti,omap4-padconf", "pinctrl-single"; - reg = <0x4a31e040 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap4_padconf_global: tisyscon@4a1005a0 { - compatible = "syscon"; - reg = <0x4a1005a0 0x170>; - }; - - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap4_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap4 { - regulator-name = "pbias_mmc_omap4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + l4_wkup: l4@300000 { + compatible = "ti,omap4-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x300000 0x40000>; + + counter32k: counter@4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x20>; + ti,hwmods = "counter_32k"; + }; + + prm: prm@6000 { + compatible = "ti,omap4-prm"; + reg = <0x6000 0x3000>; + interrupts = ; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + + scrm: scrm@a000 { + compatible = "ti,omap4-scrm"; + reg = <0xa000 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + + omap4_pmx_wkup: pinmux@1e040 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x1e040 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; }; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 77b5f70d0ebcc8279b1e8e3e45afbc92be2abc6a..7d24ae0306b56845c80c2c783dd818033a3a6cd1 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -128,7 +128,7 @@ mpu { * hierarchy. */ ocp { - compatible = "ti,omap4-l3-noc", "simple-bus"; + compatible = "ti,omap5-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -139,99 +139,141 @@ ocp { interrupts = , ; - prm: prm@4ae06000 { - compatible = "ti,omap5-prm"; - reg = <0x4ae06000 0x3000>; - interrupts = ; + l4_cfg: l4@4a000000 { + compatible = "ti,omap5-l4-cfg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a000000 0x22a000>; - prm_clocks: clocks { + scm_core: scm@2000 { + compatible = "ti,omap5-scm-core", "simple-bus"; + reg = <0x2000 0x1000>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges = <0 0x2000 0x800>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + }; }; - prm_clockdomains: clockdomains { + scm_padconf_core: scm@2800 { + compatible = "ti,omap5-scm-padconf-core", + "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2800 0x800>; + + omap5_pmx_core: pinmux@40 { + compatible = "ti,omap5-padconf", + "pinctrl-single"; + reg = <0x40 0x01b6>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap5_padconf_global: omap5_padconf_global@5a0 { + compatible = "syscon"; + reg = <0x5a0 0xec>; + #address-cells = <1>; + #size-cells = <1>; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap5_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; }; - }; - cm_core_aon: cm_core_aon@4a004000 { - compatible = "ti,omap5-cm-core-aon"; - reg = <0x4a004000 0x2000>; + cm_core_aon: cm_core_aon@4000 { + compatible = "ti,omap5-cm-core-aon"; + reg = <0x4000 0x2000>; - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - cm_core_aon_clockdomains: clockdomains { + cm_core_aon_clockdomains: clockdomains { + }; }; - }; - scrm: scrm@4ae0a000 { - compatible = "ti,omap5-scrm"; - reg = <0x4ae0a000 0x2000>; + cm_core: cm_core@8000 { + compatible = "ti,omap5-cm-core"; + reg = <0x8000 0x3000>; - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - scrm_clockdomains: clockdomains { + cm_core_clockdomains: clockdomains { + }; }; }; - cm_core: cm_core@4a008000 { - compatible = "ti,omap5-cm-core"; - reg = <0x4a008000 0x3000>; + l4_wkup: l4@4ae00000 { + compatible = "ti,omap5-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4ae00000 0x2b000>; - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; + counter32k: counter@4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x40>; + ti,hwmods = "counter_32k"; }; - cm_core_clockdomains: clockdomains { + prm: prm@6000 { + compatible = "ti,omap5-prm"; + reg = <0x6000 0x3000>; + interrupts = ; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; }; - }; - counter32k: counter@4ae04000 { - compatible = "ti,omap-counter32k"; - reg = <0x4ae04000 0x40>; - ti,hwmods = "counter_32k"; - }; + scrm: scrm@a000 { + compatible = "ti,omap5-scrm"; + reg = <0xa000 0x2000>; - omap5_pmx_core: pinmux@4a002840 { - compatible = "ti,omap5-padconf", "pinctrl-single"; - reg = <0x4a002840 0x01b6>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - omap5_pmx_wkup: pinmux@4ae0c840 { - compatible = "ti,omap5-padconf", "pinctrl-single"; - reg = <0x4ae0c840 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - omap5_padconf_global: tisyscon@4a002da0 { - compatible = "syscon"; - reg = <0x4A002da0 0xec>; - }; + scrm_clockdomains: clockdomains { + }; + }; - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap5_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + omap5_pmx_wkup: pinmux@c840 { + compatible = "ti,omap5-padconf", + "pinctrl-single"; + reg = <0xc840 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index b3154c0716525a77f41c602d219f2360bb0ab1f5..6c1511263a55deacd582b96bd4c57edad59300a8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -23,6 +23,7 @@ cpu@0 { next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu@1 { @@ -33,6 +34,7 @@ cpu@1 { next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu@2 { @@ -43,6 +45,7 @@ cpu@2 { next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu@3 { @@ -53,12 +56,23 @@ cpu@3 { next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <400>; + exit-latency-us = <900>; + min-residency-us = <3000>; + }; + }; }; cpu-pmu { @@ -139,26 +153,26 @@ acc3: clock-controller@20b8000 { reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; + saw0: power-controller@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; + saw1: power-controller@2099000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: regulator@20a9000 { - compatible = "qcom,saw2"; + saw2: power-controller@20a9000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: regulator@20b9000 { - compatible = "qcom,saw2"; + saw3: power-controller@20b9000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; }; @@ -166,6 +180,7 @@ saw3: regulator@20b9000 { gsbi1: gsbi@12440000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; + cell-index = <1>; reg = <0x12440000 0x100>; clocks = <&gcc GSBI1_H_CLK>; clock-names = "iface"; @@ -173,6 +188,8 @@ gsbi1: gsbi@12440000 { #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; + i2c1: i2c@12460000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x12460000 0x1000>; @@ -187,6 +204,7 @@ i2c1: i2c@12460000 { gsbi2: gsbi@12480000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; reg = <0x12480000 0x100>; clocks = <&gcc GSBI2_H_CLK>; clock-names = "iface"; @@ -194,6 +212,8 @@ gsbi2: gsbi@12480000 { #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; + i2c2: i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; @@ -208,6 +228,7 @@ i2c2: i2c@124a0000 { gsbi7: gsbi@16600000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; + cell-index = <7>; reg = <0x16600000 0x100>; clocks = <&gcc GSBI7_H_CLK>; clock-names = "iface"; @@ -215,6 +236,8 @@ gsbi7: gsbi@16600000 { #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; + serial@16640000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, @@ -239,6 +262,13 @@ gcc: clock-controller@900000 { #reset-cells = <1>; }; + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-apq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + mmcc: clock-controller@4000000 { compatible = "qcom,mmcc-apq8064"; reg = <0x4000000 0x1000>; @@ -349,5 +379,10 @@ sdcc4: sdcc@121c0000 { pinctrl-0 = <&sdc4_gpios>; }; }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-apq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 47370494d0f84ecf2cec66f4cd9ca22beb4f1269..d484d08163e9415557e17d05e34c567c7e2d9de1 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -1,4 +1,6 @@ #include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" / { model = "Qualcomm APQ8074 Dragonboard"; diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts index c9ff10821ad992b6f4df866fb9974f11e4a68993..f7725b96612c65475fec7f67445f4afb54c19e81 100644 --- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts +++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts @@ -1,4 +1,5 @@ #include "qcom-apq8084.dtsi" +#include "qcom-pma8084.dtsi" / { model = "Qualcomm APQ8084/IFC6540"; diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts index 8ecec58a9ff6bcc62139f17a99239925c5dbb924..cb43acfc5d1d9d0773243d42874d5bd1f5243e4f 100644 --- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts +++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts @@ -1,4 +1,5 @@ #include "qcom-apq8084.dtsi" +#include "qcom-pma8084.dtsi" / { model = "Qualcomm APQ 8084-MTP"; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 1f130bc16858d4d1b2bbfbbca031cb49755b067a..7084010ee61ba463024a9e4ba5d48caf327e3c05 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -21,6 +21,8 @@ cpu@0 { enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu@1 { @@ -30,6 +32,8 @@ cpu@1 { enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu@2 { @@ -39,6 +43,8 @@ cpu@2 { enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu@3 { @@ -48,6 +54,8 @@ cpu@3 { enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { @@ -55,6 +63,16 @@ L2: l2-cache { cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu { @@ -144,7 +162,27 @@ frame@f9028000 { }; }; - saw_l2: regulator@f9012000 { + saw0: power-controller@f9089000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; + + saw1: power-controller@f9099000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; + }; + + saw2: power-controller@f90a9000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw3: power-controller@f90b9000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; @@ -226,5 +264,21 @@ sdhci@f98a4900 { clock-names = "core", "iface"; status = "disabled"; }; + + spmi_bus: spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = <0 190 0>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index cb225dafe97cd83c9ae4cc19482ed55d4a71b8b3..9f727d8eadf6998561e748e0400e46299417f9b3 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -2,6 +2,7 @@ #include "skeleton.dtsi" #include +#include #include / { @@ -60,12 +61,35 @@ smem@41000000 { }; }; + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "simple-bus"; + lpass@28100000 { + compatible = "qcom,lpass-cpu"; + status = "disabled"; + clocks = <&lcc AHBIX_CLK>, + <&lcc MI2S_OSR_CLK>, + <&lcc MI2S_BIT_CLK>; + clock-names = "ahbix-clk", + "mi2s-osr-clk", + "mi2s-bit-clk"; + interrupts = <0 85 1>; + interrupt-names = "lpass-irq-lpaif"; + reg = <0x28100000 0x10000>; + reg-names = "lpass-lpaif"; + }; + qcom_pinmux: pinmux@800000 { compatible = "qcom,ipq8064-pinctrl"; reg = <0x800000 0x4000>; @@ -89,10 +113,14 @@ timer@200a000 { compatible = "qcom,kpss-timer", "qcom,msm-timer"; interrupts = <1 1 0x301>, <1 2 0x301>, - <1 3 0x301>; + <1 3 0x301>, + <1 4 0x301>, + <1 5 0x301>; reg = <0x0200a000 0x100>; clock-frequency = <25000000>, <32768>; + clocks = <&sleep_clk>; + clock-names = "sleep"; cpu-offset = <0x80000>; }; @@ -120,6 +148,7 @@ saw1: regulator@2099000 { gsbi2: gsbi@12480000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; reg = <0x12480000 0x100>; clocks = <&gcc GSBI2_H_CLK>; clock-names = "iface"; @@ -128,6 +157,8 @@ gsbi2: gsbi@12480000 { ranges; status = "disabled"; + syscon-tcsr = <&tcsr>; + serial@12490000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x12490000 0x1000>, @@ -155,6 +186,7 @@ i2c@124a0000 { gsbi4: gsbi@16300000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; reg = <0x16300000 0x100>; clocks = <&gcc GSBI4_H_CLK>; clock-names = "iface"; @@ -163,6 +195,8 @@ gsbi4: gsbi@16300000 { ranges; status = "disabled"; + syscon-tcsr = <&tcsr>; + serial@16340000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16340000 0x1000>, @@ -189,6 +223,7 @@ i2c@16380000 { gsbi5: gsbi@1a200000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; reg = <0x1a200000 0x100>; clocks = <&gcc GSBI5_H_CLK>; clock-names = "iface"; @@ -197,6 +232,8 @@ gsbi5: gsbi@1a200000 { ranges; status = "disabled"; + syscon-tcsr = <&tcsr>; + serial@1a240000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x1a240000 0x1000>, @@ -279,5 +316,18 @@ gcc: clock-controller@900000 { #clock-cells = <1>; #reset-cells = <1>; }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-ipq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-ipq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 0affd6193f56c987c5a2806f40705fbddb92cab2..20bbd19b996ecfc4b883e770f0800dbb4f288215 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -82,6 +82,7 @@ gcc: clock-controller@900000 { gsbi12: gsbi@19c00000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; reg = <0x19c00000 0x100>; clocks = <&gcc GSBI12_H_CLK>; clock-names = "iface"; @@ -89,6 +90,8 @@ gsbi12: gsbi@19c00000 { #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; + serial@19c40000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, @@ -196,6 +199,11 @@ sdcc3: sdcc@12180000 { vmmc-supply = <&vsdcc_fixed>; }; }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8660", "syscon"; + reg = <0x1a400000 0x100>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index e1b0d5cd9e3cb7860363169a4f58efc158d05ced..a02b984cc68d8e2704abcb175e54c061ed54f629 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -91,6 +91,13 @@ gcc: clock-controller@900000 { reg = <0x900000 0x4000>; }; + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-msm8960"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + clock-controller@4000000 { compatible = "qcom,mmcc-msm8960"; reg = <0x4000000 0x1000>; @@ -122,6 +129,7 @@ saw1: regulator@2099000 { gsbi5: gsbi@16400000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; reg = <0x16400000 0x100>; clocks = <&gcc GSBI5_H_CLK>; clock-names = "iface"; @@ -129,6 +137,8 @@ gsbi5: gsbi@16400000 { #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; + serial@16440000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16440000 0x1000>, @@ -238,5 +248,10 @@ sdcc3: sdcc@12180000 { vmmc-supply = <&vsdcc_fixed>; }; }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8960", "syscon"; + reg = <0x1a400000 0x100>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index cccc21b7c8fde929c3c118dde9c46be740179609..bd35b0674ff6894cd6518046d049b385e038a624 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -1,4 +1,6 @@ #include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" / { model = "Sony Xperia Z1"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index e265ec16a7879b013639821e2a7b2db56aa57989..37b47b5538b816bb51c251c521d58d18b7bbd806 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -21,6 +21,8 @@ cpu@0 { reg = <0>; next-level-cache = <&L2>; qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu@1 { @@ -30,6 +32,8 @@ cpu@1 { reg = <1>; next-level-cache = <&L2>; qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu@2 { @@ -39,6 +43,8 @@ cpu@2 { reg = <2>; next-level-cache = <&L2>; qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu@3 { @@ -48,6 +54,8 @@ cpu@3 { reg = <3>; next-level-cache = <&L2>; qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { @@ -55,6 +63,16 @@ L2: l2-cache { cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu { @@ -144,7 +162,27 @@ frame@f9028000 { }; }; - saw_l2: regulator@f9012000 { + saw0: power-controller@f9089000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; + + saw1: power-controller@f9099000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; + }; + + saw2: power-controller@f90a9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw3: power-controller@f90b9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; @@ -247,5 +285,21 @@ blsp_i2c11: i2c@f9967000 { #address-cells = <1>; #size-cells = <0>; }; + + spmi_bus: spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = <0 190 0>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..73813cc118f9e968dce4b20e9f2c385764439b80 --- /dev/null +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi @@ -0,0 +1,18 @@ +#include + +&spmi_bus { + + usid4: pm8841@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usid5: pm8841@5 { + compatible = "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..24c5088acea2a244f79ae5b4edf537c07b8e22e3 --- /dev/null +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -0,0 +1,18 @@ +#include + +&spmi_bus { + + usid0: pm8941@0 { + compatible ="qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usid1: pm8941@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..a5a4fe695a46afb08f054e9fd44044bfd4fb3285 --- /dev/null +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -0,0 +1,18 @@ +#include + +&spmi_bus { + + usid0: pma8084@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usid1: pma8084@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts deleted file mode 100644 index b3d8f844b57a8fc2713ef2ba678c316fc970137b..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Device Tree Source for the APE6EVM board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a73a4.dtsi" -#include - -/ { - model = "APE6EVM"; - compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"; - - aliases { - serial0 = &scifa0; - }; - - chosen { - bootargs = "ignore_loglevel rw"; - stdout-path = &scifa0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - vcc_mmc0: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "MMC0 Vcc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vcc_sdhi0: regulator@1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 76 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* Common 3.3V rail, used by several devices on APE6EVM */ - ape6evm_fixed_3v3: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - lbsc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x20000000>; - }; -}; - -&i2c5 { - status = "okay"; - vdd_dvfs: max8973@1b { - compatible = "maxim,max8973"; - reg = <0x1b>; - - regulator-min-microvolt = <935000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; - operating-points = < - /* kHz uV */ - 1950000 1115000 - 1462500 995000 - >; - voltage-tolerance = <1>; /* 1% */ -}; - -&cmt1 { - status = "okay"; -}; - -&pfc { - scifa0_pins: serial0 { - renesas,groups = "scifa0_data"; - renesas,function = "scifa0"; - }; - - mmc0_pins: mmc { - renesas,groups = "mmc0_data8", "mmc0_ctrl"; - renesas,function = "mmc0"; - }; - - sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - renesas,function = "sdhi0"; - }; - - sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; - }; -}; - -&mmcif0 { - vmmc-supply = <&vcc_mmc0>; - bus-width = <8>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "okay"; -}; - -&scifa0 { - pinctrl-0 = <&scifa0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - vmmc-supply = <&vcc_sdhi0>; - bus-width = <4>; - toshiba,mmc-wrprotect-disable; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi0_pins>; - status = "okay"; -}; - -&sdhi1 { - vmmc-supply = <&ape6evm_fixed_3v3>; - bus-width = <4>; - broken-cd; - toshiba,mmc-wrprotect-disable; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi1_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 0d50bef0123449f5763a3fbd0f38956ae8508d74..81a38ceee098087ecd05ab13fa5e700783648e29 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -22,7 +22,7 @@ aliases { }; chosen { - bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw"; stdout-path = &scifa0; }; @@ -72,50 +72,30 @@ ape6evm_fixed_3v3: regulator@3 { regulator-always-on; }; - lbsc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x20000000>; - - ethernet@8000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x08000000 0x1000>; - interrupt-parent = <&irqc1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&ape6evm_fixed_3v3>; - vddvario-supply = <&ape6evm_fixed_1v8>; - }; - }; - leds { compatible = "gpio-leds"; led1 { - gpios = <&pfc 28 GPIO_ACTIVE_LOW>; + gpios = <&pfc 28 GPIO_ACTIVE_HIGH>; label = "GNSS_EN"; }; led2 { - gpios = <&pfc 126 GPIO_ACTIVE_LOW>; + gpios = <&pfc 126 GPIO_ACTIVE_HIGH>; label = "NFC_NRST"; }; led3 { - gpios = <&pfc 132 GPIO_ACTIVE_LOW>; + gpios = <&pfc 132 GPIO_ACTIVE_HIGH>; label = "GNSS_NRST"; }; led4 { - gpios = <&pfc 232 GPIO_ACTIVE_LOW>; + gpios = <&pfc 232 GPIO_ACTIVE_HIGH>; label = "BT_WAKEUP"; }; led5 { - gpios = <&pfc 250 GPIO_ACTIVE_LOW>; + gpios = <&pfc 250 GPIO_ACTIVE_HIGH>; label = "STROBE"; }; led6 { - gpios = <&pfc 288 GPIO_ACTIVE_LOW>; + gpios = <&pfc 288 GPIO_ACTIVE_HIGH>; label = "BBRESETOUT"; }; }; @@ -123,10 +103,14 @@ led6 { keyboard { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + zero-key { gpios = <&pfc 324 GPIO_ACTIVE_LOW>; linux,code = ; label = "S16"; + gpio-key,wakeup; }; menu-key { @@ -184,6 +168,21 @@ &cpu0 { voltage-tolerance = <1>; /* 1% */ }; +&bsc { + ethernet@8000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x08000000 0x1000>; + interrupt-parent = <&irqc1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&ape6evm_fixed_3v3>; + vddvario-supply = <&ape6evm_fixed_1v8>; + }; +}; + &cmt1 { status = "okay"; }; @@ -208,6 +207,12 @@ sdhi1_pins: sd1 { renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; renesas,function = "sdhi1"; }; + + keyboard_pins: keyboard { + renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327", + "PORT328", "PORT329"; + bias-pull-up; + }; }; &mmcif0 { diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 38136d9f6d95a16ea0bb08f846ba4522a4d469aa..0fd889f88109de173c8760d7a7412ec0bc758b1d 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -9,6 +9,7 @@ * kind, whether express or implied. */ +#include #include #include @@ -27,9 +28,15 @@ cpu0: cpu@0 { compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; + power-domains = <&pd_a2sl>; }; }; + ptm { + compatible = "arm,coresight-etm3x"; + power-domains = <&pd_d4>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -41,11 +48,13 @@ timer { dbsc1: memory-controller@e6790000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe6790000 0 0x10000>; + power-domains = <&pd_a3bc>; }; dbsc2: memory-controller@e67a0000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe67a0000 0 0x10000>; + power-domains = <&pd_a3bc>; }; dmac: dma-multiplexer { @@ -87,38 +96,19 @@ dma0: dma-controller@e6700020 { "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15", "ch16", "ch17", "ch18", "ch19"; + clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; + power-domains = <&pd_a3sp>; }; }; - pfc: pfc@e6050000 { - compatible = "renesas,pfc-r8a73a4"; - reg = <0 0xe6050000 0 0x9000>; - gpio-controller; - #gpio-cells = <2>; - interrupts-extended = - <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, - <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, - <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, - <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, - <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, - <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, - <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, - <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, - <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, - <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, - <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, - <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, - <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, - <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, - <&irqc1 24 0>, <&irqc1 25 0>; - }; - i2c5: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x428>; interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -127,6 +117,9 @@ cmt1: timer@e6130000 { compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; reg = <0 0xe6130000 0 0x1004>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; + clock-names = "fck"; + power-domains = <&pd_c5>; renesas,channels-mask = <0xff>; @@ -170,6 +163,7 @@ irqc0: interrupt-controller@e61c0000 { <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>, <0 31 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_c4>; }; irqc1: interrupt-controller@e61c0200 { @@ -203,6 +197,31 @@ irqc1: interrupt-controller@e61c0200 { <0 55 IRQ_TYPE_LEVEL_HIGH>, <0 56 IRQ_TYPE_LEVEL_HIGH>, <0 57 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_c4>; + }; + + pfc: pfc@e6050000 { + compatible = "renesas,pfc-r8a73a4"; + reg = <0 0xe6050000 0 0x9000>; + gpio-controller; + #gpio-cells = <2>; + interrupts-extended = + <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, + <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, + <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, + <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, + <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, + <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, + <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, + <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, + <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, + <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, + <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, + <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, + <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, + <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, + <&irqc1 24 0>, <&irqc1 25 0>; + power-domains = <&pd_c5>; }; thermal@e61f0000 { @@ -210,6 +229,8 @@ thermal@e61f0000 { reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; + power-domains = <&pd_c5>; }; i2c0: i2c@e6500000 { @@ -218,6 +239,8 @@ i2c0: i2c@e6500000 { compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x428>; interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -227,6 +250,8 @@ i2c1: i2c@e6510000 { compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x428>; interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -236,6 +261,8 @@ i2c2: i2c@e6520000 { compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x428>; interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -245,6 +272,8 @@ i2c3: i2c@e6530000 { compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6530000 0 0x428>; interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -254,6 +283,8 @@ i2c4: i2c@e6540000 { compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6540000 0 0x428>; interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -263,6 +294,8 @@ i2c6: i2c@e6550000 { compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6550000 0 0x428>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -272,6 +305,8 @@ i2c7: i2c@e6560000 { compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6560000 0 0x428>; interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -281,6 +316,8 @@ i2c8: i2c@e6570000 { compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6570000 0 0x428>; interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -288,6 +325,9 @@ scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; + clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -295,6 +335,9 @@ scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; + clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -302,6 +345,9 @@ scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; reg = <0 0xe6c40000 0 0x100>; interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; + clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -309,6 +355,9 @@ scifa1: serial@e6c50000 { compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; reg = <0 0xe6c50000 0 0x100>; interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; + clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -316,6 +365,9 @@ scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; + clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -323,6 +375,9 @@ scifb3: serial@e6cf0000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6cf0000 0 0x100>; interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; + clock-names = "sci_ick"; + power-domains = <&pd_c4>; status = "disabled"; }; @@ -330,6 +385,8 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee100000 0 0x100>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; + power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; @@ -338,6 +395,8 @@ sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee120000 0 0x100>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; + power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; @@ -346,6 +405,8 @@ sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; + power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; @@ -354,6 +415,8 @@ mmcif0: mmc@ee200000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; + power-domains = <&pd_a3sp>; reg-io-width = <4>; status = "disabled"; }; @@ -362,6 +425,8 @@ mmcif1: mmc@ee220000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; + power-domains = <&pd_a3sp>; reg-io-width = <4>; status = "disabled"; }; @@ -377,4 +442,450 @@ gic: interrupt-controller@f1001000 { <0 0xf1006000 0 0x2000>; interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + + bsc: bus@fec10000 { + compatible = "renesas,bsc-r8a73a4", "renesas,bsc", + "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + reg = <0 0xfec10000 0 0x400>; + clocks = <&zb_clk>; + power-domains = <&pd_c4>; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clocks */ + extalr_clk: extalr_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "extalr"; + }; + extal1_clk: extal1_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "extal1"; + }; + extal2_clk: extal2_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "extal2"; + }; + fsiack_clk: fsiack_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "fsiack"; + }; + fsibck_clk: fsibck_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "fsibck"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a73a4-cpg-clocks"; + reg = <0 0xe6150000 0 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll2", + "pll2s", "pll2h", "z", "z2", + "i", "m3", "b", "m1", "m2", + "zx", "zs", "hp"; + }; + + /* Variable factor clocks (DIV6) */ + zb_clk: zb_clk@e6150010 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150010 0 4>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; + #clock-cells = <0>; + clock-output-names = "zb"; + }; + sdhi0_clk: sdhi0_clk@e6150074 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150074 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "sdhi0ck"; + }; + sdhi1_clk: sdhi1_clk@e6150078 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "sdhi1ck"; + }; + sdhi2_clk: sdhi2_clk@e615007c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "sdhi2ck"; + }; + mmc0_clk: mmc0_clk@e6150240 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + mmc1_clk: mmc1_clk@e6150244 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150244 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc1"; + }; + vclk1_clk: vclk1_clk@e6150008 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150008 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "vclk1"; + }; + vclk2_clk: vclk2_clk@e615000c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615000c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "vclk2"; + }; + vclk3_clk: vclk3_clk@e615001c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615001c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "vclk3"; + }; + vclk4_clk: vclk4_clk@e6150014 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150014 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "vclk4"; + }; + vclk5_clk: vclk5_clk@e6150034 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150034 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "vclk5"; + }; + fsia_clk: fsia_clk@e6150018 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150018 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&fsiack_clk>, <0>; + #clock-cells = <0>; + clock-output-names = "fsia"; + }; + fsib_clk: fsib_clk@e6150090 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150090 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&fsibck_clk>, <0>; + #clock-cells = <0>; + clock-output-names = "fsib"; + }; + mp_clk: mp_clk@e6150080 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150080 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&extal2_clk>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "mp"; + }; + m4_clk: m4_clk@e6150098 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150098 0 4>; + clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; + #clock-cells = <0>; + clock-output-names = "m4"; + }; + hsi_clk: hsi_clk@e615026c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615026c 0 4>; + clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, + <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; + #clock-cells = <0>; + clock-output-names = "hsi"; + }; + spuv_clk: spuv_clk@e6150094 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150094 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&extal2_clk>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "spuv"; + }; + + /* Fixed factor clocks */ + main_div2_clk: main_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "main_div2"; + }; + pll0_div2_clk: pll0_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll0_div2"; + }; + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + extal1_div2_clk: extal1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal1_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "extal1_div2"; + }; + + /* Gate clocks */ + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 + R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 + R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 + R8A73A4_CLK_DMAC + >; + clock-output-names = + "scifa0", "scifa1", "scifb0", "scifb1", + "scifb2", "scifb3", "dmac"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, + <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, + <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, + <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks + R8A73A4_CLK_HP>, <&cpg_clocks + R8A73A4_CLK_HP>, <&extalr_clk>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 + R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 + R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 + R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 + R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 + R8A73A4_CLK_CMT1 + >; + clock-output-names = + "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", + "mmcif0", "iic6", "iic7", "iic0", "iic1", + "cmt1"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>, + <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 + R8A73A4_CLK_IIC3 + >; + clock-output-names = + "iic5", "iic4", "iic3"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 + >; + clock-output-names = + "thermal", "iic8"; + }; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; + reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; + + pm-domains { + pd_c5: c5 { + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_c4: c4@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3sg: a3sg@16 { + reg = <16>; + #power-domain-cells = <0>; + }; + + pd_a3ex: a3ex@17 { + reg = <17>; + #power-domain-cells = <0>; + }; + + pd_a3sp: a3sp@18 { + reg = <18>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2us: a2us@19 { + reg = <19>; + #power-domain-cells = <0>; + }; + }; + + pd_a3sm: a3sm@20 { + reg = <20>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2sl: a2sl@21 { + reg = <21>; + #power-domain-cells = <0>; + }; + }; + + pd_a3km: a3km@22 { + reg = <22>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2kl: a2kl@23 { + reg = <23>; + #power-domain-cells = <0>; + }; + }; + }; + + pd_c4ma: c4ma@1 { + reg = <1>; + #power-domain-cells = <0>; + }; + + pd_c4cl: c4cl@2 { + reg = <2>; + #power-domain-cells = <0>; + }; + + pd_d4: d4@3 { + reg = <3>; + #power-domain-cells = <0>; + }; + + pd_a4bc: a4bc@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3bc: a3bc@5 { + reg = <5>; + #power-domain-cells = <0>; + }; + }; + + pd_a4l: a4l@6 { + reg = <6>; + #power-domain-cells = <0>; + }; + + pd_a4lc: a4lc@7 { + reg = <7>; + #power-domain-cells = <0>; + }; + + pd_a4mp: a4mp@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3mp: a3mp@9 { + reg = <9>; + #power-domain-cells = <0>; + }; + + pd_a3vc: a3vc@10 { + reg = <10>; + #power-domain-cells = <0>; + }; + }; + + pd_a4sf: a4sf@11 { + reg = <11>; + #power-domain-cells = <0>; + }; + + pd_a3r: a3r@12 { + reg = <12>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2rv: a2rv@13 { + reg = <13>; + #power-domain-cells = <0>; + }; + + pd_a2is: a2is@14 { + reg = <14>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 8a092605d641f7d40827104404baed8c8e819281..83c1c3ca1b8f1400010bb28fba1d8af706633e0a 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -431,6 +431,18 @@ dv_clk: dv_clk { clock-frequency = <27000000>; clock-output-names = "dv"; }; + fmsick_clk: fmsick_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "fmsick"; + }; + fmsock_clk: fmsock_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "fmsock"; + }; fsiack_clk: fsiack_clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -459,13 +471,78 @@ cpg_clocks: cpg_clocks@e6150000 { }; /* Variable factor clocks (DIV6) */ + vclk1_clk: vclk1_clk@e6150008 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150008 4>; + clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, + <&extal1_div2_clk>, <&extalr_clk>, <0>, + <0>; + #clock-cells = <0>; + clock-output-names = "vclk1"; + }; + vclk2_clk: vclk2_clk@e615000c { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615000c 4>; + clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, + <&extal1_div2_clk>, <&extalr_clk>, <0>, + <0>; + #clock-cells = <0>; + clock-output-names = "vclk2"; + }; + fmsi_clk: fmsi_clk@e6150010 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150010 4>; + clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "fmsi"; + }; + fmso_clk: fmso_clk@e6150014 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150014 4>; + clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "fmso"; + }; + fsia_clk: fsia_clk@e6150018 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150018 4>; + clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "fsia"; + }; sub_clk: sub_clk@e6150080 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150080 4>; - clocks = <&pllc1_div2_clk>; + clocks = <&pllc1_div2_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; #clock-cells = <0>; clock-output-names = "sub"; }; + spu_clk: spu_clk@e6150084 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150084 4>; + clocks = <&pllc1_div2_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "spu"; + }; + vou_clk: vou_clk@e6150088 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150088 4>; + clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, + <0>; + #clock-cells = <0>; + clock-output-names = "vou"; + }; + stpro_clk: stpro_clk@e615009c { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615009c 4>; + clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; + #clock-cells = <0>; + clock-output-names = "stpro"; + }; /* Fixed factor clocks */ pllc1_div2_clk: pllc1_div2_clk { diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index 46a884d4517566959992b98901d6a13b94064798..787fa6f9f46ddf4d2bd0d0db9abb82e4223c2413 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -16,17 +16,191 @@ /dts-v1/; #include "r8a7778.dtsi" +#include +#include / { model = "bockw"; compatible = "renesas,bockw", "renesas,r8a7778"; + aliases { + serial0 = &scif0; + }; + chosen { bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw"; + stdout-path = &scif0; }; memory { device_type = "memory"; reg = <0x60000000 0x10000000>; }; + + fixedregulator3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + system-clock-frequency = <11289600>; + }; + }; +}; + +&bsc { + ethernet@18300000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x18300000 0x1000>; + + phy-mode = "mii"; + interrupt-parent = <&irqpin>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + reg-io-width = <4>; + vddvario-supply = <&fixedregulator3v3>; + vdd33a-supply = <&fixedregulator3v3>; + }; +}; + +&extal_clk { + clock-frequency = <33333333>; +}; + +&i2c0 { + status = "okay"; + + ak4643: sound-codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + camera@41 { + compatible = "oki,ml86v7667"; + reg = <0x41>; + }; + + camera@43 { + compatible = "oki,ml86v7667"; + reg = <0x43>; + }; + + rx8581: rtc@51 { + compatible = "epson,rx8581"; + reg = <0x51>; + }; +}; + +&mmcif { + pinctrl-0 = <&mmc_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <8>; + broken-cd; + status = "okay"; +}; + +&irqpin { + status = "okay"; +}; + +&tmu0 { + status = "okay"; +}; + +&pfc { + scif0_pins: serial0 { + renesas,groups = "scif0_data_a", "scif0_ctrl"; + renesas,function = "scif0"; + }; + + mmc_pins: mmc { + renesas,groups = "mmc_data8", "mmc_ctrl"; + renesas,function = "mmc"; + }; + + sdhi0_pins: sd0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", + "sdhi0_cd"; + renesas,function = "sdhi0"; + }; + + hspi0_pins: hspi0 { + renesas,groups = "hspi0_a"; + renesas,function = "hspi0"; + }; + + usb0_pins: usb0 { + renesas,groups = "usb0"; + renesas,function = "usb0"; + }; + + usb1_pins: usb1 { + renesas,groups = "usb1"; + renesas,function = "usb1"; + }; + + vin0_pins: vin0 { + renesas,groups = "vin0_data8", "vin0_clk"; + renesas,function = "vin0"; + }; + + vin1_pins: vin1 { + renesas,groups = "vin1_data8", "vin1_clk"; + renesas,function = "vin1"; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <4>; + status = "okay"; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +}; + +&hspi0 { + pinctrl-0 = <&hspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl008k"; + reg = <0>; + spi-max-frequency = <104000000>; + m25p,fast-read; + + partition@0 { + label = "data(spi)"; + reg = <0x00000000 0x00100000>; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index ef8533910029620e5cb974bdafece1c2f90a3e1d..868f9730953350e9bb8b368b7b71efb5a85e7144 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -16,6 +16,7 @@ /include/ "skeleton.dtsi" +#include #include / { @@ -40,6 +41,24 @@ aliases { spi2 = &hspi2; }; + bsc: bus@1c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1c000000>; + }; + + ether: ethernet@fde00000 { + compatible = "renesas,ether-r8a7778"; + reg = <0xfde00000 0x400>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7778_CLK_ETHER>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe438000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -132,6 +151,7 @@ i2c0: i2c@ffc70000 { compatible = "renesas,i2c-r8a7778"; reg = <0xffc70000 0x1000>; interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C0>; status = "disabled"; }; @@ -141,6 +161,7 @@ i2c1: i2c@ffc71000 { compatible = "renesas,i2c-r8a7778"; reg = <0xffc71000 0x1000>; interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C1>; status = "disabled"; }; @@ -150,6 +171,7 @@ i2c2: i2c@ffc72000 { compatible = "renesas,i2c-r8a7778"; reg = <0xffc72000 0x1000>; interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C2>; status = "disabled"; }; @@ -159,6 +181,7 @@ i2c3: i2c@ffc73000 { compatible = "renesas,i2c-r8a7778"; reg = <0xffc73000 0x1000>; interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C3>; status = "disabled"; }; @@ -168,6 +191,8 @@ tmu0: timer@ffd80000 { interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, <0 33 IRQ_TYPE_LEVEL_HIGH>, <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_TMU0>; + clock-names = "fck"; #renesas,channels = <3>; @@ -180,6 +205,8 @@ tmu1: timer@ffd81000 { interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, <0 37 IRQ_TYPE_LEVEL_HIGH>, <0 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_TMU1>; + clock-names = "fck"; #renesas,channels = <3>; @@ -192,16 +219,75 @@ tmu2: timer@ffd82000 { interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, <0 41 IRQ_TYPE_LEVEL_HIGH>, <0 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_TMU2>; + clock-names = "fck"; #renesas,channels = <3>; status = "disabled"; }; + rcar_sound: sound@ffd90000 { + #sound-dai-cells = <1>; + compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1"; + reg = <0xffd90000 0x1000>, /* SRU */ + <0xffd91000 0x1240>, /* SSI */ + <0xfffe0000 0x24>; /* ADG */ + clocks = <&mstp3_clks R8A7778_CLK_SSI8>, + <&mstp3_clks R8A7778_CLK_SSI7>, + <&mstp3_clks R8A7778_CLK_SSI6>, + <&mstp3_clks R8A7778_CLK_SSI5>, + <&mstp3_clks R8A7778_CLK_SSI4>, + <&mstp0_clks R8A7778_CLK_SSI3>, + <&mstp0_clks R8A7778_CLK_SSI2>, + <&mstp0_clks R8A7778_CLK_SSI1>, + <&mstp0_clks R8A7778_CLK_SSI0>, + <&mstp5_clks R8A7778_CLK_SRU_SRC8>, + <&mstp5_clks R8A7778_CLK_SRU_SRC7>, + <&mstp5_clks R8A7778_CLK_SRU_SRC6>, + <&mstp5_clks R8A7778_CLK_SRU_SRC5>, + <&mstp5_clks R8A7778_CLK_SRU_SRC4>, + <&mstp5_clks R8A7778_CLK_SRU_SRC3>, + <&mstp5_clks R8A7778_CLK_SRU_SRC2>, + <&mstp5_clks R8A7778_CLK_SRU_SRC1>, + <&mstp5_clks R8A7778_CLK_SRU_SRC0>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg_clocks R8A7778_CLK_S1>; + clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", + "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.8", "src.7", "src.6", "src.5", "src.4", + "src.3", "src.2", "src.1", "src.0", + "clk_a", "clk_b", "clk_c", "clk_i"; + + status = "disabled"; + + rcar_sound,src { + src3: src@3 { }; + src4: src@4 { }; + src5: src@5 { }; + src6: src@6 { }; + src7: src@7 { }; + src8: src@8 { }; + src9: src@9 { }; + }; + + rcar_sound,ssi { + ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; }; + ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; }; + ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; + ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; + ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; + ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; + ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; + }; + }; + scif0: serial@ffe40000 { compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe40000 0x100>; interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF0>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -209,6 +295,8 @@ scif1: serial@ffe41000 { compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe41000 0x100>; interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF1>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -216,6 +304,8 @@ scif2: serial@ffe42000 { compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe42000 0x100>; interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF2>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -223,6 +313,8 @@ scif3: serial@ffe43000 { compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe43000 0x100>; interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF3>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -230,6 +322,8 @@ scif4: serial@ffe44000 { compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe44000 0x100>; interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF4>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -237,6 +331,8 @@ scif5: serial@ffe45000 { compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe45000 0x100>; interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF5>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -244,6 +340,7 @@ mmcif: mmc@ffe4e000 { compatible = "renesas,sh-mmcif"; reg = <0xffe4e000 0x100>; interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_MMC>; status = "disabled"; }; @@ -251,6 +348,7 @@ sdhi0: sd@ffe4c000 { compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4c000 0x100>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; status = "disabled"; }; @@ -258,6 +356,7 @@ sdhi1: sd@ffe4d000 { compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4d000 0x100>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; status = "disabled"; }; @@ -265,6 +364,7 @@ sdhi2: sd@ffe4f000 { compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4f000 0x100>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; status = "disabled"; }; @@ -272,6 +372,7 @@ hspi0: spi@fffc7000 { compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc7000 0x18>; interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -281,6 +382,7 @@ hspi1: spi@fffc8000 { compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc8000 0x18>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -290,8 +392,199 @@ hspi2: spi@fffc6000 { compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc6000 0x18>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* External input clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@ffc80000 { + compatible = "renesas,r8a7778-cpg-clocks"; + reg = <0xffc80000 0x80>; + #clock-cells = <1>; + clocks = <&extal_clk>; + clock-output-names = "plla", "pllb", "b", + "out", "p", "s", "s1"; + }; + + /* Audio clocks; frequencies are set by boards if applicable. */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "audio_clk_a"; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "audio_clk_b"; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "audio_clk_c"; + }; + + /* Fixed ratio clocks */ + g_clk: g_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "g"; + }; + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "i"; + }; + s3_clk: s3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "s3"; + }; + s4_clk: s4_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "s4"; + }; + z_clk: z_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLB>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "z"; + }; + + /* Gate clocks */ + mstp0_clks: mstp0_clks@ffc80030 { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc80030 4>; + clocks = <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_S>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_I2C0 R8A7778_CLK_I2C1 + R8A7778_CLK_I2C2 R8A7778_CLK_I2C3 + R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 + R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 + R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 + R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 + R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 + R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 + R8A7778_CLK_SSI3 R8A7778_CLK_SRU + R8A7778_CLK_HSPI + >; + clock-output-names = + "i2c0", "i2c1", "i2c2", "i2c3", "scif0", + "scif1", "scif2", "scif3", "scif4", "scif5", + "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", + "ssi2", "ssi3", "sru", "hspi"; + }; + mstp1_clks: mstp1_clks@ffc80034 { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc80034 4>, <0xffc80044 4>; + clocks = <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_S>, + <&cpg_clocks R8A7778_CLK_S>, + <&cpg_clocks R8A7778_CLK_P>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_ETHER R8A7778_CLK_VIN0 + R8A7778_CLK_VIN1 R8A7778_CLK_USB + >; + clock-output-names = + "ether", "vin0", "vin1", "usb"; + }; + mstp3_clks: mstp3_clks@ffc8003c { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc8003c 4>; + clocks = <&s4_clk>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_MMC R8A7778_CLK_SDHI0 + R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2 + R8A7778_CLK_SSI4 R8A7778_CLK_SSI5 + R8A7778_CLK_SSI6 R8A7778_CLK_SSI7 + R8A7778_CLK_SSI8 + >; + clock-output-names = + "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4", + "ssi5", "ssi6", "ssi7", "ssi8"; + }; + mstp5_clks: mstp5_clks@ffc80054 { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc80054 4>; + clocks = <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1 + R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3 + R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5 + R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7 + R8A7778_CLK_SRU_SRC8 + >; + clock-output-names = + "sru-src0", "sru-src1", "sru-src2", + "sru-src3", "sru-src4", "sru-src5", + "sru-src6", "sru-src7", "sru-src8"; + }; + }; }; diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index e83d40e24bcd48113d6bd1051f44413710af8b59..540756cdf3914a2af398d08734a48aa5b93ea21b 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -122,6 +122,12 @@ lvds_connector: endpoint { }; }; }; + + x3_clk: x3-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <65000000>; + }; }; &du { @@ -129,6 +135,9 @@ &du { pinctrl-names = "default"; status = "okay"; + clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; + clock-names = "du", "dclkin.0"; + ports { port@0 { endpoint { diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 0c3b6783b72add5d05001c35f39d1da6e55f141b..aaa4f258e279ccfac92ff1142faf4fe83ce3195d 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -222,6 +222,29 @@ vga_in: endpoint { }; }; }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + x13_clk: x13-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; }; &du { @@ -229,12 +252,26 @@ &du { pinctrl-names = "default"; status = "okay"; + clocks = <&mstp7_clks R8A7790_CLK_DU0>, + <&mstp7_clks R8A7790_CLK_DU1>, + <&mstp7_clks R8A7790_CLK_DU2>, + <&mstp7_clks R8A7790_CLK_LVDS0>, + <&mstp7_clks R8A7790_CLK_LVDS1>, + <&x13_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", + "dclkin.0", "dclkin.1"; + ports { port@0 { endpoint { remote-endpoint = <&adv7123_in>; }; }; + port@1 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; port@2 { lvds_connector: endpoint { }; @@ -506,6 +543,38 @@ adv7180: endpoint { }; }; }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; }; &iic3 { @@ -513,9 +582,27 @@ &iic3 { pinctrl-0 = <&iic3_pins>; status = "okay"; + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; + vdd_dvfs: regulator@68 { compatible = "dlg,da9210"; reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 4b38fc92011472e0684107cce5283eb7b1b3a937..4bb2f4c17321bd55f97050cb59c1690e45f24cf5 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1,6 +1,7 @@ /* * Device Tree Source for the r8a7790 SoC * + * Copyright (C) 2015 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. * @@ -369,13 +370,6 @@ audma1: dma-controller@ec720000 { dma-channels = <13>; }; - audmapp: dma-controller@ec740000 { - compatible = "renesas,rcar-audmapp"; - #dma-cells = <1>; - - reg = <0 0xec740000 0 0x200>; - }; - i2c0: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; @@ -493,17 +487,21 @@ pfc: pfc@e6060000 { sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee100000 0 0x200>; + reg = <0 0xee100000 0 0x328>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; + dmas = <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx"; status = "disabled"; }; sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee120000 0 0x200>; + reg = <0 0xee120000 0 0x328>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; + dmas = <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -512,6 +510,8 @@ sdhi2: sd@ee140000 { reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; + dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -520,6 +520,8 @@ sdhi3: sd@ee160000 { reg = <0 0xee160000 0 0x100>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; + dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -792,6 +794,26 @@ du_out_lvds1: endpoint { }; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7790"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, + <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7790"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, + <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -838,16 +860,34 @@ audio_clk_c: audio_clk_c { clock-output-names = "audio_clk_c"; }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "usb_extal"; + }; + + /* External CAN clock */ + can_clk: can_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "can_clk"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7790-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; + clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", - "z"; + "z", "rcan", "adsp"; }; /* Variable factor clocks */ @@ -1121,18 +1161,21 @@ R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; + clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>, + <&extal_clk>, <&p_clk>; #clock-cells = <1>; clock-indices = < R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 - R8A7790_CLK_THERMAL R8A7790_CLK_PWM + R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL + R8A7790_CLK_PWM >; - clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; + clock-output-names = "audmac0", "audmac1", "adsp_mod", + "thermal", "pwm"; }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, + clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; @@ -1410,7 +1453,10 @@ rcar_sound: rcar_sound@ec500000 { reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x1280>; /* SSI */ + <0 0xec541000 0 0x1280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, @@ -1435,34 +1481,171 @@ rcar_sound: rcar_sound@ec500000 { status = "disabled"; rcar_sound,dvc { - dvc0: dvc@0 { }; - dvc1: dvc@1 { }; + dvc0: dvc@0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc@1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; }; rcar_sound,src { - src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; }; - src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; }; - src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; }; - src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; }; - src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; }; - src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; }; - src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; }; - src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; }; - src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; }; - src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; }; + src0: src@0 { + interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src@1 { + interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src@2 { + interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src@3 { + interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src@4 { + interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src@5 { + interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src@6 { + interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src@7 { + interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src@8 { + interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src@9 { + interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; }; rcar_sound,ssi { - ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; }; - ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; }; - ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; }; - ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; }; - ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; }; - ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; }; - ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; }; - ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; }; - ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; }; - ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; + ssi0: ssi@0 { + interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi@1 { + interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi@2 { + interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi@3 { + interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi@4 { + interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi@5 { + interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi@6 { + interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi@7 { + interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi@8 { + interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi@9 { + interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; }; }; + + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, + <0 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, + <0 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index d2ebf11f98814ab59c7d0a6d8987bd7c21e360a0..e33e4047b0b0c9207494e8cb3e30e4f2ac7bc6ee 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -141,6 +141,11 @@ vin0_pins: vin0 { renesas,groups = "vin0_data8", "vin0_clk"; renesas,function = "vin0"; }; + + can0_pins: can0 { + renesas,groups = "can0_data"; + renesas,function = "can0"; + }; }; &scif0 { @@ -307,3 +312,9 @@ vin0ep: endpoint { }; }; }; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index a3c27807f6c516e8c28b75642cb2df3c1a259e5e..824ddab9c3adcbde11ac8ea62f339af6aa1b3ec6 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -258,6 +258,29 @@ sndcodec: simple-audio-card,codec { system-clock-frequency = <11289600>; }; }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + x13_clk: x13-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; }; &du { @@ -265,7 +288,19 @@ &du { pinctrl-names = "default"; status = "okay"; + clocks = <&mstp7_clks R8A7791_CLK_DU0>, + <&mstp7_clks R8A7791_CLK_DU1>, + <&mstp7_clks R8A7791_CLK_LVDS0>, + <&x13_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "lvds.0", + "dclkin.0", "dclkin.1"; + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; port@1 { lvds_connector: endpoint { }; @@ -284,7 +319,7 @@ i2c2_pins: i2c2 { }; du_pins: du { - renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0"; + renesas,groups = "du_rgb666", "du_sync", "du_disp", "du_clk_out_0"; renesas,function = "du"; }; @@ -506,6 +541,38 @@ adv7180: endpoint { }; }; + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + eeprom@50 { compatible = "renesas,24c02"; reg = <0x50>; @@ -517,9 +584,27 @@ &i2c6 { status = "okay"; clock-frequency = <100000>; + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; + vdd_dvfs: regulator@68 { compatible = "dlg,da9210"; reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index e35812a0d8d40e8c986c58ea71f529b54c1f5cc6..4696062f6ddeaaeb27a4260bd8932238ec461a2a 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for the r8a7791 SoC * - * Copyright (C) 2013-2014 Renesas Electronics Corporation + * Copyright (C) 2013-2015 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. * @@ -357,13 +357,6 @@ audma1: dma-controller@ec720000 { dma-channels = <13>; }; - audmapp: dma-controller@ec740000 { - compatible = "renesas,rcar-audmapp"; - #dma-cells = <1>; - - reg = <0 0xec740000 0 0x200>; - }; - /* The memory map in the User's Manual maps the cores to bus numbers */ i2c0: i2c@e6508000 { #address-cells = <1>; @@ -482,9 +475,11 @@ mmcif0: mmc@ee200000 { sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7791"; - reg = <0 0xee100000 0 0x200>; + reg = <0 0xee100000 0 0x328>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; + dmas = <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -493,6 +488,8 @@ sdhi1: sd@ee140000 { reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; + dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -501,6 +498,8 @@ sdhi2: sd@ee160000 { reg = <0 0xee160000 0 0x100>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; + dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -816,6 +815,26 @@ du_out_lvds0: endpoint { }; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7791"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, + <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7791"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, + <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -862,31 +881,50 @@ pcie_bus_clk: pcie_bus_clk { status = "disabled"; }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "usb_extal"; + }; + + /* External CAN clock */ + can_clk: can_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "can_clk"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; + clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z"; + "lb", "qspi", "sdh", "sd0", "z", + "rcan", "adsp"; }; /* Variable factor clocks */ - sd1_clk: sd2_clk@e6150078 { + sd2_clk: sd2_clk@e6150078 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd1"; + clock-output-names = "sd2"; }; - sd2_clk: sd3_clk@e615026c { + sd3_clk: sd3_clk@e615026c { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; + clock-output-names = "sd3"; }; mmc0_clk: mmc0_clk@e6150240 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; @@ -1107,7 +1145,7 @@ R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, + clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; @@ -1125,18 +1163,21 @@ R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; + clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, + <&extal_clk>, <&p_clk>; #clock-cells = <1>; clock-indices = < R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 - R8A7791_CLK_THERMAL R8A7791_CLK_PWM + R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL + R8A7791_CLK_PWM >; - clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; + clock-output-names = "audmac0", "audmac1", "adsp_mod", + "thermal", "pwm"; }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; @@ -1154,7 +1195,7 @@ R8A7791_CLK_LVDS0 mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, + clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; clock-indices = < @@ -1384,6 +1425,66 @@ pciec: pcie@fe000000 { status = "disabled"; }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, + <0 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, + <0 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, + <0 261 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + rcar_sound: rcar_sound@ec500000 { /* * #sound-dai-cells is required @@ -1395,7 +1496,10 @@ rcar_sound: rcar_sound@ec500000 { reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x1280>; /* SSI */ + <0 0xec541000 0 0x1280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, @@ -1420,34 +1524,120 @@ rcar_sound: rcar_sound@ec500000 { status = "disabled"; rcar_sound,dvc { - dvc0: dvc@0 { }; - dvc1: dvc@1 { }; + dvc0: dvc@0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc@1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; }; rcar_sound,src { - src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; }; - src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; }; - src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; }; - src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; }; - src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; }; - src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; }; - src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; }; - src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; }; - src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; }; - src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; }; + src0: src@0 { + interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src@1 { + interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src@2 { + interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src@3 { + interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src@4 { + interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src@5 { + interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src@6 { + interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src@7 { + interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src@8 { + interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src@9 { + interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; }; rcar_sound,ssi { - ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; }; - ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; }; - ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; }; - ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; }; - ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; }; - ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; }; - ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; }; - ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; }; - ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; }; - ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; + ssi0: ssi@0 { + interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi@1 { + interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi@2 { + interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi@3 { + interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi@4 { + interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi@5 { + interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi@6 { + interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi@7 { + interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi@8 { + interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi@9 { + interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; }; }; }; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 0d848e60507172ef8f0a7872e6b2cde4f61a7fda..928cfa641475e4f96a44232c60aacea9f7744159 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -43,6 +43,19 @@ &cmt0 { status = "okay"; }; +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; + &scif2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 8f78da5ef10b603bc8324b0834e2632fec28e1e7..7a3ffa51a8bf2c8be0a5a1c990867a2a138bb06f 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -107,6 +107,66 @@ irqc0: interrupt-controller@e61c0000 { <0 17 IRQ_TYPE_LEVEL_HIGH>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH + 0 308 IRQ_TYPE_LEVEL_HIGH + 0 309 IRQ_TYPE_LEVEL_HIGH + 0 310 IRQ_TYPE_LEVEL_HIGH + 0 311 IRQ_TYPE_LEVEL_HIGH + 0 312 IRQ_TYPE_LEVEL_HIGH + 0 313 IRQ_TYPE_LEVEL_HIGH + 0 314 IRQ_TYPE_LEVEL_HIGH + 0 315 IRQ_TYPE_LEVEL_HIGH + 0 316 IRQ_TYPE_LEVEL_HIGH + 0 317 IRQ_TYPE_LEVEL_HIGH + 0 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; @@ -269,6 +329,41 @@ hscif2: serial@e62d0000 { status = "disabled"; }; + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7794"; + reg = <0 0xee700000 0 0x400>; + interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7794_CLK_ETHER>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7794"; + reg = <0 0xee100000 0 0x200>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7794"; + reg = <0 0xee140000 0 0x100>; + interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7794"; + reg = <0 0xee160000 0 0x100>; + interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -294,19 +389,19 @@ cpg_clocks: cpg_clocks@e6150000 { "lb", "qspi", "sdh", "sd0", "z"; }; /* Variable factor clocks */ - sd1_clk: sd2_clk@e6150078 { + sd2_clk: sd2_clk@e6150078 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd1"; + clock-output-names = "sd2"; }; - sd2_clk: sd3_clk@e615007c { + sd3_clk: sd3_clk@e615026c { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615007c 0 4>; + reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; + clock-output-names = "sd3"; }; mmc0_clk: mmc0_clk@e6150240 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; @@ -518,7 +613,7 @@ R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>, + clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; clock-indices = < @@ -585,4 +680,54 @@ R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 clock-output-names = "scifa3", "scifa4", "scifa5"; }; }; + + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, + <0 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, + <0 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + }; + + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + }; + + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, + <0 261 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 9a09579b8309c39fbb767c7798adee8f56062cea..bdf85701987d7d355746b26a9b68e323864c4f2b 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -103,6 +103,14 @@ vcc_host: usb-host-regulator { regulator-always-on; regulator-boot-on; }; + + vsys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; }; &emac { @@ -148,6 +156,14 @@ act8846: act8846@5a { pinctrl-names = "default"; pinctrl-0 = <&act8846_dvs0_ctl>; + vp1-supply = <&vsys>; + vp2-supply = <&vsys>; + vp3-supply = <&vsys>; + vp4-supply = <&vsys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vsys>; + inl3-supply = <&vsys>; + regulators { vcc_ddr: REG1 { regulator-name = "VCC_DDR"; diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts index d7b8bbc0c25fa00c8ccf59ee0b1ad03485136622..1687e8336994fc4bb87b5d4edfd7d66250be9626 100644 --- a/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts @@ -33,6 +33,7 @@ vdd_cpu: syr827@40 { regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; + vin-supply = <&vcc_sys>; }; vdd_gpu: syr828@41 { @@ -43,6 +44,7 @@ vdd_gpu: syr828@41 { regulator-min-microvolt = <850000>; regulator-max-microvolt = <1350000>; regulator-always-on; + vin-supply = <&vcc_sys>; }; hym8563@51 { @@ -64,6 +66,14 @@ act8846: act8846@5a { reg = <0x5a>; status = "okay"; + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + regulators { vcc_ddr: REG1 { regulator-name = "VCC_DDR"; diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index a1c294bf7fed0e51a29bd9205a408819d7aeadeb..f62ea78754a956d2f562a8900e3bfcf3cdba4871 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -43,9 +43,16 @@ rk808: pmic@1b { #clock-cells = <1>; clock-output-names = "xin32k", "rk808-clkout2"; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; vcc8-supply = <&vcc_18>; vcc9-supply = <&vcc_io>; vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; vcc12-supply = <&vcc_io>; vddio-supply = <&vccio_pmu>; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 5e895a514a0b82afef27ae7c7e849ed1ab8d226f..4a457518d8616044b26fbfa34bea17ebbd421f84 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -103,6 +103,15 @@ vcc_phy: vcc-phy-regulator { regulator-always-on; regulator-boot-on; }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; }; &emmc { @@ -238,6 +247,10 @@ eth_phy_pwr: eth-phy-pwr { }; }; +&usbphy { + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index e6f873abbe0dd991fcdcf5a81dbe33c09aec1e1d..b54dd78580c1c77a01035b62d8181d0cd995b18f 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -179,6 +179,22 @@ &emmc { status = "okay"; }; +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; @@ -459,6 +475,10 @@ &uart3 { status = "okay"; }; +&usbphy { + status = "okay"; +}; + &usb_host1 { pinctrl-names = "default"; pinctrl-0 = <&usbhub_rst>; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts new file mode 100644 index 0000000000000000000000000000000000000000..d081f0e0da36c3c42fd97626a79d5e4df54bc300 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -0,0 +1,447 @@ +/* + * Copyright (c) 2014, 2015 Andy Yan + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk3288.dtsi" + +/ { + model = "PopMetal-RK3288"; + compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; + + memory{ + reg = <0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio4 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lan: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_lan"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + ldo5: LDO_REG5 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ldo5"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_codec: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_wl: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_wl"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + ak8963: ak8963@0d { + compatible = "asahi-kasei,ak8975"; + reg = <0x0d>; + interrupt-parent = <&gpio8>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&comp_int>; + }; + + l3g4200d: l3g4200d@68 { + compatible = "st,l3g4200d-gyro"; + st,drdy-int-pin = <2>; + reg = <0x6b>; + }; + + mma8452: mma8452@1d { + compatible = "fsl,mma8452"; + reg = <0x1d>; + interrupt-parent = <&gpio8>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + ak8963 { + comp_int: comp-int { + rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + mma8452 { + gsensor_int: gsensor-int { + rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = ; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index eccc78d3220ba2e59e2994dfb4f5f20d3d3f7a91..165968d51d8fd7370ca596833c0e2126fc616970 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -420,6 +420,8 @@ usb_host0_ehci: usb@ff500000 { interrupts = ; clocks = <&cru HCLK_USBHOST0>; clock-names = "usbhost"; + phys = <&usbphy1>; + phy-names = "usb"; status = "disabled"; }; @@ -432,6 +434,8 @@ usb_host1: usb@ff540000 { interrupts = ; clocks = <&cru HCLK_USBHOST1>; clock-names = "otg"; + phys = <&usbphy2>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -442,6 +446,8 @@ usb_otg: usb@ff580000 { interrupts = ; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -698,6 +704,35 @@ gic: interrupt-controller@ffc01000 { interrupts = ; }; + usbphy: phy { + compatible = "rockchip,rk3288-usb-phy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy0 { + #phy-cells = <0>; + reg = <0x320>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + }; + + usbphy1: usb-phy1 { + #phy-cells = <0>; + reg = <0x334>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + }; + + usbphy2: usb-phy2 { + #phy-cells = <0>; + reg = <0x348>; + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + }; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3288-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 367af53c1b8437d30059b32abff7dd3ed7a0c992..57ab8587f7b977d4274dfdf2380d9f363f5a06ff 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -26,6 +26,7 @@ aliases { serial2 = &usart1; serial3 = &usart2; serial4 = &usart3; + serial5 = &uart0; gpio0 = &pioA; gpio1 = &pioB; gpio2 = &pioC; @@ -206,6 +207,17 @@ usart1: serial@f0020000 { status = "disabled"; }; + uart0: serial@f0024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0024000 0x100>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + pwm0: pwm@f002c000 { compatible = "atmel,sama5d3-pwm"; reg = <0xf002c000 0x300>; @@ -439,7 +451,7 @@ ramc0: ramc@ffffea00 { }; dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-usart"; + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, @@ -764,6 +776,22 @@ AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts wit }; }; + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; /* conflicts with ISI_PCK */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; /* conflicts with TWCK0, ISI_HSYNC */ + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = @@ -1098,6 +1126,12 @@ usart3_clk: usart3_clk { atmel,clk-output-range = <0 66000000>; }; + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <16>; + atmel,clk-output-range = <0 66000000>; + }; + twi0_clk: twi0_clk { reg = <18>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts index 9089c7c6cea863e547a26d7c8d2233c138827334..d9a9aca1ccfdf6d5514b535241d7c5f2ae379e92 100644 --- a/arch/arm/boot/dts/sama5d35ek.dts +++ b/arch/arm/boot/dts/sama5d35ek.dts @@ -44,8 +44,6 @@ macb1: ethernet@f802c000 { gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pb_user1 { label = "pb_user1"; diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index eaf41451ad0cf5afec07ab94a03ae9e9a4bdee42..c5a3772741bf610b300a10147e76bcc882b973fb 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with * CAN support * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi index b4544cf11bad1b08e5825dcf6690bb57acc558db..7cb235ef0fb6dba30e77d6c91a0b9eafda6359a3 100644 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with * Ethernet. * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi index de5ed59fb446d5c7cefc8ddc02d2bbe24032b9bc..23f225fbb7563e3efb4c896464b27bd3b8bf11de 100644 --- a/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with * Gigabit Ethernet. * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 85d30270156561c3e8b44cc189482ec469c6e1af..be7cfefc6c312351a138244dbe0db7a3cc195ee0 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with * LCD support * * Copyright (C) 2013 Boris BREZILLON @@ -13,40 +13,183 @@ / { ahb { apb { + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + pinctrl@fffff200 { lcd { - pinctrl_lcd: lcd-0 { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt { + atmel,pins = + ; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ + }; + + pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt { atmel,pins = - ; /* PE28 periph C LCDD23 pin */ + ; /* LCDD23 pin */ }; }; }; diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi index 1b02208ea6ff2b70aab43ddd416b37ef0b9a2a1f..026b252f09b3e6b2db4b6310fe19969f3332798e 100644 --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with * 3 MMC ports * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 02848453ca0cf5447de27aaca6b233611173da4e..f7fa58fe09f1553eff94f61b2d3f38113ad95c7b 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with * 2 TC blocks. * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index 7a8d4c6115f72fdab533980a0f0d96eb6cb1469a..2511d748867bdd17fc3e08140b69ba5f61b594d7 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with * UART support * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 4303874889c69954fa894ff458bb9bfb492f33d4..6b1bb58f9c0b609fdb3622a02c89d2d394750c81 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -64,9 +64,13 @@ aliases { gpio2 = &pioC; gpio3 = &pioD; gpio4 = &pioE; + pwm0 = &pwm0; + ssc0 = &ssc0; + ssc1 = &ssc1; tcb0 = &tcb0; tcb1 = &tcb1; i2c0 = &i2c0; + i2c1 = &i2c1; i2c2 = &i2c2; }; cpus { @@ -310,6 +314,34 @@ apb { #size-cells = <1>; ranges; + hlcdc: hlcdc@f0000000 { + compatible = "atmel,sama5d4-hlcdc"; + reg = <0xf0000000 0x4000>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + dma1: dma-controller@f0004000 { compatible = "atmel,sama5d4-dma"; reg = <0xf0004000 0x200>; @@ -319,6 +351,21 @@ dma1: dma-controller@f0004000 { clock-names = "dma_clk"; }; + isi: isi@f0008000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf0008000 0x4000>; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + ramc0: ramc@f0010000 { compatible = "atmel,sama5d3-ddramc"; reg = <0xf0010000 0x200>; @@ -800,6 +847,33 @@ mmc0: mmc@f8000000 { clock-names = "mci_clk"; }; + ssc0: ssc@f8008000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf8008000 0x4000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(26))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(27))>; + dma-names = "tx", "rx"; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + pwm0: pwm@f800c000 { + compatible = "atmel,sama5d3-pwm"; + reg = <0xf800c000 0x300>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + status = "disabled"; + }; + spi0: spi@f8010000 { #address-cells = <1>; #size-cells = <0>; @@ -839,6 +913,25 @@ i2c0: i2c@f8014000 { status = "disabled"; }; + i2c1: i2c@f8018000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8018000 0x4000>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(4)>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(5)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + tcb0: timer@f801c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf801c000 0x100>; @@ -853,6 +946,8 @@ macb0: ethernet@f8020000 { interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_rmii>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&macb0_clk>, <&macb0_clk>; clock-names = "hclk", "pclk"; status = "disabled"; @@ -953,6 +1048,24 @@ usart4: serial@fc010000 { status = "disabled"; }; + ssc1: ssc@fc014000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xfc014000 0x4000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(28))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(29))>; + dma-names = "tx", "rx"; + clocks = <&ssc1_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + tcb1: timer@fc020000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xfc020000 0x100>; @@ -1008,6 +1121,46 @@ trigger@3 { }; }; + aes@fc044000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xfc044000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(41)>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(40)>; + dma-names = "tx", "rx"; + clocks = <&aes_clk>; + clock-names = "aes_clk"; + status = "disabled"; + }; + + tdes@fc04c000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xfc04c000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(42)>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(43)>; + dma-names = "tx", "rx"; + clocks = <&tdes_clk>; + clock-names = "tdes_clk"; + status = "disabled"; + }; + + sha@fc050000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xfc050000 0x100>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(44)>; + dma-names = "tx"; + clocks = <&sha_clk>; + clock-names = "sha_clk"; + status = "disabled"; + }; + rstc@fc068600 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; @@ -1064,7 +1217,7 @@ rtc@fc0686b0 { }; dbgu: serial@fc069000 { - compatible = "atmel,at91sam9260-usart"; + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfc069000 0x200>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; @@ -1190,6 +1343,14 @@ pinctrl_i2c0: i2c0-0 { }; }; + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; /* TWCK1, conflicts with UART0 TX and DIBN */ + }; + }; + i2c2 { pinctrl_i2c2: i2c2-0 { atmel,pins = @@ -1198,6 +1359,155 @@ pinctrl_i2c2: i2c2-0 { }; }; + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* ISI_HSYNC */ + }; + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ + }; + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ + }; + }; + + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD23 pin */ + }; + pinctrl_lcd_rgb777: lcd-rgb-3 { + atmel,pins = + /* LCDDAT0 conflicts with TMS */ + ; /* LCDD23 pin */ + }; + pinctrl_lcd_rgb888: lcd-rgb-4 { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + macb0 { pinctrl_macb0_rmii: macb0_rmii-0 { atmel,pins = @@ -1281,6 +1591,38 @@ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */ }; }; + ssc0 { + pinctrl_ssc0_tx: ssc0_tx { + atmel,pins = + ; /* TD0 */ + }; + + pinctrl_ssc0_rx: ssc0_rx { + atmel,pins = + ; /* RD0 */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx { + atmel,pins = + ; /* TD1 */ + }; + + pinctrl_ssc1_rx: ssc1_rx { + atmel,pins = + ; /* RD1 */ + }; + }; + usart2 { pinctrl_usart2: usart2-0 { atmel,pins = diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts deleted file mode 100644 index a759a276c9a972d4174e519240e4f9ed7d720fd0..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/sh7372-mackerel.dts +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Device Tree Source for the mackerel board - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "sh7372.dtsi" - -/ { - model = "Mackerel (AP4 EVM 2nd)"; - compatible = "renesas,mackerel"; - - chosen { - bootargs = "console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp mem=240m rw"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x10000000>; - }; -}; diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi deleted file mode 100644 index f863a10cb1b2d4b7050a942af90478d432b85ecd..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/sh7372.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Device Tree Source for the sh7372 SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "renesas,sh7372"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0x0>; - clock-frequency = <800000000>; - }; - }; - - pfc: pfc@e6050000 { - compatible = "renesas,pfc-sh7372"; - reg = <0xe6050000 0x8000>, - <0xe605801c 0x1c>; - gpio-controller; - #gpio-cells = <2>; - }; -}; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts deleted file mode 100644 index 6d32c87632d42fda072304bdc7fd366491dcbda9..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Device Tree Source for the KZM-A9-GT board - * - * Copyright (C) 2012 Horms Solutions Ltd. - * - * Based on sh73a0-kzm9g.dts - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "sh73a0.dtsi" -#include -#include -#include - -/ { - model = "KZM-A9-GT"; - compatible = "renesas,kzm9g-reference", "renesas,sh73a0"; - - aliases { - serial4 = &scifa4; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd_dvfs>; - operating-points = < - /* kHz uV */ - 1196000 1315000 - 598000 1175000 - 398667 1065000 - >; - voltage-tolerance = <1>; /* 1% */ - }; - }; - - chosen { - bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw"; - stdout-path = &scifa4; - }; - - memory { - device_type = "memory"; - reg = <0x41000000 0x1e800000>; - }; - - reg_1p8v: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc_sdhi0: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vmmc_sdhi2: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lan9220@10000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x10000000 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqpin0>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg-io-width = <4>; - smsc,irq-push-pull; - smsc,save-mac-address; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 20 GPIO_ACTIVE_LOW>; - label = "LED1"; - }; - led2 { - gpios = <&pfc 21 GPIO_ACTIVE_LOW>; - label = "LED2"; - }; - led3 { - gpios = <&pfc 22 GPIO_ACTIVE_LOW>; - label = "LED3"; - }; - led4 { - gpios = <&pfc 23 GPIO_ACTIVE_LOW>; - label = "LED4"; - }; - }; - - keyboard { - compatible = "gpio-keys"; - - back-key { - gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW3"; - }; - - right-key { - gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-R"; - }; - - left-key { - gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-L"; - }; - - enter-key { - gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-P"; - }; - - up-key { - gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-U"; - }; - - down-key { - gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-D"; - }; - - home-key { - gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW1"; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "left_j"; - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - }; - simple-audio-card,codec { - sound-dai = <&ak4648>; - bitclock-master; - frame-master; - system-clock-frequency = <11289600>; - }; - }; -}; - -&cmt1 { - status = "okay"; -}; - -&extal2_clk { - clock-frequency = <48000000>; -}; - -&i2c0 { - status = "okay"; - as3711@40 { - compatible = "ams,as3711"; - reg = <0x40>; - - regulators { - vdd_dvfs: sd1 { - regulator-name = "1.315V CPU"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - sd2 { - regulator-name = "1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - sd4 { - regulator-name = "1.215V"; - regulator-min-microvolt = <1215000>; - regulator-max-microvolt = <1235000>; - regulator-always-on; - regulator-boot-on; - }; - ldo2 { - regulator-name = "2.8V CPU"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo3 { - regulator-name = "3.0V CPU"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - ldo4 { - regulator-name = "2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo5 { - regulator-name = "2.8V #2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo7 { - regulator-name = "1.15V CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - ldo8 { - regulator-name = "1.15V CPU #2"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - ak4648: ak4648@12 { - #sound-dai-cells = <0>; - compatible = "asahi-kasei,ak4648"; - reg = <0x12>; - }; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - status = "okay"; - - pcf8575: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&irqpin2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&mmcif { - pinctrl-0 = <&mmcif_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - vmmc-supply = <®_1p8v>; - status = "okay"; -}; - -&pfc { - i2c3_pins: i2c3 { - renesas,groups = "i2c3_1"; - renesas,function = "i2c3"; - }; - - mmcif_pins: mmc { - mux { - renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; - renesas,function = "mmc0"; - }; - cfg { - renesas,groups = "mmc0_data8_0"; - renesas,pins = "PORT279"; - bias-pull-up; - }; - }; - - scifa4_pins: serial4 { - renesas,groups = "scifa4_data", "scifa4_ctrl"; - renesas,function = "scifa4"; - }; - - sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; - renesas,function = "sdhi0"; - }; - - sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; - }; - - fsia_pins: sounda { - renesas,groups = "fsia_mclk_in", "fsia_sclk_in", - "fsia_data_in", "fsia_data_out"; - renesas,function = "fsia"; - }; -}; - -&scifa4 { - pinctrl-0 = <&scifa4_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vmmc_sdhi0>; - bus-width = <4>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vmmc_sdhi2>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&sh_fsi2 { - pinctrl-0 = <&fsia_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index 27c5f426d172f03d53801875ec5a5293c4f45b88..022ba505f57339a959d8208732eeb75e585911d4 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -1,6 +1,9 @@ /* * Device Tree Source for the KZM-A9-GT board * + * Copyright (C) 2012 Horms Solutions Ltd. + * + * Based on sh73a0-kzm9g.dts * Copyright (C) 2012 Renesas Solutions Corp. * * This file is licensed under the terms of the GNU General Public License @@ -10,17 +13,388 @@ /dts-v1/; #include "sh73a0.dtsi" +#include +#include +#include / { model = "KZM-A9-GT"; compatible = "renesas,kzm9g", "renesas,sh73a0"; + aliases { + serial4 = &scifa4; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd_dvfs>; + operating-points = < + /* kHz uV */ + 1196000 1315000 + 598000 1175000 + 398667 1065000 + >; + voltage-tolerance = <1>; /* 1% */ + }; + }; + chosen { - bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw"; + bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw"; + stdout-path = &scifa4; }; memory { device_type = "memory"; - reg = <0x41000000 0x1e800000>; + reg = <0x40000000 0x20000000>; + }; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc_sdhi0: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vmmc_sdhi2: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + led1 { + gpios = <&pfc 20 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + led2 { + gpios = <&pfc 21 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + led3 { + gpios = <&pfc 22 GPIO_ACTIVE_LOW>; + label = "LED3"; + }; + led4 { + gpios = <&pfc 23 GPIO_ACTIVE_LOW>; + label = "LED4"; + }; + }; + + keyboard { + compatible = "gpio-keys"; + + back-key { + gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW3"; + }; + + right-key { + gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-R"; + }; + + left-key { + gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-L"; + }; + + enter-key { + gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-P"; + }; + + up-key { + gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-U"; + }; + + down-key { + gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-D"; + }; + + home-key { + gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW1"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "left_j"; + simple-audio-card,cpu { + sound-dai = <&sh_fsi2 0>; + }; + simple-audio-card,codec { + sound-dai = <&ak4648>; + bitclock-master; + frame-master; + system-clock-frequency = <11289600>; + }; + }; +}; + +&bsc { + ethernet@10000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x10000000 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqpin0>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + reg-io-width = <4>; + smsc,irq-push-pull; + smsc,save-mac-address; + vddvario-supply = <®_1p8v>; + vdd33a-supply = <®_3p3v>; + }; +}; + +&cmt1 { + status = "okay"; +}; + +&extal2_clk { + clock-frequency = <48000000>; +}; + +&i2c0 { + status = "okay"; + + compass@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + interrupt-parent = <&irqpin3>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; + + ak4648: codec@12 { + compatible = "asahi-kasei,ak4648"; + reg = <0x12>; + #sound-dai-cells = <0>; + }; + + accelerometer@1d { + compatible = "adi,adxl34x"; + reg = <0x1d>; + interrupt-parent = <&irqpin3>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>; }; + + rtc@32 { + compatible = "ricoh,r2025sd"; + reg = <0x32>; + }; + + as3711@40 { + compatible = "ams,as3711"; + reg = <0x40>; + + regulators { + vdd_dvfs: sd1 { + regulator-name = "1.315V CPU"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + sd2 { + regulator-name = "1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + sd4 { + regulator-name = "1.215V"; + regulator-min-microvolt = <1215000>; + regulator-max-microvolt = <1235000>; + regulator-always-on; + regulator-boot-on; + }; + ldo2 { + regulator-name = "2.8V CPU"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo3 { + regulator-name = "3.0V CPU"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + ldo4 { + regulator-name = "2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo5 { + regulator-name = "2.8V #2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo7 { + regulator-name = "1.15V CPU"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + ldo8 { + regulator-name = "1.15V CPU #2"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + touchscreen@55 { + compatible = "sitronix,st1232"; + reg = <0x55>; + interrupt-parent = <&irqpin1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; + + pcf8575: gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&irqpin2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&mmcif { + pinctrl-0 = <&mmcif_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + vmmc-supply = <®_1p8v>; + status = "okay"; +}; + +&pfc { + i2c3_pins: i2c3 { + renesas,groups = "i2c3_1"; + renesas,function = "i2c3"; + }; + + mmcif_pins: mmc { + mux { + renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; + renesas,function = "mmc0"; + }; + cfg { + renesas,groups = "mmc0_data8_0"; + renesas,pins = "PORT279"; + bias-pull-up; + }; + }; + + scifa4_pins: serial4 { + renesas,groups = "scifa4_data", "scifa4_ctrl"; + renesas,function = "scifa4"; + }; + + sdhi0_pins: sd0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; + renesas,function = "sdhi0"; + }; + + sdhi2_pins: sd2 { + renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; + renesas,function = "sdhi2"; + }; + + fsia_pins: sounda { + renesas,groups = "fsia_mclk_in", "fsia_sclk_in", + "fsia_data_in", "fsia_data_out"; + renesas,function = "fsia"; + }; +}; + +&scifa4 { + pinctrl-0 = <&scifa4_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vmmc_sdhi0>; + bus-width = <4>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vmmc_sdhi2>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +&sh_fsi2 { + pinctrl-0 = <&fsia_pins>; + pinctrl-names = "default"; + + status = "okay"; }; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 2dfd5b44255de147e11f2c36c2b9cc5f7e9f3793..45b539ce4d3520356d45470f3bdfeb5f8020ce30 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -11,6 +11,7 @@ /include/ "skeleton.dtsi" #include +#include #include / { @@ -26,15 +27,24 @@ cpu@0 { compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <1196000000>; + power-domains = <&pd_a2sl>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1196000000>; + power-domains = <&pd_a2sl>; }; }; + timer@f0000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf0000600 0x20>; + interrupts = ; + clocks = <&twd_clk>; + }; + gic: interrupt-controller@f0001000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -49,6 +59,7 @@ sbsc2: memory-controller@fb400000 { interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>, <0 38 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sec", "temp"; + power-domains = <&pd_a4bc1>; }; sbsc1: memory-controller@fe400000 { @@ -57,6 +68,7 @@ sbsc1: memory-controller@fe400000 { interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, <0 36 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sec", "temp"; + power-domains = <&pd_a4bc0>; }; pmu { @@ -69,11 +81,12 @@ cmt1: timer@e6138000 { compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; reg = <0xe6138000 0x200>; interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks SH73A0_CLK_CMT1>; + clock-names = "fck"; + power-domains = <&pd_c5>; renesas,channels-mask = <0x3f>; - clocks = <&mstp3_clks SH73A0_CLK_CMT1>; - clock-names = "fck"; status = "disabled"; }; @@ -94,6 +107,9 @@ irqpin0: irqpin@e6900000 { 0 6 IRQ_TYPE_LEVEL_HIGH 0 7 IRQ_TYPE_LEVEL_HIGH 0 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; + control-parent; }; irqpin1: irqpin@e6900004 { @@ -113,6 +129,8 @@ irqpin1: irqpin@e6900004 { 0 14 IRQ_TYPE_LEVEL_HIGH 0 15 IRQ_TYPE_LEVEL_HIGH 0 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; control-parent; }; @@ -133,6 +151,9 @@ irqpin2: irqpin@e6900008 { 0 22 IRQ_TYPE_LEVEL_HIGH 0 23 IRQ_TYPE_LEVEL_HIGH 0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; + control-parent; }; irqpin3: irqpin@e690000c { @@ -152,6 +173,9 @@ irqpin3: irqpin@e690000c { 0 30 IRQ_TYPE_LEVEL_HIGH 0 31 IRQ_TYPE_LEVEL_HIGH 0 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; + control-parent; }; i2c0: i2c@e6820000 { @@ -164,6 +188,7 @@ i2c0: i2c@e6820000 { 0 169 IRQ_TYPE_LEVEL_HIGH 0 170 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks SH73A0_CLK_IIC0>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -177,6 +202,7 @@ i2c1: i2c@e6822000 { 0 53 IRQ_TYPE_LEVEL_HIGH 0 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_IIC1>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -190,6 +216,7 @@ i2c2: i2c@e6824000 { 0 173 IRQ_TYPE_LEVEL_HIGH 0 174 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks SH73A0_CLK_IIC2>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -203,6 +230,7 @@ i2c3: i2c@e6826000 { 0 185 IRQ_TYPE_LEVEL_HIGH 0 186 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks SH73A0_CLK_IIC3>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -216,6 +244,7 @@ i2c4: i2c@e6828000 { 0 189 IRQ_TYPE_LEVEL_HIGH 0 190 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks SH73A0_CLK_IIC4>; + power-domains = <&pd_c5>; status = "disabled"; }; @@ -225,6 +254,7 @@ mmcif: mmc@e6bd0000 { interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 0 141 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; + power-domains = <&pd_a3sp>; reg-io-width = <4>; status = "disabled"; }; @@ -236,6 +266,7 @@ sdhi0: sd@ee100000 { 0 84 IRQ_TYPE_LEVEL_HIGH 0 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; + power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; @@ -247,6 +278,7 @@ sdhi1: sd@ee120000 { interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 0 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; + power-domains = <&pd_a3sp>; toshiba,mmc-wrprotect-disable; cap-sd-highspeed; status = "disabled"; @@ -258,6 +290,7 @@ sdhi2: sd@ee140000 { interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; + power-domains = <&pd_a3sp>; toshiba,mmc-wrprotect-disable; cap-sd-highspeed; status = "disabled"; @@ -269,6 +302,7 @@ scifa0: serial@e6c40000 { interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -278,6 +312,7 @@ scifa1: serial@e6c50000 { interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -287,6 +322,7 @@ scifa2: serial@e6c60000 { interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -296,6 +332,7 @@ scifa3: serial@e6c70000 { interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -305,6 +342,7 @@ scifa4: serial@e6c80000 { interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -314,6 +352,7 @@ scifa5: serial@e6cb0000 { interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -323,6 +362,7 @@ scifa6: serial@e6cc0000 { interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -332,6 +372,7 @@ scifa7: serial@e6cd0000 { interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -341,6 +382,7 @@ scifb8: serial@e6c30000 { interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -359,6 +401,117 @@ pfc: pfc@e6050000 { <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; + power-domains = <&pd_c5>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile"; + reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; + + pm-domains { + pd_c5: c5 { + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_c4: c4@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_d4: d4@1 { + reg = <1>; + #power-domain-cells = <0>; + }; + + pd_a4bc0: a4bc0@4 { + reg = <4>; + #power-domain-cells = <0>; + }; + + pd_a4bc1: a4bc1@5 { + reg = <5>; + #power-domain-cells = <0>; + }; + + pd_a4lc0: a4lc0@6 { + reg = <6>; + #power-domain-cells = <0>; + }; + + pd_a4lc1: a4lc1@7 { + reg = <7>; + #power-domain-cells = <0>; + }; + + pd_a4mp: a4mp@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3mp: a3mp@9 { + reg = <9>; + #power-domain-cells = <0>; + }; + + pd_a3vc: a3vc@10 { + reg = <10>; + #power-domain-cells = <0>; + }; + }; + + pd_a4rm: a4rm@12 { + reg = <12>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3r: a3r@13 { + reg = <13>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2rv: a2rv@14 { + reg = <14>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + }; + }; + }; + + pd_a4s: a4s@16 { + reg = <16>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3sp: a3sp@17 { + reg = <17>; + #power-domain-cells = <0>; + }; + + pd_a3sg: a3sg@18 { + reg = <18>; + #power-domain-cells = <0>; + }; + + pd_a3sm: a3sm@19 { + reg = <19>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2sl: a2sl@20 { + reg = <20>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; }; sh_fsi2: sound@ec230000 { @@ -366,9 +519,22 @@ sh_fsi2: sound@ec230000 { compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; reg = <0xec230000 0x400>; interrupts = <0 146 0x4>; + power-domains = <&pd_a4mp>; status = "disabled"; }; + bsc: bus@fec10000 { + compatible = "renesas,bsc-sh73a0", "renesas,bsc", + "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20000000>; + reg = <0xfec10000 0x400>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&zb_clk>; + power-domains = <&pd_a4s>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -426,133 +592,159 @@ cpg_clocks: cpg_clocks@e6150000 { vclk1_clk: vclk1_clk@e6150008 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150008 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, + <0>; #clock-cells = <0>; clock-output-names = "vclk1"; }; vclk2_clk: vclk2_clk@e615000c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615000c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, + <0>; #clock-cells = <0>; clock-output-names = "vclk2"; }; vclk3_clk: vclk3_clk@e615001c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615001c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, + <0>; #clock-cells = <0>; clock-output-names = "vclk3"; }; zb_clk: zb_clk@e6150010 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150010 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "zb"; }; flctl_clk: flctl_clk@e6150014 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150014 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "flctlck"; }; sdhi0_clk: sdhi0_clk@e6150074 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150074 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>, <0>; #clock-cells = <0>; clock-output-names = "sdhi0ck"; }; sdhi1_clk: sdhi1_clk@e6150078 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150078 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>, <0>; #clock-cells = <0>; clock-output-names = "sdhi1ck"; }; sdhi2_clk: sdhi2_clk@e615007c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615007c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>, <0>; #clock-cells = <0>; clock-output-names = "sdhi2ck"; }; fsia_clk: fsia_clk@e6150018 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150018 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&fsiack_clk>, <&fsiack_clk>; #clock-cells = <0>; clock-output-names = "fsia"; }; fsib_clk: fsib_clk@e6150090 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150090 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&fsibck_clk>, <&fsibck_clk>; #clock-cells = <0>; clock-output-names = "fsib"; }; sub_clk: sub_clk@e6150080 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150080 4>; - clocks = <&extal2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "sub"; }; spua_clk: spua_clk@e6150084 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150084 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "spua"; }; spuv_clk: spuv_clk@e6150094 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150094 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "spuv"; }; msu_clk: msu_clk@e6150088 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150088 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "msu"; }; hsi_clk: hsi_clk@e615008c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615008c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div7_clk>, <0>; #clock-cells = <0>; clock-output-names = "hsi"; }; mfg1_clk: mfg1_clk@e6150098 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150098 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "mfg1"; }; mfg2_clk: mfg2_clk@e615009c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "mfg2"; }; dsit_clk: dsit_clk@e6150060 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150060 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "dsit"; }; dsi0p_clk: dsi0p_clk@e6150064 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150064 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, + <&extcki_clk>, <0>, <0>, <0>; #clock-cells = <0>; clock-output-names = "dsi0pck"; }; @@ -695,5 +887,16 @@ SH73A0_CLK_KEYSC clock-output-names = "iic3", "iic4", "keysc"; }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150144 4>, <0xe615003c 4>; + clocks = <&cpg_clocks SH73A0_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + SH73A0_CLK_INTCA0 + >; + clock-output-names = + "intca0"; + }; }; }; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index bfd3f1c734b8d84dec4a622032e1b29efa07b83d..2201cd5da3bb95843278b27c8f855d540d154041 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -1017,23 +1017,6 @@ cpufreq-cooling { status = "disabled"; }; - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - enable-active-high; - - states = <1800000 0x1 - 2900000 0x0>; - - status = "disabled"; - }; - mcde@a0350000 { compatible = "stericsson,mcde"; reg = <0xa0350000 0x1000>, /* MCDE */ diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index bf8f0eddc2c020d03dda99adfdc32d453e254c14..744c1e3a744df1530ba53cd2a56029a9e9ac5d37 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -111,6 +111,21 @@ i2c@80110000 { pinctrl-1 = <&i2c3_sleep_mode>; }; + vmmci: regulator-gpio { + compatible = "regulator-gpio"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-name = "mmci-reg"; + regulator-type = "voltage"; + + startup-delay-us = <100>; + enable-active-high; + + states = <1800000 0x1 + 2900000 0x0>; + }; + // External Micro SD slot sdi0_per1@80126000 { arm,primecell-periphid = <0x10480180>; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 206826a855c0dc0e5025539e5a8930405c8cdd56..1bc84ebdccaa2fe119ebb9e542f88b64f017cea9 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -146,8 +146,21 @@ ethernet@0 { }; vmmci: regulator-gpio { + compatible = "regulator-gpio"; + gpios = <&gpio7 4 0x4>; enable-gpio = <&gpio6 25 0x4>; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-name = "mmci-reg"; + regulator-type = "voltage"; + + startup-delay-us = <100>; + enable-active-high; + + states = <1800000 0x1 + 2900000 0x0>; }; // External Micro SD slot diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..2c5cede686dc57d883542f1ab44a1f95b6cc834c --- /dev/null +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -0,0 +1,2421 @@ +/ { + clock@0,60006000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + timing-924000000 { + clock-frequency = <924000000>; + nvidia,parent-clock-frequency = <924000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + emc@0,7001b000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000060 + 0x00000000 + 0x00000018 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000005 + 0x00000005 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000064 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000007 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x800001c5 + 0x0000000a + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x0000009a + 0x00000000 + 0x00000026 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000006 + 0x00000006 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x000000a0 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x0000000b + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000023a + 0x0000000a + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 + 0x0000000a + 0x00000000 + 0x00000001 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000134 + 0x00000000 + 0x0000004d + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000008 + 0x0000000f + 0x0000000c + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000013f + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000015 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000370 + 0x0000000a + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 + 0x00000011 + 0x00000000 + 0x00000002 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 + 0x00000000 + 0x00000080 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000001 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000213 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000022 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000050e + 0x0000000a + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000304 + 0x00000000 + 0x000000c1 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000018 + 0x0000000f + 0x0000001c + 0x0000001c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000031c + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000033 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000713 + 0x0000000a + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008cd>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 + 0x00000035 + 0x00000000 + 0x00000006 + 0x00000002 + 0x00000005 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000004 + 0x00000006 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 + 0x00000000 + 0x00000181 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000006 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00008000 + 0x00000000 + 0x00000000 + 0x00008000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000707 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000066 + 0x00000000 + 0x00000100 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000d2b3 + 0x80000d22 + 0x0000000a + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0173000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d + 0x0000004d + 0x00000000 + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 + 0x00000003 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000007 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x0000000e + 0x00000010 + 0x00000012 + 0x000008e4 + 0x00000000 + 0x00000239 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x0000004b + 0x0000000e + 0x00000052 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000008 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000924 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00050000 + 0x00050000 + 0x00050000 + 0x00050000 + 0x00005000 + 0x00005000 + 0x00005000 + 0x00005000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000096 + 0x00000000 + 0x00000100 + 0x0173000e + 0x00000000 + 0x00000003 + 0x000052a3 + 0x800012d7 + 0x00000009 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000011 + 0x00000066 + 0x00000000 + 0x0000000c + 0x00000004 + 0x00000004 + 0x00000008 + 0x00000002 + 0x0000000a + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000008 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x00000063 + 0x0000000f + 0x0000006c + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x0000000b + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000c11 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00003800 + 0x00003800 + 0x00003800 + 0x00003800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x000000c6 + 0x00000000 + 0x00000100 + 0x015b000e + 0x00000000 + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x0139000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 + 0x00000088 + 0x00000000 + 0x00000010 + 0x00000006 + 0x00000006 + 0x00000009 + 0x00000002 + 0x0000000d + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000009 + 0x00030000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000010 + 0x00000012 + 0x00000014 + 0x00000fd6 + 0x00000000 + 0x000003f5 + 0x00000002 + 0x0000000b + 0x00000001 + 0x00000000 + 0x00000085 + 0x00000012 + 0x00000090 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001017 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe01200b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00054000 + 0x00054000 + 0x00000000 + 0x00054000 + 0x00054000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0139000e + 0x00000000 + 0x00000003 + 0x000042a0 + 0x80002062 + 0x0000000a + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0127000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001b + 0x0000009b + 0x00000000 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b + 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000000a + 0x00000002 + 0x00000000 + 0x00000003 + 0x0000000b + 0x00070000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000002 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 + 0x00000000 + 0x00000482 + 0x00000002 + 0x0000000d + 0x00000001 + 0x00000000 + 0x00000097 + 0x00000015 + 0x000000a3 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000013 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001248 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0127000e + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024aa + 0x0000000e + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f7000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 + 0x000000cd + 0x00000000 + 0x00000019 + 0x0000000a + 0x00000008 + 0x0000000d + 0x00000004 + 0x00000013 + 0x0000000a + 0x0000000a + 0x00000004 + 0x00000002 + 0x00000000 + 0x00000006 + 0x00000006 + 0x0000000b + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000d + 0x00080000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 + 0x00000003 + 0x00000011 + 0x00000001 + 0x00000000 + 0x000000c7 + 0x00000018 + 0x000000d7 + 0x00000200 + 0x00000005 + 0x00000006 + 0x00000005 + 0x00000019 + 0x00000000 + 0x00000008 + 0x00000008 + 0x00001822 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00700b1 + 0x00008000 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00514514 + 0x00514514 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x00f7000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emc-auto-cal-config = <0xa1430303>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200020>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000f15>; + nvidia,emc-mrs-wait-cnt = <0x00cd000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000002b + 0x000000f0 + 0x00000000 + 0x0000001e + 0x0000000b + 0x00000009 + 0x0000000f + 0x00000005 + 0x00000016 + 0x0000000b + 0x0000000b + 0x00000004 + 0x00000002 + 0x00000000 + 0x00000007 + 0x00000007 + 0x0000000d + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000f + 0x000a0000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000016 + 0x0000001a + 0x0000001c + 0x00001be7 + 0x00000000 + 0x000006f9 + 0x00000004 + 0x00000015 + 0x00000001 + 0x00000000 + 0x000000e7 + 0x0000001b + 0x000000fb + 0x00000200 + 0x00000006 + 0x00000007 + 0x00000006 + 0x0000001e + 0x00000000 + 0x0000000a + 0x0000000a + 0x00001c28 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab898 + 0xe00400b1 + 0x00008000 + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x5d75d720 + 0x00514514 + 0x00514514 + 0x5d75d700 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000128 + 0x00cd000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x800037ea + 0x00000011 + >; + }; + + }; + }; + + memory-controller@0,70019000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0503 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000004 + 0x00000002 + 0x00000003 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0504 + 0x73840a05 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000006 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000007 + 0x00000008 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090c + 0x7428180d + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000a + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000d + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00170e13 + 0x736c2414 + 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d + 0x80000040 + 0x00000005 + 0x00000006 + 0x00000016 + 0x0000000e + 0x0000000f + 0x00000002 + 0x00000004 + 0x0000000e + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000009 + 0x09060202 + 0x001a1016 + 0x734e2a17 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index dbfaba09703a62f0b88aa043286d14f9b2a8e883..ed8a8acd3d34b44d9e63afedf6f6a88e541e96d5 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -3,6 +3,8 @@ #include #include "tegra124.dtsi" +#include "tegra124-jetson-tk1-emc.dtsi" + / { model = "NVIDIA Tegra124 Jetson TK1"; compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; @@ -60,35 +62,35 @@ clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,function = "soc"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; uart3_cts_n_pa1 { nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap2_fs_pa2 { nvidia,pins = "dap2_fs_pa2"; nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; dap2_sclk_pa3 { nvidia,pins = "dap2_sclk_pa3"; nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; dap2_din_pa4 { nvidia,pins = "dap2_din_pa4"; nvidia,function = "i2s1"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; dap2_dout_pa5 { @@ -96,14 +98,14 @@ dap2_dout_pa5 { nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; sdmmc3_cmd_pa7 { nvidia,pins = "sdmmc3_cmd_pa7"; @@ -116,14 +118,14 @@ pb0 { nvidia,pins = "pb0"; nvidia,function = "uartd"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pb1 { nvidia,pins = "pb1"; nvidia,function = "uartd"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; sdmmc3_dat3_pb4 { @@ -156,9 +158,9 @@ sdmmc3_dat0_pb7 { }; uart3_rts_n_pc0 { nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; uart2_txd_pc2 { @@ -172,7 +174,7 @@ uart2_rxd_pc3 { nvidia,pins = "uart2_rxd_pc3"; nvidia,function = "irda"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; gen1_i2c_scl_pc4 { @@ -194,44 +196,39 @@ gen1_i2c_sda_pc5 { pc7 { nvidia,pins = "pc7"; nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pg0 { nvidia,pins = "pg0"; - nvidia,function = "rsvd1"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pg1 { nvidia,pins = "pg1"; - nvidia,function = "rsvd1"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pg2 { nvidia,pins = "pg2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pg3 { nvidia,pins = "pg3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pg4 { nvidia,pins = "pg4"; - nvidia,function = "spi4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pg5 { nvidia,pins = "pg5"; @@ -251,7 +248,7 @@ pg7 { nvidia,pins = "pg7"; nvidia,function = "spi4"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ph0 { @@ -270,7 +267,6 @@ ph1 { }; ph2 { nvidia,pins = "ph2"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -278,57 +274,53 @@ ph2 { ph3 { nvidia,pins = "ph3"; nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ph4 { nvidia,pins = "ph4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ph5 { nvidia,pins = "ph5"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ph6 { nvidia,pins = "ph6"; nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ph7 { nvidia,pins = "ph7"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; pi0 { nvidia,pins = "pi0"; - nvidia,function = "rsvd1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pi1 { nvidia,pins = "pi1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; pi2 { nvidia,pins = "pi2"; nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pi3 { @@ -341,22 +333,21 @@ pi3 { pi4 { nvidia,pins = "pi4"; nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pi5 { nvidia,pins = "pi5"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pi6 { nvidia,pins = "pi6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pi7 { @@ -368,23 +359,22 @@ pi7 { }; pj0 { nvidia,pins = "pj0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pj2 { nvidia,pins = "pj2"; nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; uart2_cts_n_pj5 { nvidia,pins = "uart2_cts_n_pj5"; nvidia,function = "uartb"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; uart2_rts_n_pj6 { @@ -403,35 +393,32 @@ pj7 { }; pk0 { nvidia,pins = "pk0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pk1 { nvidia,pins = "pk1"; - nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pk2 { nvidia,pins = "pk2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pk3 { nvidia,pins = "pk3"; nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pk4 { nvidia,pins = "pk4"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -439,13 +426,12 @@ pk4 { spdif_out_pk5 { nvidia,pins = "spdif_out_pk5"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; spdif_in_pk6 { nvidia,pins = "spdif_in_pk6"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -459,17 +445,17 @@ pk7 { }; dap1_fs_pn0 { nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; + nvidia,function = "rsvd4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap1_din_pn1 { nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; + nvidia,function = "rsvd4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap1_dout_pn2 { nvidia,pins = "dap1_dout_pn2"; @@ -480,108 +466,104 @@ dap1_dout_pn2 { }; dap1_sclk_pn3 { nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; + nvidia,function = "rsvd4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; usb_vbus_en0_pn4 { nvidia,pins = "usb_vbus_en0_pn4"; nvidia,function = "usb"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; usb_vbus_en1_pn5 { nvidia,pins = "usb_vbus_en1_pn5"; nvidia,function = "usb"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; hdmi_int_pn7 { nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; nvidia,rcv-sel = ; }; ulpi_data7_po0 { nvidia,pins = "ulpi_data7_po0"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_data0_po1 { nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ulpi_data1_po2 { nvidia,pins = "ulpi_data1_po2"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_data2_po3 { nvidia,pins = "ulpi_data2_po3"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_data3_po4 { nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ulpi_data4_po5 { nvidia,pins = "ulpi_data4_po5"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_data5_po6 { nvidia,pins = "ulpi_data5_po6"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ulpi_data6_po7 { nvidia,pins = "ulpi_data6_po7"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap3_fs_pp0 { nvidia,pins = "dap3_fs_pp0"; nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; dap3_din_pp1 { nvidia,pins = "dap3_din_pp1"; nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; dap3_dout_pp2 { nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -595,91 +577,87 @@ dap3_sclk_pp3 { }; dap4_fs_pp4 { nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; + nvidia,function = "rsvd4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap4_din_pp5 { nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; + nvidia,function = "rsvd3"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap4_dout_pp6 { nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; + nvidia,function = "rsvd4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap4_sclk_pp7 { nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; + nvidia,function = "rsvd3"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col0_pq0 { nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd2"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_col1_pq1 { nvidia,pins = "kb_col1_pq1"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col2_pq2 { nvidia,pins = "kb_col2_pq2"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col3_pq3 { nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; kb_col4_pq4 { nvidia,pins = "kb_col4_pq4"; nvidia,function = "sdmmc3"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_col5_pq5 { nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_col6_pq6 { nvidia,pins = "kb_col6_pq6"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col7_pq7 { nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_row0_pr0 { nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -687,121 +665,115 @@ kb_row0_pr0 { kb_row1_pr1 { nvidia,pins = "kb_row1_pr1"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row2_pr2 { nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; kb_row3_pr3 { nvidia,pins = "kb_row3_pr3"; - nvidia,function = "sys"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row4_pr4 { nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row5_pr5 { nvidia,pins = "kb_row5_pr5"; nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row6_pr6 { nvidia,pins = "kb_row6_pr6"; nvidia,function = "displaya_alt"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row7_pr7 { nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row8_ps0 { nvidia,pins = "kb_row8_ps0"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_row9_ps1 { nvidia,pins = "kb_row9_ps1"; - nvidia,function = "rsvd2"; + nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; kb_row10_ps2 { nvidia,pins = "kb_row10_ps2"; - nvidia,function = "rsvd2"; + nvidia,function = "uarta"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row11_ps3 { nvidia,pins = "kb_row11_ps3"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row12_ps4 { nvidia,pins = "kb_row12_ps4"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row13_ps5 { nvidia,pins = "kb_row13_ps5"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_row14_ps6 { nvidia,pins = "kb_row14_ps6"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row15_ps7 { nvidia,pins = "kb_row15_ps7"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row16_pt0 { nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; kb_row17_pt1 { nvidia,pins = "kb_row17_pt1"; - nvidia,function = "rsvd2"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gen2_i2c_scl_pt5 { nvidia,pins = "gen2_i2c_scl_pt5"; @@ -828,72 +800,63 @@ sdmmc4_cmd_pt7 { }; pu0 { nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; pu1 { nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pu2 { nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pu3 { nvidia,pins = "pu3"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; pu4 { nvidia,pins = "pu4"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; pu5 { nvidia,pins = "pu5"; - nvidia,function = "gmi"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pu6 { nvidia,pins = "pu6"; - nvidia,function = "rsvd3"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pv0 { nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pv1 { nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; sdmmc3_cd_n_pv2 { nvidia,pins = "sdmmc3_cd_n_pv2"; nvidia,function = "sdmmc3"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; sdmmc1_wp_n_pv3 { @@ -922,16 +885,16 @@ ddc_sda_pv5 { gpio_w2_aud_pw2 { nvidia,pins = "gpio_w2_aud_pw2"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_w3_aud_pw3 { nvidia,pins = "gpio_w3_aud_pw3"; nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap_mclk1_pw4 { nvidia,pins = "dap_mclk1_pw4"; @@ -949,17 +912,17 @@ clk2_out_pw5 { }; uart3_txd_pw6 { nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; uart3_rxd_pw7 { nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dvfs_pwm_px0 { nvidia,pins = "dvfs_pwm_px0"; @@ -970,10 +933,9 @@ dvfs_pwm_px0 { }; gpio_x1_aud_px1 { nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dvfs_clk_px2 { nvidia,pins = "dvfs_clk_px2"; @@ -985,34 +947,32 @@ dvfs_clk_px2 { gpio_x3_aud_px3 { nvidia,pins = "gpio_x3_aud_px3"; nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x4_aud_px4 { nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "gmi"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x5_aud_px5 { nvidia,pins = "gpio_x5_aud_px5"; nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x6_aud_px6 { nvidia,pins = "gpio_x6_aud_px6"; nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x7_aud_px7 { nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1027,8 +987,8 @@ ulpi_clk_py0 { ulpi_dir_py1 { nvidia,pins = "ulpi_dir_py1"; nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ulpi_nxt_py2 { @@ -1048,44 +1008,44 @@ ulpi_stp_py3 { sdmmc1_dat3_py4 { nvidia,pins = "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_dat2_py5 { nvidia,pins = "sdmmc1_dat2_py5"; nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_dat1_py6 { nvidia,pins = "sdmmc1_dat1_py6"; nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_dat0_py7 { nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_cmd_pz1 { nvidia,pins = "sdmmc1_cmd_pz1"; nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pwr_i2c_scl_pz6 { nvidia,pins = "pwr_i2c_scl_pz6"; @@ -1184,7 +1144,6 @@ cam_i2c_sda_pbb2 { }; pbb3 { nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1198,21 +1157,18 @@ pbb4 { }; pbb5 { nvidia,pins = "pbb5"; - nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pbb6 { nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pbb7 { nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1226,15 +1182,13 @@ cam_mclk_pcc0 { }; pcc1 { nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pcc2 { nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; @@ -1248,8 +1202,8 @@ sdmmc4_clk_pcc4 { clk2_req_pcc5 { nvidia,pins = "clk2_req_pcc5"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pex_l0_rst_n_pdd1 { @@ -1262,15 +1216,15 @@ pex_l0_rst_n_pdd1 { pex_l0_clkreq_n_pdd2 { nvidia,pins = "pex_l0_clkreq_n_pdd2"; nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pex_wake_n_pdd3 { nvidia,pins = "pex_wake_n_pdd3"; nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pex_l1_rst_n_pdd5 { @@ -1283,8 +1237,8 @@ pex_l1_rst_n_pdd5 { pex_l1_clkreq_n_pdd6 { nvidia,pins = "pex_l1_clkreq_n_pdd6"; nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; clk3_out_pee0 { @@ -1297,13 +1251,12 @@ clk3_out_pee0 { clk3_req_pee1 { nvidia,pins = "clk3_req_pee1"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; dap_mclk1_req_pee2 { nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "sata"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1314,7 +1267,7 @@ hdmi_cec_pee3 { nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; sdmmc3_clk_lb_out_pee4 { nvidia,pins = "sdmmc3_clk_lb_out_pee4"; @@ -1333,24 +1286,24 @@ sdmmc3_clk_lb_in_pee5 { dp_hpd_pff0 { nvidia,pins = "dp_hpd_pff0"; nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; usb_vbus_en2_pff1 { nvidia,pins = "usb_vbus_en2_pff1"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; }; pff2 { nvidia,pins = "pff2"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; nvidia,open-drain = ; }; core_pwr_req { @@ -1362,7 +1315,7 @@ core_pwr_req { }; cpu_pwr_req { nvidia,pins = "cpu_pwr_req"; - nvidia,function = "rsvd2"; + nvidia,function = "cpu"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1371,7 +1324,7 @@ pwr_int_n { nvidia,pins = "pwr_int_n"; nvidia,function = "pmi"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; reset_out_n { @@ -1379,7 +1332,7 @@ reset_out_n { nvidia,function = "reset_out_n"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; owr { nvidia,pins = "owr"; @@ -1391,9 +1344,9 @@ owr { }; clk_32k_in { nvidia,pins = "clk_32k_in"; - nvidia,function = "rsvd2"; + nvidia,function = "clk"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; jtag_rtck { diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..1a5748d05dda1a97c1cace1d679ad5e1c13d589e --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -0,0 +1,2023 @@ +/ { + clock@0,60006000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + /* TODO: Add 528MHz frequency */ + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + emc@0,7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000060 + 0x00000000 + 0x00000018 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000005 + 0x00000005 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000064 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000007 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x800001c5 + 0x0000000a + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x0000009a + 0x00000000 + 0x00000026 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000006 + 0x00000006 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x000000a0 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x0000000b + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000023a + 0x0000000a + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 + 0x0000000a + 0x00000000 + 0x00000001 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000134 + 0x00000000 + 0x0000004d + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000008 + 0x0000000f + 0x0000000c + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000013f + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000015 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000370 + 0x0000000a + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 + 0x00000011 + 0x00000000 + 0x00000002 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 + 0x00000000 + 0x00000080 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000001 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000213 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000022 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000050e + 0x0000000a + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000304 + 0x00000000 + 0x000000c1 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000018 + 0x0000000f + 0x0000001c + 0x0000001c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000031c + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000033 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000713 + 0x0000000a + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 + 0x00000035 + 0x00000000 + 0x00000007 + 0x00000002 + 0x00000005 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000004 + 0x00000006 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 + 0x00000000 + 0x00000181 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000007 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00094000 + 0x00094000 + 0x00009400 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000066 + 0x00000000 + 0x00000100 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000d2b3 + 0x80000d22 + 0x0000000a + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d + 0x0000004c + 0x00000000 + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 + 0x00000003 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000007 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x0000000e + 0x00000010 + 0x00000012 + 0x000008e4 + 0x00000000 + 0x00000239 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x0000004a + 0x0000000e + 0x00000051 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000009 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000924 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000101 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000096 + 0x00000000 + 0x00000100 + 0x0174000c + 0x00000000 + 0x00000003 + 0x000052a3 + 0x800012d7 + 0x00000009 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 + 0x00000065 + 0x00000000 + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000008 + 0x00000002 + 0x0000000a + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000008 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x00000063 + 0x0000000f + 0x0000006b + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x0000000d + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000c11 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00048000 + 0x00048000 + 0x00004800 + 0x00004800 + 0x00004800 + 0x00004800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000101 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x000000c6 + 0x00000000 + 0x00000100 + 0x015b000c + 0x00000000 + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c + 0x0000009a + 0x00000000 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b + 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000000a + 0x00000002 + 0x00000000 + 0x00000003 + 0x0000000b + 0x00070000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000002 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 + 0x00000000 + 0x00000482 + 0x00000002 + 0x0000000d + 0x00000001 + 0x00000000 + 0x00000096 + 0x00000015 + 0x000000a2 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000015 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001249 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000005 + 0x00000006 + 0x00000003 + 0x00000006 + 0x00000005 + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000005 + 0x00000006 + 0x00000003 + 0x00000006 + 0x00000005 + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000101 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0128000c + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024aa + 0x0000000e + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 + 0x000000cc + 0x00000000 + 0x0000001a + 0x00000009 + 0x00000008 + 0x0000000d + 0x00000004 + 0x00000013 + 0x00000009 + 0x00000009 + 0x00000003 + 0x00000002 + 0x00000000 + 0x00000006 + 0x00000006 + 0x0000000b + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000d + 0x00080000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 + 0x00000003 + 0x00000011 + 0x00000001 + 0x00000000 + 0x000000c6 + 0x00000018 + 0x000000d6 + 0x00000200 + 0x00000005 + 0x00000006 + 0x00000005 + 0x0000001d + 0x00000000 + 0x00000008 + 0x00000008 + 0x00001822 + 0x00000000 + 0x80000005 + 0x00000000 + 0x104ab198 + 0xe00700b1 + 0x00008000 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000008 + 0x00000008 + 0x00000005 + 0x00000009 + 0x00000009 + 0x00000007 + 0x00000009 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000005 + 0x00000009 + 0x00000009 + 0x00000007 + 0x00000009 + 0x00000008 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000101 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00514514 + 0x00514514 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x00f8000c + 0x00000007 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f + >; + }; + + }; + }; + + memory-controller@0,70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0403 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000005 + 0x00000002 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0405 + 0x73840a06 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000005 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000007 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000b + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000f + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00160d13 + 0x734c2414 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 004e8e4e1c04f08a9b23a10c22c864c8e1011cf2..2d21253ea4e3c059665d693f8ae2ffa648cd32bf 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -1,46 +1,29 @@ /dts-v1/; -#include -#include "tegra124.dtsi" +#include "tegra124-nyan.dtsi" + +#include "tegra124-nyan-big-emc.dtsi" / { model = "Acer Chromebook 13 CB5-311"; compatible = "google,nyan-big", "nvidia,tegra124"; - aliases { - rtc0 = "/i2c@0,7000d000/pmic@40"; - rtc1 = "/rtc@0,7000e000"; - serial0 = &uarta; - }; + panel: panel { + compatible = "auo,b133xtn01"; - memory { - reg = <0x0 0x80000000 0x0 0x80000000>; + backlight = <&backlight>; + ddc-i2c-bus = <&dpaux>; }; - host1x@0,50000000 { - hdmi@0,54280000 { - status = "okay"; - - vdd-supply = <&vdd_3v3_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - hdmi-supply = <&vdd_5v0_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - sor@0,54540000 { - status = "okay"; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; + sdhci@0,700b0400 { /* SD Card on this bus */ + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + }; - dpaux@0,545c0000 { - vdd-supply = <&vdd_3v3_panel>; - status = "okay"; - }; + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBig"; }; pinmux@0,70000868 { @@ -48,1092 +31,1308 @@ pinmux@0,70000868 { pinctrl-0 = <&pinmux_default>; pinmux_default: common { - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,enable-input = ; + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; nvidia,pull = ; nvidia,tristate = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,enable-input = ; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,enable-input = ; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,enable-input = ; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; }; - pg4 { - nvidia,pins = "pg4", - "pg5", - "pg6", - "pi3"; - nvidia,function = "spi4"; - nvidia,enable-input = ; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,enable-input = ; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - pk0 { - nvidia,pins = "pk0", - "kb_row15_ps7", - "clk_32k_out_pa0"; - nvidia,function = "soc"; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; + pb0 { + nvidia,pins = "pb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; + pb1 { + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; nvidia,function = "sdmmc3"; - nvidia,enable-input = ; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "kb_col4_pq4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5", - "sdmmc3_cd_n_pv2"; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; nvidia,function = "sdmmc3"; - nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = ; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,enable-input = ; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,enable-input = ; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; }; gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5", - "gen1_i2c_scl_pc4"; + nvidia,pins = "gen1_i2c_sda_pc5"; nvidia,function = "i2c1"; - nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; - nvidia,lock = ; + nvidia,enable-input = ; nvidia,open-drain = ; }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = ; + pc7 { + nvidia,pins = "pc7"; nvidia,pull = ; nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; nvidia,enable-input = ; - nvidia,pull = ; + }; + pg0 { + nvidia,pins = "pg0"; + nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; + pg1 { + nvidia,pins = "pg1"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; + }; + pg2 { + nvidia,pins = "pg2"; nvidia,pull = ; nvidia,tristate = ; - nvidia,lock = ; - nvidia,rcv-sel = ; + nvidia,enable-input = ; }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; + pg3 { + nvidia,pins = "pg3"; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; + pg4 { + nvidia,pins = "pg4"; + nvidia,function = "spi4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,enable-input = ; + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; nvidia,pull = ; nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; + nvidia,enable-input = ; }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - nvidia,drive-type = <1>; - }; - codec_irq_l { - nvidia,pins = "ph4"; - nvidia,function = "gmi"; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - lcd_bl_en { - nvidia,pins = "ph2"; + ph0 { + nvidia,pins = "ph0"; nvidia,function = "gmi"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; - touch_irq_l { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; - tpm_davint_l { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; + ph2 { + nvidia,pins = "ph2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ts_irq_l { - nvidia,pins = "pk2"; + ph3 { + nvidia,pins = "ph3"; nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { + nvidia,pins = "ph4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ts_reset_l { - nvidia,pins = "pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; + ph5 { + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; - ts_shdn_l { - nvidia,pins = "pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; + ph6 { + nvidia,pins = "ph6"; + nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; ph7 { nvidia,pins = "ph7"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; - kb_col0_ap { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; + pi0 { + nvidia,pins = "pi0"; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - lid_open { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; + pi1 { + nvidia,pins = "pi1"; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - en_vdd_sd { - nvidia,pins = "kb_row0_pr0"; + pi2 { + nvidia,pins = "pi2"; nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; - ac_ok { - nvidia,pins = "pj0"; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { + nvidia,pins = "pi4"; nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi5 { + nvidia,pins = "pi5"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; - sensor_irq_l { + pi6 { nvidia,pins = "pi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { + nvidia,pins = "pi7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj0 { + nvidia,pins = "pj0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj7 { + nvidia,pins = "pj7"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - wifi_en { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd4"; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { + nvidia,pins = "pk1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - en_vdd_bl { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; + pk2 { + nvidia,pins = "pk2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "gmi"; nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - en_vdd_hdmi { + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - soc_warm_reset_l { - nvidia,pins = "pi5"; - nvidia,function = "gmi"; - nvidia,pull = ; + pk7 { + nvidia,pins = "pk7"; + nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; - hp_det_l { - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; + nvidia,open-drain = ; }; - mic_det_l { - nvidia,pins = "kb_row7_pr7"; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - }; - }; - - serial@0,70006000 { - /* Debug connector on the bottom of the board near SD card. */ - status = "okay"; - }; - - pwm@0,7000a000 { - status = "okay"; - }; - - i2c@0,7000c000 { - status = "okay"; - clock-frequency = <100000>; - - acodec: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - }; - - i2c@0,7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@0,7000c500 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - }; - - hdmi_ddc: i2c@0,7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@0,7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1 { - pins = "gpio1"; - function = "gpio"; - bias-pull-up; - }; - - gpio2_4_7 { - pins = "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_6 { - pins = "gpio3", "gpio6"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - bias-pull-down; - }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.00V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - vdd_run_cam: ldo4 { - regulator-name = "+3.3V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+2.8V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - }; - }; - - spi@0,7000d400 { - status = "okay"; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <3000000>; - interrupt-parent = <&gpio>; - interrupts = ; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = ; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - }; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - power-supplies = <&charger>; - }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row16_pt0 { + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row17_pt1 { + nvidia,pins = "kb_row17_pt1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cd_n_pv2 { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_req_pee2 { + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_clk_lb_out_pee4 { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_lb_in_pee5 { + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en2_pff1 { + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; }; }; - - spi@0,7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@0 { - compatible = "winbond,w25q32dw"; - reg = <0>; - }; - }; - - pmc@0,7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - hda@0,70030000 { - status = "okay"; - }; - - sdhci@0,700b0000 { /* WiFi/BT on this bus */ - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - no-1-8-v; - non-removable; - }; - - sdhci@0,700b0400 { /* SD Card on this bus */ - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - bus-width = <4>; - no-1-8-v; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - sdhci@0,700b0600 { /* eMMC on this bus */ - status = "okay"; - bus-width = <8>; - no-1-8-v; - non-removable; - }; - - ahub@0,70300000 { - i2s@0,70301100 { - status = "okay"; - }; - }; - - usb@0,7d000000 { /* Rear external USB port. */ - status = "okay"; - }; - - usb-phy@0,7d000000 { - status = "okay"; - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb@0,7d004000 { /* Internal webcam. */ - status = "okay"; - }; - - usb-phy@0,7d004000 { - status = "okay"; - vbus-supply = <&vdd_run_cam>; - }; - - usb@0,7d008000 { /* Left external USB port. */ - status = "okay"; - }; - - usb-phy@0,7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - default-brightness-level = <224>; - brightness-levels = - < 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - 256>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; - linux,input-type = <5>; - linux,code = ; - debounce-interval = <1>; - gpio-key,wakeup; - }; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <30>; - gpio-key,wakeup; - }; - }; - - panel: panel { - compatible = "auo,b133xtn01"; - - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - vdd_5v0_ts: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_panel: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-big", - "nvidia,tegra-audio-max98090"; - nvidia,model = "Acer Chromebook 13"; - - nvidia,audio-routing = - "Headphones", "HPR", - "Headphones", "HPL", - "Speakers", "SPKR", - "Speakers", "SPKL", - "Mic Jack", "MICBIAS", - "DMICL", "Int Mic", - "DMICR", "Int Mic", - "IN34", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&acodec>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; - nvidia,mic-det-gpios = - <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - }; }; - -#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..9ecd108f56cf3b348bda5688aefa7232efe982d7 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -0,0 +1,2049 @@ +/ { + clock@0,60006000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + /* TODO: Add 528MHz frequency */ + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + emc@0,7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000060 + 0x00000000 + 0x00000018 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000005 + 0x00000005 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000064 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000007 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x800001c5 + 0x0000000a + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x0000009a + 0x00000000 + 0x00000026 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000006 + 0x00000006 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x000000a0 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x0000000b + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000023a + 0x0000000a + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 + 0x0000000a + 0x00000000 + 0x00000001 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000134 + 0x00000000 + 0x0000004d + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000008 + 0x0000000f + 0x0000000c + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000013f + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000015 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000370 + 0x0000000a + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 + 0x00000011 + 0x00000000 + 0x00000002 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 + 0x00000000 + 0x00000080 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000001 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000213 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000022 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000050e + 0x0000000a + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000304 + 0x00000000 + 0x000000c1 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000018 + 0x0000000f + 0x0000001c + 0x0000001c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000031c + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000033 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000713 + 0x0000000a + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 + 0x00000035 + 0x00000000 + 0x00000007 + 0x00000002 + 0x00000005 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000004 + 0x00000006 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 + 0x00000000 + 0x00000181 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000007 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000066 + 0x00000000 + 0x00000100 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000d2b3 + 0x80000d22 + 0x0000000a + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d + 0x0000004c + 0x00000000 + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 + 0x00000003 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000007 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x0000000e + 0x00000010 + 0x00000012 + 0x000008e4 + 0x00000000 + 0x00000239 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x0000004a + 0x0000000e + 0x00000051 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000009 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000924 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000096 + 0x00000000 + 0x00000100 + 0x0174000c + 0x00000000 + 0x00000003 + 0x000052a3 + 0x800012d7 + 0x00000009 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 + 0x00000065 + 0x00000000 + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000008 + 0x00000002 + 0x0000000a + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000008 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x00000063 + 0x0000000f + 0x0000006b + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x0000000d + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000c11 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00068000 + 0x00068000 + 0x00000000 + 0x00068000 + 0x00068000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00058000 + 0x00058000 + 0x00058000 + 0x00058000 + 0x00005800 + 0x00005800 + 0x00005800 + 0x00005800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x000000c6 + 0x00000000 + 0x00000100 + 0x015b000c + 0x00000000 + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c + 0x0000009a + 0x00000000 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b + 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000000a + 0x00000002 + 0x00000000 + 0x00000003 + 0x0000000b + 0x00070000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000002 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 + 0x00000000 + 0x00000482 + 0x00000002 + 0x0000000d + 0x00000001 + 0x00000000 + 0x00000096 + 0x00000015 + 0x000000a2 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000015 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001248 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00040000 + 0x00040000 + 0x00000000 + 0x00040000 + 0x00040000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x00000004 + 0x00000001 + 0x00000005 + 0x00000007 + 0x00000004 + 0x00000006 + 0x00000007 + 0x00000004 + 0x00000004 + 0x00000001 + 0x00000005 + 0x00000007 + 0x00000004 + 0x00000006 + 0x00000007 + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0128000c + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024a9 + 0x0000000e + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 + 0x000000cc + 0x00000000 + 0x0000001a + 0x00000009 + 0x00000008 + 0x0000000d + 0x00000004 + 0x00000013 + 0x00000009 + 0x00000009 + 0x00000003 + 0x00000002 + 0x00000000 + 0x00000006 + 0x00000006 + 0x0000000b + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000d + 0x00080000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 + 0x00000003 + 0x00000011 + 0x00000001 + 0x00000000 + 0x000000c6 + 0x00000018 + 0x000000d6 + 0x00000200 + 0x00000005 + 0x00000006 + 0x00000005 + 0x0000001d + 0x00000000 + 0x00000008 + 0x00000008 + 0x00001822 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00700b1 + 0x00008000 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000008 + 0x00000008 + 0x00000005 + 0x00000008 + 0x0000000a + 0x00000008 + 0x0000000a + 0x0000000a + 0x00000008 + 0x00000008 + 0x00000005 + 0x00000008 + 0x0000000a + 0x00000008 + 0x0000000a + 0x0000000a + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00492492 + 0x00492492 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x00f8000c + 0x00000000 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f + >; + }; + + }; + }; + + memory-controller@0,70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0403 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000005 + 0x00000002 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0405 + 0x73840a06 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000005 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000007 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000d + 0x00000008 + 0x0000000a + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090d + 0x7428180e + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000b + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000f + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00160d13 + 0x734c2414 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts new file mode 100644 index 0000000000000000000000000000000000000000..0d30c514ffad57300cb54b9652e78caa76c39530 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -0,0 +1,1334 @@ +/dts-v1/; + +#include "tegra124-nyan.dtsi" + +#include "tegra124-nyan-blaze-emc.dtsi" + +/ { + model = "HP Chromebook 14"; + compatible = "google,nyan-blaze", "google,nyan", "nvidia,tegra124"; + + panel: panel { + compatible = "samsung,ltn140at29-301"; + + backlight = <&backlight>; + ddc-i2c-bus = <&dpaux>; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-blaze", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBlaze"; + }; + + pinmux@0,70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: common { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb0 { + nvidia,pins = "pb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb1 { + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pc7 { + nvidia,pins = "pc7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg0 { + nvidia,pins = "pg0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg1 { + nvidia,pins = "pg1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg2 { + nvidia,pins = "pg2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg3 { + nvidia,pins = "pg3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg4 { + nvidia,pins = "pg4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { + nvidia,pins = "ph4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph5 { + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph6 { + nvidia,pins = "ph6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi0 { + nvidia,pins = "pi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi1 { + nvidia,pins = "pi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi2 { + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi5 { + nvidia,pins = "pi5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi6 { + nvidia,pins = "pi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { + nvidia,pins = "pi7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj0 { + nvidia,pins = "pj0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj7 { + nvidia,pins = "pj7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk2 { + nvidia,pins = "pk2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { + nvidia,pins = "pk7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row16_pt0 { + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row17_pt1 { + nvidia,pins = "kb_row17_pt1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cd_n_pv2 { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_req_pee2 { + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_clk_lb_out_pee4 { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_lb_in_pee5 { + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en2_pff1 { + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..a9aec23e06f2c60a3a1d0bc6cc2846a8380fb548 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -0,0 +1,695 @@ +#include +#include "tegra124.dtsi" + +/ { + aliases { + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; + serial0 = &uarta; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + host1x@0,50000000 { + hdmi@0,54280000 { + status = "okay"; + + vdd-supply = <&vdd_3v3_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + hdmi-supply = <&vdd_5v0_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + sor@0,54540000 { + status = "okay"; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux@0,545c0000 { + vdd-supply = <&vdd_3v3_panel>; + status = "okay"; + }; + }; + + serial@0,70006000 { + /* Debug connector on the bottom of the board near SD card. */ + status = "okay"; + }; + + pwm@0,7000a000 { + status = "okay"; + }; + + i2c@0,7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + i2c@0,7000c400 { + status = "okay"; + clock-frequency = <100000>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio>; + interrupts = ; + wakeup-source; + }; + }; + + i2c@0,7000c500 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + }; + + hdmi_ddc: i2c@0,7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1 { + pins = "gpio1"; + function = "gpio"; + bias-pull-up; + }; + + gpio2_4_7 { + pins = "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + bias-pull-down; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.00V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + vdd_run_cam: ldo4 { + regulator-name = "+3.3V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+2.8V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + spi@0,7000d400 { + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <3000000>; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = ; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&charger>; + }; + }; + }; + }; + + spi@0,7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw"; + spi-max-frequency = <25000000>; + reg = <0>; + }; + }; + + pmc@0,7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + hda@0,70030000 { + status = "okay"; + }; + + sdhci0_pwrseq: sdhci0_pwrseq { + compatible = "mmc-pwrseq-simple"; + + reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + }; + + sdhci@0,700b0000 { /* WiFi/BT on this bus */ + status = "okay"; + bus-width = <4>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&sdhci0_pwrseq>; + vmmc-supply = <&vdd_3v3_lp0>; + vqmmc-supply = <&vddio_1v8>; + keep-power-in-suspend; + }; + + sdhci@0,700b0400 { /* SD Card on this bus */ + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-1-8-v; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + sdhci@0,700b0600 { /* eMMC on this bus */ + status = "okay"; + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + ahub@0,70300000 { + i2s@0,70301100 { + status = "okay"; + }; + }; + + usb@0,7d000000 { /* Rear external USB port. */ + status = "okay"; + }; + + usb-phy@0,7d000000 { + status = "okay"; + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb@0,7d004000 { /* Internal webcam. */ + status = "okay"; + }; + + usb-phy@0,7d004000 { + status = "okay"; + vbus-supply = <&vdd_run_cam>; + }; + + usb@0,7d008000 { /* Left external USB port. */ + status = "okay"; + }; + + usb-phy@0,7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; + pwms = <&pwm 1 1000000>; + + default-brightness-level = <224>; + brightness-levels = + < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + 256>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = ; + debounce-interval = <1>; + gpio-key,wakeup; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <30>; + gpio-key,wakeup; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + + vdd_5v0_ts: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + }; + + sound { + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "DMICL", "Int Mic", + "DMICR", "Int Mic", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; + nvidia,mic-det-gpios = + <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index db85695aa7aa715713e0fa387e92de887565e233..13cc7ca5e031e5f1814697e8ead9546079f6d04e 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -220,6 +220,7 @@ tegra_car: clock@0,60006000 { reg = <0x0 0x60006000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + nvidia,external-memory-controller = <&emc>; }; flow-controller@0,60007000 { @@ -227,6 +228,17 @@ flow-controller@0,60007000 { reg = <0x0 0x60007000 0x0 0x1000>; }; + actmon@0,6000c800 { + compatible = "nvidia,tegra124-actmon"; + reg = <0x0 0x6000c800 0x0 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_ACTMON>, + <&tegra_car TEGRA124_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car 119>; + reset-names = "actmon"; + }; + gpio: gpio@0,6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; @@ -582,6 +594,13 @@ mc: memory-controller@0,70019000 { #iommu-cells = <1>; }; + emc: emc@0,7001b000 { + compatible = "nvidia,tegra124-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>; + + nvidia,memory-controller = <&mc>; + }; + sata@0,70020000 { compatible = "nvidia,tegra124-ahci"; @@ -807,7 +826,7 @@ phy1: usb-phy@0,7d000000 { <&tegra_car TEGRA124_CLK_PLL_U>, <&tegra_car TEGRA124_CLK_USBD>; clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; + resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; @@ -819,6 +838,7 @@ phy1: usb-phy@0,7d000000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,has-utmi-pad-registers; status = "disabled"; }; @@ -843,7 +863,7 @@ phy2: usb-phy@0,7d004000 { <&tegra_car TEGRA124_CLK_PLL_U>, <&tegra_car TEGRA124_CLK_USBD>; clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; + resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; @@ -855,7 +875,6 @@ phy2: usb-phy@0,7d004000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; status = "disabled"; }; @@ -880,7 +899,7 @@ phy3: usb-phy@0,7d008000 { <&tegra_car TEGRA124_CLK_PLL_U>, <&tegra_car TEGRA124_CLK_USBD>; clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; + resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 6b157eeabcc5c9b07009c4d91a291122b3732887..3dede39344461a26043a93c12914c32d962e4f64 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -62,71 +62,1652 @@ pinmux@70000868 { pinctrl-0 = <&state_default>; state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr1_pc1 { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat4_pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat7_pd4 { + nvidia,pins = "sdmmc3_dat7_pd4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_hsync_pd7 { + nvidia,pins = "vi_hsync_pd7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d0_pe0 { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d2_pe2 { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d3_pe3 { + nvidia,pins = "lcd_d3_pe3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d4_pe4 { + nvidia,pins = "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d5_pe5 { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d6_pe6 { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d7_pe7 { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d8_pf0 { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d9_pf1 { + nvidia,pins = "lcd_d9_pf1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d10_pf2 { + nvidia,pins = "lcd_d10_pf2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d11_pf3 { + nvidia,pins = "lcd_d11_pf3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d12_pf4 { + nvidia,pins = "lcd_d12_pf4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d13_pf5 { + nvidia,pins = "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d14_pf6 { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d15_pf7 { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad1_pg1 { + nvidia,pins = "gmi_ad1_pg1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad3_pg3 { + nvidia,pins = "gmi_ad3_pg3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad7_pg7 { + nvidia,pins = "gmi_ad7_pg7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wr_n_pi0 { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_oe_n_pi1 { + nvidia,pins = "gmi_oe_n_pi1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_de_pj1 { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_hsync_pj3 { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_vsync_pj4 { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d2_pl0 { + nvidia,pins = "vi_d2_pl0"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d3_pl1 { + nvidia,pins = "vi_d3_pl1"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d5_pl3 { + nvidia,pins = "vi_d5_pl3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d7_pl5 { + nvidia,pins = "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d9_pl7 { + nvidia,pins = "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d16_pm0 { + nvidia,pins = "lcd_d16_pm0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d17_pm1 { + nvidia,pins = "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d18_pm2 { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d19_pm3 { + nvidia,pins = "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d20_pm4 { + nvidia,pins = "lcd_d20_pm4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d21_pm5 { + nvidia,pins = "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d22_pm6 { + nvidia,pins = "lcd_d22_pm6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d23_pm7 { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sdout_pn5 { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_dc0_pn6 { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d0_pt4 { + nvidia,pins = "vi_d0_pt4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_cs1_n_pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_cs0_n_px6 { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; + nvidia,pins = "sdmmc1_cmd_pz1"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; + lcd_sdin_pz2 { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; }; sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; + nvidia,pins = "sdmmc4_dat0_paa0"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_prsnt_n_pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pcie"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4", - "pex_l1_clkreq_n_pdd6"; + nvidia,pins = "pex_l1_prsnt_n_pdd4"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pcie"; nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_prsnt_n_pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdio3 { nvidia,pins = "drive_sdio3"; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 33920df036401a76c2a821089b3d093c4967a67e..107395c32d8265863fecb711311def376ab500b6 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -191,6 +191,7 @@ pmu { compatible = "arm,cortex-a15-pmu"; interrupts = <0 68 4>, <0 69 4>; + interrupt-affinity = <&cpu0>, <&cpu1>; }; oscclk6a: oscclk6a { @@ -362,7 +363,6 @@ etb@0,20010000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; - coresight-default-sink; clocks = <&oscclk6a>; clock-names = "apb_pclk"; port { diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 23662b5a5e9d84554f34eb0fc3edad1ef029f4e6..d949facba37641b3b36f337cd3eefce7932280d9 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -33,28 +33,28 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + A9_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; next-level-cache = <&L2>; }; - cpu@1 { + A9_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; next-level-cache = <&L2>; }; - cpu@2 { + A9_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; next-level-cache = <&L2>; }; - cpu@3 { + A9_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; @@ -170,6 +170,7 @@ L2: cache-controller@1e00a000 { compatible = "arm,pl310-cache"; reg = <0x1e00a000 0x1000>; interrupts = <0 43 4>; + cache-unified; cache-level = <2>; arm,data-latency = <1 1 1>; arm,tag-latency = <1 1 1>; @@ -181,6 +182,8 @@ pmu { <0 61 4>, <0 62 4>, <0 63 4>; + interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; + }; dcc { diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi index 36cafbfa1bfacd58bd9e6ebbfeaf8a18c23ff018..606753eb72c8f67d9551b19bfed61137b2ab07c2 100644 --- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi @@ -12,6 +12,12 @@ chosen { bootargs = "console=ttyLP0,115200"; }; + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -47,6 +53,21 @@ &bl { status = "okay"; }; +&dspi1 { + status = "okay"; + + mcp2515can: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio1>; + interrupts = <11 GPIO_ACTIVE_LOW>; + }; +}; + &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; @@ -94,3 +115,13 @@ &uart2 { &usbh1 { vbus-supply = <&usbh_vbus_reg>; }; + +&iomuxc { + vf610-colibri { + pinctrl_can_int: can_int { + fsl,pins = < + VF610_PAD_PTB21__GPIO_43 0x22ed + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi index 5c2b7320856dc0efc49c12cf7ff5575bf94a05dc..fbef0828e9303ca54d3a2304b0d4b2cf26bea417 100644 --- a/arch/arm/boot/dts/vf-colibri.dtsi +++ b/arch/arm/boot/dts/vf-colibri.dtsi @@ -23,6 +23,12 @@ &adc1 { status = "okay"; }; +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; +}; + &edma0 { status = "okay"; }; @@ -107,6 +113,15 @@ VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */ >; }; + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x33e2 + VF610_PAD_PTD6__DSPI1_SIN 0x33e1 + VF610_PAD_PTD7__DSPI1_SOUT 0x33e2 + VF610_PAD_PTD8__DSPI1_SCK 0x33e2 + >; + }; + pinctrl_esdhc1: esdhc1grp { fsl,pins = < VF610_PAD_PTA24__ESDHC1_CLK 0x31ef diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi index 1dbf8d2d1ddf50e034b337a64b6f74b4f868fd55..e976d2fa15274239b9ed2b0568cb9bd9ba9b2aa6 100644 --- a/arch/arm/boot/dts/vf500.dtsi +++ b/arch/arm/boot/dts/vf500.dtsi @@ -24,14 +24,13 @@ a5_cpu: cpu@0 { }; soc { - interrupt-parent = <&intc>; - aips-bus@40000000 { intc: interrupt-controller@40002000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; + interrupt-parent = <&intc>; reg = <0x40003000 0x1000>, <0x40002100 0x100>; }; @@ -40,145 +39,17 @@ global_timer: timer@40002200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x40002200 0x20>; interrupts = ; + interrupt-parent = <&intc>; clocks = <&clks VF610_CLK_PLATFORM_BUS>; }; }; }; }; -&adc0 { - interrupts = ; -}; - -&adc1 { - interrupts = ; -}; - -&can0 { - interrupts = ; -}; - -&can1 { - interrupts = ; -}; - -&dspi0 { - interrupts = ; -}; - -&edma0 { - interrupts = , - ; - interrupt-names = "edma-tx", "edma-err"; -}; - -&edma1 { - interrupts = , - ; - interrupt-names = "edma-tx", "edma-err"; -}; - -&esdhc1 { - interrupts = ; -}; - -&fec0 { - interrupts = ; -}; - -&fec1 { - interrupts = ; -}; - -&ftm { - interrupts = ; -}; - -&gpio0 { - interrupts = ; -}; - -&gpio1 { - interrupts = ; -}; - -&gpio2 { - interrupts = ; -}; - -&gpio3 { - interrupts = ; -}; - -&gpio4 { - interrupts = ; -}; - -&i2c0 { - interrupts = ; -}; - -&pit { - interrupts = ; -}; - -&qspi0 { - interrupts = ; -}; - -&sai2 { - interrupts = ; -}; - -&snvsrtc { - interrupts = ; -}; - -&src { - interrupts = ; -}; - -&uart0 { - interrupts = ; -}; - -&uart1 { - interrupts = ; -}; - -&uart2 { - interrupts = ; -}; - -&uart3 { - interrupts = ; -}; - -&uart4 { - interrupts = ; -}; - -&uart5 { - interrupts = ; -}; - -&usbdev0 { - interrupts = ; -}; - -&usbh1 { - interrupts = ; -}; - -&usbphy0 { - interrupts = ; -}; - -&usbphy1 { - interrupts = ; +&mscm_ir { + interrupt-parent = <&intc>; }; &wdoga5 { - interrupts = ; status = "okay"; }; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index a29c7ce15eafb2b8bbeffb05f173c752d319d230..4aa335166be76ae7296cbaf455a03af2e872e127 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -54,6 +54,7 @@ soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; + interrupt-parent = <&mscm_ir>; ranges; aips0: aips-bus@40000000 { @@ -62,6 +63,19 @@ aips0: aips-bus@40000000 { #size-cells = <1>; ranges; + mscm_cpucfg: cpucfg@40001000 { + compatible = "fsl,vf610-mscm-cpucfg", "syscon"; + reg = <0x40001000 0x800>; + }; + + mscm_ir: interrupt-controller@40001800 { + compatible = "fsl,vf610-mscm-ir"; + reg = <0x40001800 0x400>; + fsl,cpucfg = <&mscm_cpucfg>; + interrupt-controller; + #interrupt-cells = <2>; + }; + edma0: dma-controller@40018000 { #dma-cells = <2>; compatible = "fsl,vf610-edma"; @@ -69,6 +83,9 @@ edma0: dma-controller@40018000 { <0x40024000 0x1000>, <0x40025000 0x1000>; dma-channels = <32>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, + <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; clock-names = "dmamux0", "dmamux1"; clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>; @@ -78,6 +95,7 @@ edma0: dma-controller@40018000 { can0: flexcan@40020000 { compatible = "fsl,vf610-flexcan"; reg = <0x40020000 0x4000>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_FLEXCAN0>, <&clks VF610_CLK_FLEXCAN0>; clock-names = "ipg", "per"; @@ -87,6 +105,7 @@ can0: flexcan@40020000 { uart0: serial@40027000 { compatible = "fsl,vf610-lpuart"; reg = <0x40027000 0x1000>; + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART0>; clock-names = "ipg"; dmas = <&edma0 0 2>, @@ -98,6 +117,7 @@ uart0: serial@40027000 { uart1: serial@40028000 { compatible = "fsl,vf610-lpuart"; reg = <0x40028000 0x1000>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART1>; clock-names = "ipg"; dmas = <&edma0 0 4>, @@ -109,6 +129,7 @@ uart1: serial@40028000 { uart2: serial@40029000 { compatible = "fsl,vf610-lpuart"; reg = <0x40029000 0x1000>; + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART2>; clock-names = "ipg"; dmas = <&edma0 0 6>, @@ -120,6 +141,7 @@ uart2: serial@40029000 { uart3: serial@4002a000 { compatible = "fsl,vf610-lpuart"; reg = <0x4002a000 0x1000>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART3>; clock-names = "ipg"; dmas = <&edma0 0 8>, @@ -133,15 +155,29 @@ dspi0: dspi0@4002c000 { #size-cells = <0>; compatible = "fsl,vf610-dspi"; reg = <0x4002c000 0x1000>; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_DSPI0>; clock-names = "dspi"; spi-num-chipselects = <5>; status = "disabled"; }; + dspi1: dspi1@4002d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002d000 0x1000>; + interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_DSPI1>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + status = "disabled"; + }; + sai2: sai@40031000 { compatible = "fsl,vf610-sai"; reg = <0x40031000 0x1000>; + interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_SAI2>; clock-names = "sai"; dma-names = "tx", "rx"; @@ -153,6 +189,7 @@ sai2: sai@40031000 { pit: pit@40037000 { compatible = "fsl,vf610-pit"; reg = <0x40037000 0x1000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_PIT>; clock-names = "pit"; }; @@ -186,6 +223,7 @@ pwm1: pwm@40039000 { adc0: adc@4003b000 { compatible = "fsl,vf610-adc"; reg = <0x4003b000 0x1000>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_ADC0>; clock-names = "adc"; status = "disabled"; @@ -194,6 +232,7 @@ adc0: adc@4003b000 { wdoga5: wdog@4003e000 { compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; reg = <0x4003e000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_WDT>; clock-names = "wdog"; status = "disabled"; @@ -204,6 +243,7 @@ qspi0: quadspi@40044000 { #size-cells = <0>; compatible = "fsl,vf610-qspi"; reg = <0x40044000 0x1000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_QSPI0_EN>, <&clks VF610_CLK_QSPI0>; clock-names = "qspi_en", "qspi"; @@ -213,7 +253,6 @@ qspi0: quadspi@40044000 { iomuxc: iomuxc@40048000 { compatible = "fsl,vf610-iomuxc"; reg = <0x40048000 0x1000>; - #gpio-range-cells = <3>; }; gpio0: gpio@40049000 { @@ -221,6 +260,7 @@ gpio0: gpio@40049000 { reg = <0x40049000 0x1000 0x400ff000 0x40>; gpio-controller; #gpio-cells = <2>; + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 0 32>; @@ -231,6 +271,7 @@ gpio1: gpio@4004a000 { reg = <0x4004a000 0x1000 0x400ff040 0x40>; gpio-controller; #gpio-cells = <2>; + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 32 32>; @@ -241,6 +282,7 @@ gpio2: gpio@4004b000 { reg = <0x4004b000 0x1000 0x400ff080 0x40>; gpio-controller; #gpio-cells = <2>; + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 64 32>; @@ -251,6 +293,7 @@ gpio3: gpio@4004c000 { reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; gpio-controller; #gpio-cells = <2>; + interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 96 32>; @@ -261,6 +304,7 @@ gpio4: gpio@4004d000 { reg = <0x4004d000 0x1000 0x400ff100 0x40>; gpio-controller; #gpio-cells = <2>; + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 128 7>; @@ -274,6 +318,7 @@ anatop: anatop@40050000 { usbphy0: usbphy@40050800 { compatible = "fsl,vf610-usbphy"; reg = <0x40050800 0x400>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_USBPHY0>; fsl,anatop = <&anatop>; status = "disabled"; @@ -282,6 +327,7 @@ usbphy0: usbphy@40050800 { usbphy1: usbphy@40050c00 { compatible = "fsl,vf610-usbphy"; reg = <0x40050c00 0x400>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_USBPHY1>; fsl,anatop = <&anatop>; status = "disabled"; @@ -292,6 +338,7 @@ i2c0: i2c@40066000 { #size-cells = <0>; compatible = "fsl,vf610-i2c"; reg = <0x40066000 0x1000>; + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_I2C0>; clock-names = "ipg"; dmas = <&edma0 0 50>, @@ -311,6 +358,7 @@ clks: ccm@4006b000 { usbdev0: usb@40034000 { compatible = "fsl,vf610-usb", "fsl,imx27-usb"; reg = <0x40034000 0x800>; + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_USBC0>; fsl,usbphy = <&usbphy0>; fsl,usbmisc = <&usbmisc0 0>; @@ -329,6 +377,7 @@ usbmisc0: usb@40034800 { src: src@4006e000 { compatible = "fsl,vf610-src", "syscon"; reg = <0x4006e000 0x1000>; + interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -345,6 +394,9 @@ edma1: dma-controller@40098000 { <0x400a1000 0x1000>, <0x400a2000 0x1000>; dma-channels = <32>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; clock-names = "dmamux0", "dmamux1"; clocks = <&clks VF610_CLK_DMAMUX2>, <&clks VF610_CLK_DMAMUX3>; @@ -360,6 +412,7 @@ snvs0: snvs@400a7000 { snvsrtc: snvs-rtc-lp@34 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; reg = <0x34 0x58>; + interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_SNVS>; clock-names = "snvs-rtc"; }; @@ -368,6 +421,7 @@ snvsrtc: snvs-rtc-lp@34 { uart4: serial@400a9000 { compatible = "fsl,vf610-lpuart"; reg = <0x400a9000 0x1000>; + interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART4>; clock-names = "ipg"; status = "disabled"; @@ -376,6 +430,7 @@ uart4: serial@400a9000 { uart5: serial@400aa000 { compatible = "fsl,vf610-lpuart"; reg = <0x400aa000 0x1000>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART5>; clock-names = "ipg"; status = "disabled"; @@ -384,6 +439,7 @@ uart5: serial@400aa000 { adc1: adc@400bb000 { compatible = "fsl,vf610-adc"; reg = <0x400bb000 0x1000>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_ADC1>; clock-names = "adc"; status = "disabled"; @@ -392,6 +448,7 @@ adc1: adc@400bb000 { esdhc1: esdhc@400b2000 { compatible = "fsl,imx53-esdhc"; reg = <0x400b2000 0x1000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_IPG_BUS>, <&clks VF610_CLK_PLATFORM_BUS>, <&clks VF610_CLK_ESDHC1>; @@ -402,6 +459,7 @@ esdhc1: esdhc@400b2000 { usbh1: usb@400b4000 { compatible = "fsl,vf610-usb", "fsl,imx27-usb"; reg = <0x400b4000 0x800>; + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_USBC1>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc1 0>; @@ -420,6 +478,7 @@ usbmisc1: usb@400b4800 { ftm: ftm@400b8000 { compatible = "fsl,ftm-timer"; reg = <0x400b8000 0x1000 0x400b9000 0x1000>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; clock-names = "ftm-evt", "ftm-src", "ftm-evt-counter-en", "ftm-src-counter-en"; clocks = <&clks VF610_CLK_FTM2>, @@ -432,6 +491,7 @@ ftm: ftm@400b8000 { fec0: ethernet@400d0000 { compatible = "fsl,mvf600-fec"; reg = <0x400d0000 0x1000>; + interrupts = <78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_ENET0>, <&clks VF610_CLK_ENET0>, <&clks VF610_CLK_ENET>; @@ -442,6 +502,7 @@ fec0: ethernet@400d0000 { fec1: ethernet@400d1000 { compatible = "fsl,mvf600-fec"; reg = <0x400d1000 0x1000>; + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_ENET1>, <&clks VF610_CLK_ENET1>, <&clks VF610_CLK_ENET>; @@ -452,6 +513,7 @@ fec1: ethernet@400d1000 { can1: flexcan@400d4000 { compatible = "fsl,vf610-flexcan"; reg = <0x400d4000 0x4000>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_FLEXCAN1>, <&clks VF610_CLK_FLEXCAN1>; clock-names = "ipg", "per"; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index a5cd2eda3edf4fdb4d616999532d8f94da2d7bd3..9ea54b3dba09b7de9be7936ae0a755c4ed115a97 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -193,7 +193,7 @@ spi1: spi@e0007000 { }; gem0: ethernet@e000b000 { - compatible = "cdns,gem"; + compatible = "cdns,zynq-gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; @@ -204,7 +204,7 @@ gem0: ethernet@e000b000 { }; gem1: ethernet@e000c000 { - compatible = "cdns,gem"; + compatible = "cdns,zynq-gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c index 3c165fc2dce284593de47902637e1f7068e8798b..5f8a52ac7edf2c74ba6ba2547df969a6acfdbd87 100644 --- a/arch/arm/common/mcpm_entry.c +++ b/arch/arm/common/mcpm_entry.c @@ -55,22 +55,81 @@ bool mcpm_is_available(void) return (platform_ops) ? true : false; } +/* + * We can't use regular spinlocks. In the switcher case, it is possible + * for an outbound CPU to call power_down() after its inbound counterpart + * is already live using the same logical CPU number which trips lockdep + * debugging. + */ +static arch_spinlock_t mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED; + +static int mcpm_cpu_use_count[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER]; + +static inline bool mcpm_cluster_unused(unsigned int cluster) +{ + int i, cnt; + for (i = 0, cnt = 0; i < MAX_CPUS_PER_CLUSTER; i++) + cnt |= mcpm_cpu_use_count[cluster][i]; + return !cnt; +} + int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster) { + bool cpu_is_down, cluster_is_down; + int ret = 0; + if (!platform_ops) return -EUNATCH; /* try not to shadow power_up errors */ might_sleep(); - return platform_ops->power_up(cpu, cluster); + + /* backward compatibility callback */ + if (platform_ops->power_up) + return platform_ops->power_up(cpu, cluster); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + + /* + * Since this is called with IRQs enabled, and no arch_spin_lock_irq + * variant exists, we need to disable IRQs manually here. + */ + local_irq_disable(); + arch_spin_lock(&mcpm_lock); + + cpu_is_down = !mcpm_cpu_use_count[cluster][cpu]; + cluster_is_down = mcpm_cluster_unused(cluster); + + mcpm_cpu_use_count[cluster][cpu]++; + /* + * The only possible values are: + * 0 = CPU down + * 1 = CPU (still) up + * 2 = CPU requested to be up before it had a chance + * to actually make itself down. + * Any other value is a bug. + */ + BUG_ON(mcpm_cpu_use_count[cluster][cpu] != 1 && + mcpm_cpu_use_count[cluster][cpu] != 2); + + if (cluster_is_down) + ret = platform_ops->cluster_powerup(cluster); + if (cpu_is_down && !ret) + ret = platform_ops->cpu_powerup(cpu, cluster); + + arch_spin_unlock(&mcpm_lock); + local_irq_enable(); + return ret; } typedef void (*phys_reset_t)(unsigned long); void mcpm_cpu_power_down(void) { + unsigned int mpidr, cpu, cluster; + bool cpu_going_down, last_man; phys_reset_t phys_reset; - if (WARN_ON_ONCE(!platform_ops || !platform_ops->power_down)) - return; + if (WARN_ON_ONCE(!platform_ops)) + return; BUG_ON(!irqs_disabled()); /* @@ -79,28 +138,65 @@ void mcpm_cpu_power_down(void) */ setup_mm_for_reboot(); - platform_ops->power_down(); + /* backward compatibility callback */ + if (platform_ops->power_down) { + platform_ops->power_down(); + goto not_dead; + } + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + + __mcpm_cpu_going_down(cpu, cluster); + arch_spin_lock(&mcpm_lock); + BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP); + + mcpm_cpu_use_count[cluster][cpu]--; + BUG_ON(mcpm_cpu_use_count[cluster][cpu] != 0 && + mcpm_cpu_use_count[cluster][cpu] != 1); + cpu_going_down = !mcpm_cpu_use_count[cluster][cpu]; + last_man = mcpm_cluster_unused(cluster); + + if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { + platform_ops->cpu_powerdown_prepare(cpu, cluster); + platform_ops->cluster_powerdown_prepare(cluster); + arch_spin_unlock(&mcpm_lock); + platform_ops->cluster_cache_disable(); + __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN); + } else { + if (cpu_going_down) + platform_ops->cpu_powerdown_prepare(cpu, cluster); + arch_spin_unlock(&mcpm_lock); + /* + * If cpu_going_down is false here, that means a power_up + * request raced ahead of us. Even if we do not want to + * shut this CPU down, the caller still expects execution + * to return through the system resume entry path, like + * when the WFI is aborted due to a new IRQ or the like.. + * So let's continue with cache cleaning in all cases. + */ + platform_ops->cpu_cache_disable(); + } + + __mcpm_cpu_down(cpu, cluster); + + /* Now we are prepared for power-down, do it: */ + if (cpu_going_down) + wfi(); + +not_dead: /* * It is possible for a power_up request to happen concurrently * with a power_down request for the same CPU. In this case the - * power_down method might not be able to actually enter a - * powered down state with the WFI instruction if the power_up - * method has removed the required reset condition. The - * power_down method is then allowed to return. We must perform - * a re-entry in the kernel as if the power_up method just had - * deasserted reset on the CPU. - * - * To simplify race issues, the platform specific implementation - * must accommodate for the possibility of unordered calls to - * power_down and power_up with a usage count. Therefore, if a - * call to power_up is issued for a CPU that is not down, then - * the next call to power_down must not attempt a full shutdown - * but only do the minimum (normally disabling L1 cache and CPU - * coherency) and return just as if a concurrent power_up request - * had happened as described above. + * CPU might not be able to actually enter a powered down state + * with the WFI instruction if the power_up request has removed + * the required reset condition. We must perform a re-entry in + * the kernel as if the power_up method just had deasserted reset + * on the CPU. */ - phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset); phys_reset(virt_to_phys(mcpm_entry_point)); @@ -125,26 +221,66 @@ int mcpm_wait_for_cpu_powerdown(unsigned int cpu, unsigned int cluster) void mcpm_cpu_suspend(u64 expected_residency) { - phys_reset_t phys_reset; - - if (WARN_ON_ONCE(!platform_ops || !platform_ops->suspend)) + if (WARN_ON_ONCE(!platform_ops)) return; - BUG_ON(!irqs_disabled()); - /* Very similar to mcpm_cpu_power_down() */ - setup_mm_for_reboot(); - platform_ops->suspend(expected_residency); - phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset); - phys_reset(virt_to_phys(mcpm_entry_point)); - BUG(); + /* backward compatibility callback */ + if (platform_ops->suspend) { + phys_reset_t phys_reset; + BUG_ON(!irqs_disabled()); + setup_mm_for_reboot(); + platform_ops->suspend(expected_residency); + phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset); + phys_reset(virt_to_phys(mcpm_entry_point)); + BUG(); + } + + /* Some platforms might have to enable special resume modes, etc. */ + if (platform_ops->cpu_suspend_prepare) { + unsigned int mpidr = read_cpuid_mpidr(); + unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + arch_spin_lock(&mcpm_lock); + platform_ops->cpu_suspend_prepare(cpu, cluster); + arch_spin_unlock(&mcpm_lock); + } + mcpm_cpu_power_down(); } int mcpm_cpu_powered_up(void) { + unsigned int mpidr, cpu, cluster; + bool cpu_was_down, first_man; + unsigned long flags; + if (!platform_ops) return -EUNATCH; - if (platform_ops->powered_up) + + /* backward compatibility callback */ + if (platform_ops->powered_up) { platform_ops->powered_up(); + return 0; + } + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + local_irq_save(flags); + arch_spin_lock(&mcpm_lock); + + cpu_was_down = !mcpm_cpu_use_count[cluster][cpu]; + first_man = mcpm_cluster_unused(cluster); + + if (first_man && platform_ops->cluster_is_up) + platform_ops->cluster_is_up(cluster); + if (cpu_was_down) + mcpm_cpu_use_count[cluster][cpu] = 1; + if (platform_ops->cpu_is_up) + platform_ops->cpu_is_up(cpu, cluster); + + arch_spin_unlock(&mcpm_lock); + local_irq_restore(flags); + return 0; } @@ -334,8 +470,10 @@ int __init mcpm_sync_init( } mpidr = read_cpuid_mpidr(); this_cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); - for_each_online_cpu(i) + for_each_online_cpu(i) { + mcpm_cpu_use_count[this_cluster][i] = 1; mcpm_sync.clusters[this_cluster].cpus[i].cpu = CPU_UP; + } mcpm_sync.clusters[this_cluster].cluster = CLUSTER_UP; sync_cache_w(&mcpm_sync); diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig deleted file mode 100644 index 9e9a72e3d30faddbca84596d8bb0feae9899d402..0000000000000000000000000000000000000000 --- a/arch/arm/configs/ape6evm_defconfig +++ /dev/null @@ -1,109 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_CGROUPS=y -CONFIG_CGROUP_SCHED=y -CONFIG_KALLSYMS_ALL=y -CONFIG_EMBEDDED=y -CONFIG_PERF_EVENTS=y -CONFIG_SLAB=y -CONFIG_ARCH_SHMOBILE_LEGACY=y -CONFIG_ARCH_R8A73A4=y -CONFIG_MACH_APE6EVM=y -# CONFIG_ARM_THUMB is not set -CONFIG_CPU_BPREDICT_DISABLE=y -CONFIG_PL310_ERRATA_588369=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_SMP=y -CONFIG_SCHED_MC=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_NR_CPUS=8 -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -# CONFIG_HW_PERF_EVENTS is not set -# CONFIG_COMPACTION is not set -# CONFIG_CROSS_MEMORY_ATTACH is not set -CONFIG_ARM_APPENDED_DTB=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6_SIT is not set -CONFIG_NETFILTER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_FW_LOADER_USER_HELPER is not set -CONFIG_NETDEVICES=y -# CONFIG_NET_CADENCE is not set -CONFIG_SMC91X=y -CONFIG_SMSC911X=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=12 -CONFIG_SERIAL_SH_SCI_CONSOLE=y -CONFIG_I2C=y -CONFIG_I2C_SH_MOBILE=y -CONFIG_GPIO_SH_PFC=y -CONFIG_GPIOLIB=y -# CONFIG_HWMON is not set -CONFIG_THERMAL=y -CONFIG_RCAR_THERMAL=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MAX8973=y -# CONFIG_HID is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_SDHI=y -CONFIG_MMC_SH_MMCIF=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_DMADEVICES=y -CONFIG_SH_DMAE=y -# CONFIG_IOMMU_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_ENABLE_DEFAULT_TRACERS=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 811e72bbe6429b6e6a18ac5c31c267c178d17714..bcef49a21801436dc7f4251c3fa788e17f769a3e 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -13,10 +13,13 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_MULTI_V4T=y +CONFIG_ARCH_MULTI_V5=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_AT91=y +CONFIG_SOC_SAM_V4_V5=y CONFIG_SOC_AT91RM9200=y CONFIG_SOC_AT91SAM9=y -CONFIG_AT91_TIMER_HZ=128 CONFIG_AEABI=y CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 1d8935359fd0600ba56485a42969acbe3c4a301a..d034c96c039bd054c98eb28f4dc868e2212e53e9 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -26,6 +26,8 @@ CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" +CONFIG_CPU_IDLE=y +CONFIG_ARM_EXYNOS_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_PM=y @@ -34,6 +36,14 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +CONFIG_MWIFIEX=y +CONFIG_MWIFIEX_SDIO=y CONFIG_RFKILL_REGULATOR=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y @@ -91,9 +101,11 @@ CONFIG_CHARGER_MAX77693=y CONFIG_CHARGER_TPS65090=y CONFIG_HWMON=y CONFIG_SENSORS_LM90=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_THERMAL=y CONFIG_THERMAL=y CONFIG_EXYNOS_THERMAL=y -CONFIG_EXYNOS_THERMAL_CORE=y +CONFIG_THERMAL_EMULATION=y CONFIG_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y CONFIG_MFD_CROS_EC=y @@ -118,6 +130,7 @@ CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y CONFIG_DRM=y +CONFIG_DRM_EXYNOS_HDMI=y CONFIG_DRM_BRIDGE=y CONFIG_DRM_PTN3460=y CONFIG_DRM_PS8622=y @@ -171,10 +184,11 @@ CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_S3C=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC_CHARDEV=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_COMMON_CLK_MAX77802=y CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_EXYNOS_IOMMU=y CONFIG_EXTCON=y CONFIG_EXTCON_MAX14577=y CONFIG_EXTCON_MAX77693=y @@ -197,6 +211,8 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_CRAMFS=y CONFIG_ROMFS_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index e6b0007355f883eaca70e4ce4df5b6fcc9818ae4..d3a8018639de22d20e71e5de73a35bb1ab30309a 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -24,9 +24,8 @@ CONFIG_ARCH_MXC=y CONFIG_MACH_SCB9328=y CONFIG_MACH_APF9328=y CONFIG_MACH_MX21ADS=y -CONFIG_MACH_MX25_3DS=y CONFIG_MACH_EUKREA_CPUIMX25SD=y -CONFIG_MACH_IMX25_DT=y +CONFIG_SOC_IMX25=y CONFIG_MACH_MX27ADS=y CONFIG_MACH_MX27_3DS=y CONFIG_MACH_IMX27_VISSTRIM_M10=y @@ -177,6 +176,7 @@ CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set +CONFIG_VFAT_FS=y # CONFIG_PROC_PAGE_MONITOR is not set CONFIG_TMPFS=y CONFIG_JFFS2_FS=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index cf1e71e2f60abedc7bb8cb8c3ce5b268deaffa7e..fdeb1c83dcb57c1f2fd61c4a967df8e9248e4172 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -71,6 +71,9 @@ CONFIG_IPV6=y CONFIG_NETFILTER=y CONFIG_CAN=y CONFIG_CAN_FLEXCAN=y +CONFIG_BT=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_3WIRE=y CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_RFKILL=y @@ -168,6 +171,7 @@ CONFIG_SPI=y CONFIG_SPI_IMX=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MC9S08DZ60=y +CONFIG_GPIO_PCA953X=y CONFIG_GPIO_STMPE=y CONFIG_POWER_SUPPLY=y CONFIG_POWER_RESET=y diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig deleted file mode 100644 index 05a529311b4d964ac44a099c169f9a3f93c0e3f6..0000000000000000000000000000000000000000 --- a/arch/arm/configs/mackerel_defconfig +++ /dev/null @@ -1,157 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -# CONFIG_UTS_NS is not set -# CONFIG_IPC_NS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set -# CONFIG_NET_NS is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE_LEGACY=y -CONFIG_ARCH_SH7372=y -CONFIG_MACH_MACKEREL=y -CONFIG_MEMORY_SIZE=0x10000000 -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_FORCE_MAX_ZONEORDER=15 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_KEXEC=y -CONFIG_VFP=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_ARM_INTEGRATOR=y -CONFIG_MTD_BLOCK2MTD=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=8 -CONFIG_SERIAL_SH_SCI_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_SH_MOBILE=y -# CONFIG_HWMON is not set -# CONFIG_MFD_SUPPORT is not set -CONFIG_REGULATOR=y -CONFIG_FB=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_SH_MOBILE_LCDC=y -CONFIG_FB_SH_MOBILE_HDMI=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_SOC_SH4_FSI=y -CONFIG_USB=y -CONFIG_USB_RENESAS_USBHS_HCD=y -CONFIG_USB_RENESAS_USBHS=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_RENESAS_USBHS_UDC=y -CONFIG_MMC=y -CONFIG_MMC_SDHI=y -CONFIG_MMC_SH_MMCIF=y -CONFIG_DMADEVICES=y -CONFIG_SH_DMAE=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT2_FS_XIP=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=y -CONFIG_NLS_CODEPAGE_775=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_852=y -CONFIG_NLS_CODEPAGE_855=y -CONFIG_NLS_CODEPAGE_857=y -CONFIG_NLS_CODEPAGE_860=y -CONFIG_NLS_CODEPAGE_861=y -CONFIG_NLS_CODEPAGE_862=y -CONFIG_NLS_CODEPAGE_863=y -CONFIG_NLS_CODEPAGE_864=y -CONFIG_NLS_CODEPAGE_865=y -CONFIG_NLS_CODEPAGE_866=y -CONFIG_NLS_CODEPAGE_869=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=y -CONFIG_NLS_ISO8859_3=y -CONFIG_NLS_ISO8859_4=y -CONFIG_NLS_ISO8859_5=y -CONFIG_NLS_ISO8859_6=y -CONFIG_NLS_ISO8859_7=y -CONFIG_NLS_ISO8859_9=y -CONFIG_NLS_ISO8859_13=y -CONFIG_NLS_ISO8859_14=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_KOI8_R=y -CONFIG_NLS_KOI8_U=y -CONFIG_NLS_UTF8=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_ARM_UNWIND is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ANSI_CPRNG=y diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig deleted file mode 100644 index dd18c9e527d647b0f9685285248764571e8d1d4a..0000000000000000000000000000000000000000 --- a/arch/arm/configs/msm_defconfig +++ /dev/null @@ -1,121 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS_ALL=y -CONFIG_EMBEDDED=y -# CONFIG_SLUB_DEBUG is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_OPROFILE=y -CONFIG_KPROBES=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_ARCH_MSM=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_CLEANCACHE=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_VFP=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_CFG80211=y -CONFIG_RFKILL=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_SLIP=y -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLIP_MODE_SLIP6=y -CONFIG_USB_USBNET=y -# CONFIG_USB_NET_AX8817X is not set -# CONFIG_USB_NET_ZAURUS is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_MOUSE_PS2 is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_SPI=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -CONFIG_THERMAL=y -CONFIG_REGULATOR=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_FB=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DYNAMIC_MINORS=y -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ACM=y -CONFIG_USB_SERIAL=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_RTC_CLASS=y -CONFIG_STAGING=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT4_FS=y -CONFIG_FUSE_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_CIFS=y -CONFIG_PRINTK_TIME=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DEBUG_INFO=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_LOCKUP_DETECTOR=y -# CONFIG_DETECT_HUNG_TASK is not set -# CONFIG_SCHED_DEBUG is not set -CONFIG_TIMER_STATS=y diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig index 9d56781a8f80171e65922a44786d8bb10cbd3d4a..f69a459f4f92db0016857df6c710eb3b281c500e 100644 --- a/arch/arm/configs/multi_v5_defconfig +++ b/arch/arm/configs/multi_v5_defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_MVEBU=y CONFIG_MACH_KIRKWOOD=y CONFIG_MACH_NETXBIG=y CONFIG_ARCH_MXC=y -CONFIG_MACH_IMX25_DT=y +CONFIG_SOC_IMX25=y CONFIG_MACH_IMX27_DT=y CONFIG_ARCH_U300=y CONFIG_PCI_MVEBU=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 06075b6d246364db1c57b1e8860e6f675d1857c5..fbbb1915c6a95a81ac3edc58a6725f96c3c8b890 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -12,10 +12,12 @@ CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y CONFIG_CMDLINE_PARTITION=y CONFIG_ARCH_VIRT=y +CONFIG_ARCH_ALPINE=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_375=y CONFIG_MACH_ARMADA_38X=y +CONFIG_MACH_ARMADA_39X=y CONFIG_MACH_ARMADA_XP=y CONFIG_MACH_DOVE=y CONFIG_ARCH_BCM=y @@ -37,11 +39,14 @@ CONFIG_ARCH_HIP04=y CONFIG_ARCH_KEYSTONE=y CONFIG_ARCH_MESON=y CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX50=y CONFIG_SOC_IMX51=y CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SX=y CONFIG_SOC_VF610=y +CONFIG_SOC_LS1021A=y CONFIG_ARCH_OMAP3=y CONFIG_ARCH_OMAP4=y CONFIG_SOC_OMAP5=y @@ -91,6 +96,7 @@ CONFIG_ARCH_WM8850=y CONFIG_ARCH_ZYNQ=y CONFIG_TRUSTED_FOUNDATIONS=y CONFIG_PCI=y +CONFIG_PCI_HOST_GENERIC=y CONFIG_PCI_KEYSTONE=y CONFIG_PCI_MSI=y CONFIG_PCI_MVEBU=y @@ -133,6 +139,9 @@ CONFIG_CAN_BCM=y CONFIG_CAN_DEV=y CONFIG_CAN_XILINXCAN=y CONFIG_CAN_MCP251X=y +CONFIG_BT=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_RFKILL=y @@ -200,6 +209,8 @@ CONFIG_USB_NET_SMSC95XX=y CONFIG_BRCMFMAC=m CONFIG_RT2X00=m CONFIG_RT2800USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m CONFIG_INPUT_JOYDEV=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y @@ -208,6 +219,7 @@ CONFIG_KEYBOARD_SPEAR=y CONFIG_KEYBOARD_ST_KEYSCAN=y CONFIG_KEYBOARD_CROS_EC=y CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_ELAN_I2C=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_TOUCHSCREEN_ST1232=m @@ -308,6 +320,7 @@ CONFIG_BATTERY_SBS=y CONFIG_CHARGER_TPS65090=y CONFIG_POWER_RESET_AS3722=y CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_KEYSTONE=y CONFIG_POWER_RESET_SUN6I=y CONFIG_POWER_RESET_RMOBILE=y @@ -416,7 +429,7 @@ CONFIG_USB_EHCI_EXYNOS=y CONFIG_USB_EHCI_TEGRA=y CONFIG_USB_EHCI_HCD_STI=y CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_ISP1760_HCD=y +CONFIG_USB_ISP1760=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_STI=y CONFIG_USB_OHCI_HCD_PLATFORM=y @@ -505,7 +518,6 @@ CONFIG_DW_DMAC=y CONFIG_MV_XOR=y CONFIG_TEGRA20_APB_DMA=y CONFIG_SH_DMAE=y -CONFIG_RCAR_AUDMAC_PP=m CONFIG_RCAR_DMAC=y CONFIG_STE_DMA40=y CONFIG_SIRF_DMA=y @@ -533,6 +545,8 @@ CONFIG_MSM_MMCC_8960=y CONFIG_MSM_MMCC_8974=y CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y +CONFIG_PM_DEVFREQ=y +CONFIG_ARM_TEGRA_DEVFREQ=m CONFIG_MEMORY=y CONFIG_TI_AEMIF=y CONFIG_IIO=y @@ -550,6 +564,7 @@ CONFIG_PHY_MIPHY365X=y CONFIG_PHY_STIH41X_USB=y CONFIG_PHY_STIH407_USB=y CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_SUN9I_USB=y CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index 73673e95f23c6351982ec081533f92acd72fd52f..cacc9f4055a72945aab6dba3909b0409c6cf9abc 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -5,6 +5,7 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -12,6 +13,7 @@ CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_375=y CONFIG_MACH_ARMADA_38X=y +CONFIG_MACH_ARMADA_39X=y CONFIG_MACH_ARMADA_XP=y CONFIG_MACH_DOVE=y CONFIG_PCI=y diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index c7906c2fd645de229aeb12cde6c15cee7e0bb429..b47e7c6628c9f8883322cffba9e97c12f6963098 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -149,6 +149,7 @@ CONFIG_EXT4_FS=y CONFIG_FSCACHE=m CONFIG_FSCACHE_STATS=y CONFIG_CACHEFILES=m +CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_JFFS2_FS=y diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index a7dce674f1be073558dd062d5d29b32e331dba9d..0c8a787345368794950b28d529686a1554b4b1a0 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -34,7 +33,6 @@ CONFIG_ARCH_OMAP16XX=y CONFIG_MACH_OMAP_INNOVATOR=y CONFIG_MACH_OMAP_H2=y CONFIG_MACH_OMAP_H3=y -CONFIG_MACH_OMAP_HTCWIZARD=y CONFIG_MACH_HERALD=y CONFIG_MACH_OMAP_OSK=y CONFIG_MACH_OMAP_PERSEUS2=y @@ -55,7 +53,6 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_LEDS=y -CONFIG_LEDS_CPU=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=1f03 rootfstype=jffs2" @@ -80,8 +77,6 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_IPV6=y CONFIG_NETFILTER=y CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=y @@ -92,11 +87,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_CONNECTOR=y # CONFIG_PROC_EVENTS is not set CONFIG_MTD=y -CONFIG_MTD_DEBUG=y -CONFIG_MTD_DEBUG_VERBOSE=3 -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y @@ -113,11 +104,9 @@ CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y CONFIG_CHR_DEV_SG=y -CONFIG_SCSI_MULTI_LUN=y CONFIG_NETDEVICES=y CONFIG_TUN=y CONFIG_PHYLIB=y -CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y CONFIG_USB_CATC=y CONFIG_USB_KAWETH=y @@ -158,7 +147,6 @@ CONFIG_SPI_OMAP_UWIRE=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_NOWAYOUT=y CONFIG_OMAP_WATCHDOG=y -CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y @@ -168,7 +156,6 @@ CONFIG_FB_OMAP_LCDC_EXTERNAL=y CONFIG_FB_OMAP_LCDC_HWA742=y CONFIG_FB_OMAP_MANUAL_UPDATE=y CONFIG_FB_OMAP_LCD_MIPID=y -CONFIG_FB_OMAP_BOOTLOADER_INIT=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -194,7 +181,6 @@ CONFIG_SND_OMAP_SOC=y # CONFIG_USB_HID is not set CONFIG_USB=y CONFIG_USB_PHY=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y @@ -261,9 +247,7 @@ CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_SECURITY=y CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_PCBC=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 8e108599e1af401451aeeb01a9e6b7a1752c7c0d..3743ca221d402ce5d89df72baca5b1500ebb799b 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -1,3 +1,4 @@ +CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_FHANDLE=y @@ -86,17 +87,33 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y # CONFIG_INET_LRO is not set CONFIG_NETFILTER=y +CONFIG_PHONET=m CONFIG_CAN=m CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN_PLATFORM=m CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_CFG80211=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_AF_RXRPC=m +CONFIG_RXKAD=m CONFIG_MAC80211=m CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y @@ -163,6 +180,7 @@ CONFIG_USB_EPSON2888=y CONFIG_USB_EHCI_HCD=m CONFIG_USB_OHCI_HCD=m CONFIG_USB_KC2190=y +CONFIG_USB_CDC_PHONET=m CONFIG_LIBERTAS=m CONFIG_LIBERTAS_USB=m CONFIG_LIBERTAS_SDIO=m @@ -209,6 +227,10 @@ CONFIG_I2C_CHARDEV=y CONFIG_SPI=y CONFIG_SPI_OMAP24XX=y CONFIG_SPI_TI_QSPI=m +CONFIG_HSI=m +CONFIG_OMAP_SSI=m +CONFIG_NOKIA_MODEM=m +CONFIG_SSI_PROTOCOL=m CONFIG_PINCTRL_SINGLE=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y @@ -334,6 +356,7 @@ CONFIG_USB_CONFIGFS_ECM=y CONFIG_USB_CONFIGFS_ECM_SUBSET=y CONFIG_USB_CONFIGFS_RNDIS=y CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_PHONET=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y CONFIG_USB_CONFIGFS_F_LB_SS=y CONFIG_USB_CONFIGFS_F_FS=y @@ -342,6 +365,7 @@ CONFIG_USB_CONFIGFS_F_UAC2=y CONFIG_USB_CONFIGFS_F_MIDI=y CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_ZERO=m +CONFIG_USB_G_NOKIA=m CONFIG_MMC=y CONFIG_SDIO_UART=y CONFIG_MMC_OMAP=y @@ -349,6 +373,7 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m CONFIG_LEDS_GPIO=m +CONFIG_LEDS_PWM=m CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -368,6 +393,7 @@ CONFIG_TI_EDMA=y CONFIG_DMA_OMAP=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXTCON=m +CONFIG_EXTCON_USB_GPIO=m CONFIG_EXTCON_PALMAS=m CONFIG_TI_EMIF=m CONFIG_PWM=y @@ -390,6 +416,7 @@ CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_FS_XATTR=y diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index 8c7da3319d82b050cb964e3bd841c333481d61b8..d2f2babfd47a0985adda898f6de949cffb2010eb 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -97,9 +97,9 @@ CONFIG_PINCTRL_APQ8084=y CONFIG_PINCTRL_IPQ8064=y CONFIG_PINCTRL_MSM8960=y CONFIG_PINCTRL_MSM8X74=y +CONFIG_GPIOLIB=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y -CONFIG_POWER_SUPPLY=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_MSM=y CONFIG_THERMAL=y @@ -125,7 +125,7 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG_FILES=y CONFIG_USB_GADGET_VBUS_DRAW=500 CONFIG_MMC=y -CONFIG_MMC_BLOCK_MINORS=16 +CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y @@ -134,14 +134,15 @@ CONFIG_RTC_CLASS=y CONFIG_DMADEVICES=y CONFIG_QCOM_BAM_DMA=y CONFIG_STAGING=y -CONFIG_QCOM_GSBI=y CONFIG_COMMON_CLK_QCOM=y CONFIG_APQ_MMCC_8084=y -CONFIG_IPQ_GCC_806X=y +CONFIG_IPQ_LCC_806X=y CONFIG_MSM_GCC_8660=y +CONFIG_MSM_LCC_8960=y CONFIG_MSM_MMCC_8960=y CONFIG_MSM_MMCC_8974=y CONFIG_MSM_IOMMU=y +CONFIG_QCOM_GSBI=y CONFIG_PHY_QCOM_APQ8064_SATA=y CONFIG_PHY_QCOM_IPQ806X_SATA=y CONFIG_EXT2_FS=y diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index b17036088726eb2b135473fbd41a82d587c48f3f..b58618e2d13c51c869c3d4fa2b1c43aa7f61fd41 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -12,7 +12,9 @@ CONFIG_SLAB=y CONFIG_ARCH_SHMOBILE_MULTI=y CONFIG_ARCH_EMEV2=y CONFIG_ARCH_R7S72100=y +CONFIG_ARCH_R8A73A4=y CONFIG_ARCH_R8A7740=y +CONFIG_ARCH_R8A7778=y CONFIG_ARCH_R8A7779=y CONFIG_ARCH_R8A7790=y CONFIG_ARCH_R8A7791=y @@ -92,7 +94,6 @@ CONFIG_INPUT_ADXL34X=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_EM=y CONFIG_SERIAL_SH_SCI=y CONFIG_SERIAL_SH_SCI_NR_UARTS=20 @@ -109,6 +110,9 @@ CONFIG_SPI_SH_HSPI=y CONFIG_GPIO_EM=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_PCF857X=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_RMOBILE=y # CONFIG_HWMON is not set CONFIG_THERMAL=y CONFIG_CPU_THERMAL=y @@ -121,6 +125,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_AS3711=y CONFIG_REGULATOR_DA9210=y CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX8973=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_CONTROLLER=y @@ -133,6 +138,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_RENESAS_VSP1=y # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_ADV7180=y +CONFIG_VIDEO_ML86V7667=y CONFIG_DRM=y CONFIG_DRM_RCAR_DU=y CONFIG_FB_SH_MOBILE_LCDC=y @@ -167,6 +173,7 @@ CONFIG_LEDS_GPIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_RS5C372=y CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_RX8581=y CONFIG_DMADEVICES=y CONFIG_SH_DMAE=y CONFIG_RCAR_DMAC=y diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 8f6a5702b69619eb6d332db0dbf45853b527faa4..8ecba00dcd83def3a2ef3abc86d71e1aec942b0f 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -107,6 +107,7 @@ CONFIG_RTC_DRV_SUN6I=y CONFIG_RTC_DRV_SUNXI=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_SUN9I_USB=y CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y diff --git a/arch/arm/include/asm/arm-cci.h b/arch/arm/include/asm/arm-cci.h new file mode 100644 index 0000000000000000000000000000000000000000..fe77f7ab7e6bbb91f2683cc46b169ae76eabc8ca --- /dev/null +++ b/arch/arm/include/asm/arm-cci.h @@ -0,0 +1,42 @@ +/* + * arch/arm/include/asm/arm-cci.h + * + * Copyright (C) 2015 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __ASM_ARM_CCI_H +#define __ASM_ARM_CCI_H + +#ifdef CONFIG_MCPM +#include + +/* + * We don't have a reliable way of detecting whether, + * if we have access to secure-only registers, unless + * mcpm is registered. + */ +static inline bool platform_has_secure_cci_access(void) +{ + return mcpm_is_available(); +} + +#else +static inline bool platform_has_secure_cci_access(void) +{ + return false; +} +#endif + +#endif diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h index 8e3fcb924db6f13fcf0c5c08f6c8bb6cdc28a36b..2ef282f96651fbac9daa8b614c697c8020d1715f 100644 --- a/arch/arm/include/asm/dma-iommu.h +++ b/arch/arm/include/asm/dma-iommu.h @@ -25,7 +25,7 @@ struct dma_iommu_mapping { }; struct dma_iommu_mapping * -arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size); +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size); void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping); diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h index 3446f6a1d9fa6c982dbfc511aa34da8c8803da9e..50b378f59e086c45331a594060b1bafc3d627d48 100644 --- a/arch/arm/include/asm/mcpm.h +++ b/arch/arm/include/asm/mcpm.h @@ -171,12 +171,73 @@ void mcpm_cpu_suspend(u64 expected_residency); int mcpm_cpu_powered_up(void); /* - * Platform specific methods used in the implementation of the above API. + * Platform specific callbacks used in the implementation of the above API. + * + * cpu_powerup: + * Make given CPU runable. Called with MCPM lock held and IRQs disabled. + * The given cluster is assumed to be set up (cluster_powerup would have + * been called beforehand). Must return 0 for success or negative error code. + * + * cluster_powerup: + * Set up power for given cluster. Called with MCPM lock held and IRQs + * disabled. Called before first cpu_powerup when cluster is down. Must + * return 0 for success or negative error code. + * + * cpu_suspend_prepare: + * Special suspend configuration. Called on target CPU with MCPM lock held + * and IRQs disabled. This callback is optional. If provided, it is called + * before cpu_powerdown_prepare. + * + * cpu_powerdown_prepare: + * Configure given CPU for power down. Called on target CPU with MCPM lock + * held and IRQs disabled. Power down must be effective only at the next WFI instruction. + * + * cluster_powerdown_prepare: + * Configure given cluster for power down. Called on one CPU from target + * cluster with MCPM lock held and IRQs disabled. A cpu_powerdown_prepare + * for each CPU in the cluster has happened when this occurs. + * + * cpu_cache_disable: + * Clean and disable CPU level cache for the calling CPU. Called on with IRQs + * disabled only. The CPU is no longer cache coherent with the rest of the + * system when this returns. + * + * cluster_cache_disable: + * Clean and disable the cluster wide cache as well as the CPU level cache + * for the calling CPU. No call to cpu_cache_disable will happen for this + * CPU. Called with IRQs disabled and only when all the other CPUs are done + * with their own cpu_cache_disable. The cluster is no longer cache coherent + * with the rest of the system when this returns. + * + * cpu_is_up: + * Called on given CPU after it has been powered up or resumed. The MCPM lock + * is held and IRQs disabled. This callback is optional. + * + * cluster_is_up: + * Called by the first CPU to be powered up or resumed in given cluster. + * The MCPM lock is held and IRQs disabled. This callback is optional. If + * provided, it is called before cpu_is_up for that CPU. + * + * wait_for_powerdown: + * Wait until given CPU is powered down. This is called in sleeping context. + * Some reasonable timeout must be considered. Must return 0 for success or + * negative error code. */ struct mcpm_platform_ops { + int (*cpu_powerup)(unsigned int cpu, unsigned int cluster); + int (*cluster_powerup)(unsigned int cluster); + void (*cpu_suspend_prepare)(unsigned int cpu, unsigned int cluster); + void (*cpu_powerdown_prepare)(unsigned int cpu, unsigned int cluster); + void (*cluster_powerdown_prepare)(unsigned int cluster); + void (*cpu_cache_disable)(void); + void (*cluster_cache_disable)(void); + void (*cpu_is_up)(unsigned int cpu, unsigned int cluster); + void (*cluster_is_up)(unsigned int cluster); + int (*wait_for_powerdown)(unsigned int cpu, unsigned int cluster); + + /* deprecated callbacks */ int (*power_up)(unsigned int cpu, unsigned int cluster); void (*power_down)(void); - int (*wait_for_powerdown)(unsigned int cpu, unsigned int cluster); void (*suspend)(u64); void (*powered_up)(void); }; diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h index 2f7e6ff67d51556218dbc4e9858442da6601df81..0b579b2f4e0e6490bb396c301cd2adf433e3b1ad 100644 --- a/arch/arm/include/asm/xen/page.h +++ b/arch/arm/include/asm/xen/page.h @@ -110,5 +110,6 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn) bool xen_arch_need_swiotlb(struct device *dev, unsigned long pfn, unsigned long mfn); +unsigned long xen_get_swiotlb_free_pages(unsigned int order); #endif /* _ASM_ARM_XEN_PAGE_H */ diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S index e55a9426b49676f838663c2b6164266da7fef5e9..b03024fa671f41cebc5a0bf728b1a30fe1ad571d 100644 --- a/arch/arm/include/debug/msm.S +++ b/arch/arm/include/debug/msm.S @@ -16,24 +16,17 @@ */ .macro addruart, rp, rv, tmp -#ifdef CONFIG_DEBUG_UART_PHYS ldr \rp, =CONFIG_DEBUG_UART_PHYS ldr \rv, =CONFIG_DEBUG_UART_VIRT -#endif .endm .macro senduart, rd, rx ARM_BE8(rev \rd, \rd ) -#ifdef CONFIG_DEBUG_QCOM_UARTDM @ Write the 1 character to UARTDM_TF str \rd, [\rx, #0x70] -#else - str \rd, [\rx, #0x0C] -#endif .endm .macro waituart, rd, rx -#ifdef CONFIG_DEBUG_QCOM_UARTDM @ check for TX_EMT in UARTDM_SR ldr \rd, [\rx, #0x08] ARM_BE8(rev \rd, \rd ) @@ -55,13 +48,6 @@ ARM_BE8(rev \rd, \rd ) str \rd, [\rx, #0x40] @ UARTDM reg. Read to induce delay ldr \rd, [\rx, #0x08] -#else - @ wait for TX_READY -1001: ldr \rd, [\rx, #0x08] -ARM_BE8(rev \rd, \rd ) - tst \rd, #0x04 - beq 1001b -#endif .endm .macro busyuart, rd, rx diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h index 2499867dd0d86d79477e85ac0933228b9bbcf6a2..df3f60cb1168aff33ed9c2df530439ccfedb1a72 100644 --- a/arch/arm/include/uapi/asm/kvm.h +++ b/arch/arm/include/uapi/asm/kvm.h @@ -195,8 +195,14 @@ struct kvm_arch_memory_slot { #define KVM_ARM_IRQ_CPU_IRQ 0 #define KVM_ARM_IRQ_CPU_FIQ 1 -/* Highest supported SPI, from VGIC_NR_IRQS */ +/* + * This used to hold the highest supported SPI, but it is now obsolete + * and only here to provide source code level compatibility with older + * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. + */ +#ifndef __KERNEL__ #define KVM_ARM_IRQ_GIC_MAX 127 +#endif /* One single KVM irqchip, ie. the VGIC */ #define KVM_NR_IRQCHIPS 1 diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index f8ccc21fa032354facead9735abf9f4eb0cb7eb2..4e7f40c577e6e4fe9df3dd677b0d146b1ceb13c2 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -33,7 +33,9 @@ ret_fast_syscall: UNWIND(.fnstart ) UNWIND(.cantunwind ) disable_irq @ disable interrupts - ldr r1, [tsk, #TI_FLAGS] + ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing + tst r1, #_TIF_SYSCALL_WORK + bne __sys_trace_return tst r1, #_TIF_WORK_MASK bne fast_work_pending asm_trace_hardirqs_on diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index cc176b67c13487b080bf7d1dc430314496a8b9b1..aebfbf79a1a3f5f2a98981e5abca8657634cb7c6 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -80,9 +80,9 @@ ENTRY(stext) ldr r13, =__mmap_switched @ address to jump to after @ initialising sctlr adr lr, BSYM(1f) @ return (PIC) address - ARM( add pc, r10, #PROCINFO_INITFUNC ) - THUMB( add r12, r10, #PROCINFO_INITFUNC ) - THUMB( ret r12 ) + ldr r12, [r10, #PROCINFO_INITFUNC] + add r12, r12, r10 + ret r12 1: b __after_proc_init ENDPROC(stext) @@ -117,9 +117,9 @@ ENTRY(secondary_startup) adr lr, BSYM(__after_proc_init) @ return address mov r13, r12 @ __secondary_switched address - ARM( add pc, r10, #PROCINFO_INITFUNC ) - THUMB( add r12, r10, #PROCINFO_INITFUNC ) - THUMB( ret r12 ) + ldr r12, [r10, #PROCINFO_INITFUNC] + add r12, r12, r10 + ret r12 ENDPROC(secondary_startup) ENTRY(__secondary_switched) diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index 91c7ba182dcdd9b9e84ce8f5222181b32922deaf..3b8c2833c5379aa36ca3a0a384bb740df3f3284a 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -303,9 +303,15 @@ static int probe_current_pmu(struct arm_pmu *pmu) static int of_pmu_irq_cfg(struct platform_device *pdev) { - int i; - int *irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL); + int i, irq; + int *irqs; + /* Don't bother with PPIs; they're already affine */ + irq = platform_get_irq(pdev, 0); + if (irq >= 0 && irq_is_percpu(irq)) + return 0; + + irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL); if (!irqs) return -ENOMEM; @@ -317,7 +323,7 @@ static int of_pmu_irq_cfg(struct platform_device *pdev) i); if (!dn) { pr_warn("Failed to parse %s/interrupt-affinity[%d]\n", - of_node_full_name(dn), i); + of_node_full_name(pdev->dev.of_node), i); break; } diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index 6f536451ab784e99966a308c0892e8614214591f..d9631ecddd56ea09a9b9f922520e2e05576c974a 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -671,8 +671,7 @@ int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_level, if (!irqchip_in_kernel(kvm)) return -ENXIO; - if (irq_num < VGIC_NR_PRIVATE_IRQS || - irq_num > KVM_ARM_IRQ_GIC_MAX) + if (irq_num < VGIC_NR_PRIVATE_IRQS) return -EINVAL; return kvm_vgic_inject_irq(kvm, 0, irq_num, level); diff --git a/arch/arm/mach-alpine/Kconfig b/arch/arm/mach-alpine/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..2c44b930505a27d49bfe743f9ede46e8cbe7dfe5 --- /dev/null +++ b/arch/arm/mach-alpine/Kconfig @@ -0,0 +1,12 @@ +config ARCH_ALPINE + bool "Annapurna Labs Alpine platform" if ARCH_MULTI_V7 + select ARM_AMBA + select ARM_GIC + select GENERIC_IRQ_CHIP + select HAVE_ARM_ARCH_TIMER + select HAVE_SMP + select MFD_SYSCON + select PCI + select PCI_HOST_GENERIC + help + This enables support for the Annapurna Labs Alpine V1 boards. diff --git a/arch/arm/mach-alpine/Makefile b/arch/arm/mach-alpine/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..b6674890be7134823d2d63b88dc50698fed0daf2 --- /dev/null +++ b/arch/arm/mach-alpine/Makefile @@ -0,0 +1,2 @@ +obj-y += alpine_machine.o +obj-$(CONFIG_SMP) += platsmp.o alpine_cpu_pm.o diff --git a/arch/arm/mach-alpine/alpine_cpu_pm.c b/arch/arm/mach-alpine/alpine_cpu_pm.c new file mode 100644 index 0000000000000000000000000000000000000000..121c77c4b53c3a48c36abea3694f85ff956eaac7 --- /dev/null +++ b/arch/arm/mach-alpine/alpine_cpu_pm.c @@ -0,0 +1,70 @@ +/* + * Low-level power-management support for Alpine platform. + * + * Copyright (C) 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "alpine_cpu_pm.h" +#include "alpine_cpu_resume.h" + +/* NB registers */ +#define AL_SYSFAB_POWER_CONTROL(cpu) (0x2000 + (cpu)*0x100 + 0x20) + +static struct regmap *al_sysfabric; +static struct al_cpu_resume_regs __iomem *al_cpu_resume_regs; +static int wakeup_supported; + +int alpine_cpu_wakeup(unsigned int phys_cpu, uint32_t phys_resume_addr) +{ + if (!wakeup_supported) + return -ENOSYS; + + /* + * Set CPU resume address - + * secure firmware running on boot will jump to this address + * after setting proper CPU mode, and initialiing e.g. secure + * regs (the same mode all CPUs are booted to - usually HYP) + */ + writel(phys_resume_addr, + &al_cpu_resume_regs->per_cpu[phys_cpu].resume_addr); + + /* Power-up the CPU */ + regmap_write(al_sysfabric, AL_SYSFAB_POWER_CONTROL(phys_cpu), 0); + + return 0; +} + +void __init alpine_cpu_pm_init(void) +{ + struct device_node *np; + uint32_t watermark; + + al_sysfabric = syscon_regmap_lookup_by_compatible("al,alpine-sysfabric-service"); + + np = of_find_compatible_node(NULL, NULL, "al,alpine-cpu-resume"); + al_cpu_resume_regs = of_iomap(np, 0); + + wakeup_supported = !IS_ERR(al_sysfabric) && al_cpu_resume_regs; + + if (wakeup_supported) { + watermark = readl(&al_cpu_resume_regs->watermark); + wakeup_supported = (watermark & AL_CPU_RESUME_MAGIC_NUM_MASK) + == AL_CPU_RESUME_MAGIC_NUM; + } +} diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-alpine/alpine_cpu_pm.h similarity index 55% rename from arch/arm/mach-at91/include/mach/io.h rename to arch/arm/mach-alpine/alpine_cpu_pm.h index 2d9ca0455745524d50ec1417ec0d36596b05bea9..5179e697c492fea36b9e62f60a162209239cd368 100644 --- a/arch/arm/mach-at91/include/mach/io.h +++ b/arch/arm/mach-alpine/alpine_cpu_pm.h @@ -1,7 +1,7 @@ /* - * arch/arm/mach-at91/include/mach/io.h + * Low-level power-management support for Alpine platform. * - * Copyright (C) 2003 SAN People + * Copyright (C) 2015 Annapurna Labs Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -12,16 +12,15 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H +#ifndef __ALPINE_CPU_PM_H__ +#define __ALPINE_CPU_PM_H__ + +/* Alpine CPU Power Management Services Initialization */ +void alpine_cpu_pm_init(void); -#define IO_SPACE_LIMIT 0xFFFFFFFF -#define __io(a) __typesafe_io(a) +/* Wake-up a CPU */ +int alpine_cpu_wakeup(unsigned int phys_cpu, uint32_t phys_resume_addr); -#endif +#endif /* __ALPINE_CPU_PM_H__ */ diff --git a/arch/arm/mach-alpine/alpine_cpu_resume.h b/arch/arm/mach-alpine/alpine_cpu_resume.h new file mode 100644 index 0000000000000000000000000000000000000000..c80150c0d2d84a838f36fd927575af6241f17ab8 --- /dev/null +++ b/arch/arm/mach-alpine/alpine_cpu_resume.h @@ -0,0 +1,38 @@ +/* + * Annapurna labs cpu-resume register structure. + * + * Copyright (C) 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ALPINE_CPU_RESUME_H_ +#define ALPINE_CPU_RESUME_H_ + +/* Per-cpu regs */ +struct al_cpu_resume_regs_per_cpu { + uint32_t flags; + uint32_t resume_addr; +}; + +/* general regs */ +struct al_cpu_resume_regs { + /* Watermark for validating the CPU resume struct */ + uint32_t watermark; + uint32_t flags; + struct al_cpu_resume_regs_per_cpu per_cpu[]; +}; + +/* The expected magic number for validating the resume addresses */ +#define AL_CPU_RESUME_MAGIC_NUM 0xf0e1d200 +#define AL_CPU_RESUME_MAGIC_NUM_MASK 0xffffff00 + +#endif /* ALPINE_CPU_RESUME_H_ */ diff --git a/arch/arm/mach-alpine/alpine_machine.c b/arch/arm/mach-alpine/alpine_machine.c new file mode 100644 index 0000000000000000000000000000000000000000..b8e2145e962b21309c092a813553815aeafedd40 --- /dev/null +++ b/arch/arm/mach-alpine/alpine_machine.c @@ -0,0 +1,28 @@ +/* + * Machine declaration for Alpine platforms. + * + * Copyright (C) 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include + +static const char * const al_match[] __initconst = { + "al,alpine", + NULL, +}; + +DT_MACHINE_START(AL_DT, "Annapurna Labs Alpine") + .dt_compat = al_match, +MACHINE_END diff --git a/arch/arm/mach-alpine/platsmp.c b/arch/arm/mach-alpine/platsmp.c new file mode 100644 index 0000000000000000000000000000000000000000..f78429f48bd6527ce8d833dc2707e55c57c71be0 --- /dev/null +++ b/arch/arm/mach-alpine/platsmp.c @@ -0,0 +1,49 @@ +/* + * SMP operations for Alpine platform. + * + * Copyright (C) 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include + +#include "alpine_cpu_pm.h" + +static int alpine_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + phys_addr_t addr; + + addr = virt_to_phys(secondary_startup); + + if (addr > (phys_addr_t)(uint32_t)(-1)) { + pr_err("FAIL: resume address over 32bit (%pa)", &addr); + return -EINVAL; + } + + return alpine_cpu_wakeup(cpu_logical_map(cpu), (uint32_t)addr); +} + +static void __init alpine_smp_prepare_cpus(unsigned int max_cpus) +{ + alpine_cpu_pm_init(); +} + +static struct smp_operations alpine_smp_ops __initdata = { + .smp_prepare_cpus = alpine_smp_prepare_cpus, + .smp_boot_secondary = alpine_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(alpine_smp, "al,alpine-smp", &alpine_smp_ops); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c74a44324e5bc3dc7cb4b5e0f31e64ca8c167f5f..fd95f34945f4826610ac810180456687abbb71bf 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -1,55 +1,15 @@ -if ARCH_AT91 - -config HAVE_AT91_UTMI - bool - -config HAVE_AT91_USB_CLK - bool - -config COMMON_CLK_AT91 - bool - select COMMON_CLK - -config HAVE_AT91_SMD - bool - -config HAVE_AT91_H32MX - bool - -config SOC_SAMA5 - bool - select ATMEL_AIC5_IRQ +menuconfig ARCH_AT91 + bool "Atmel SoCs" + depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 + select ARCH_REQUIRE_GPIOLIB select COMMON_CLK_AT91 - select CPU_V7 - select GENERIC_CLOCKEVENTS - select MEMORY - select ATMEL_SDRAMC - select PHYLIB if NETDEVICES - -menu "Atmel AT91 System-on-Chip" - -choice - - prompt "Core type" - -config SOC_SAM_V4_V5 - bool "ARM9 AT91SAM9/AT91RM9200" - help - Select this if you are using one of Atmel's AT91SAM9 or - AT91RM9200 SoC. - -config SOC_SAM_V7 - bool "Cortex A5" - help - Select this if you are using one of Atmel's SAMA5D3 SoC. - -endchoice + select PINCTRL + select PINCTRL_AT91 + select SOC_BUS -comment "Atmel AT91 Processor" - -if SOC_SAM_V7 +if ARCH_AT91 config SOC_SAMA5D3 - bool "SAMA5D3 family" + bool "SAMA5D3 family" if ARCH_MULTI_V7 select SOC_SAMA5 select HAVE_FB_ATMEL select HAVE_AT91_UTMI @@ -60,9 +20,8 @@ config SOC_SAMA5D3 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36. config SOC_SAMA5D4 - bool "SAMA5D4 family" + bool "SAMA5D4 family" if ARCH_MULTI_V7 select SOC_SAMA5 - select CLKSRC_MMIO select CACHE_L2X0 select HAVE_FB_ATMEL select HAVE_AT91_UTMI @@ -71,29 +30,31 @@ config SOC_SAMA5D4 select HAVE_AT91_H32MX help Select this if you are using one of Atmel's SAMA5D4 family SoC. -endif -if SOC_SAM_V4_V5 config SOC_AT91RM9200 - bool "AT91RM9200" + bool "AT91RM9200" if ARCH_MULTI_V4T select ATMEL_AIC_IRQ - select COMMON_CLK_AT91 + select ATMEL_ST select CPU_ARM920T - select GENERIC_CLOCKEVENTS select HAVE_AT91_USB_CLK + select MIGHT_HAVE_PCI + select SOC_SAM_V4_V5 + select SRAM if PM + help + Select this if you are using Atmel's AT91RM9200 SoC. config SOC_AT91SAM9 - bool "AT91SAM9" + bool "AT91SAM9" if ARCH_MULTI_V5 select ATMEL_AIC_IRQ select ATMEL_SDRAMC - select COMMON_CLK_AT91 select CPU_ARM926T - select GENERIC_CLOCKEVENTS select HAVE_AT91_SMD select HAVE_AT91_USB_CLK select HAVE_AT91_UTMI select HAVE_FB_ATMEL select MEMORY + select SOC_SAM_V4_V5 + select SRAM if PM help Select this if you are using one of those Atmel SoC: AT91SAM9260 @@ -112,40 +73,35 @@ config SOC_AT91SAM9 AT91SAM9X25 AT91SAM9X35 AT91SAM9XE -endif # SOC_SAM_V4_V5 -comment "AT91 Feature Selections" +config HAVE_AT91_UTMI + bool -config AT91_SLOW_CLOCK - bool "Suspend-to-RAM disables main oscillator" - select SRAM - depends on SUSPEND - help - Select this if you want Suspend-to-RAM to save the most power - possible (without powering off the CPU) by disabling the PLLs - and main oscillator so that only the 32 KiHz clock is available. +config HAVE_AT91_USB_CLK + bool - When only that slow-clock is available, some peripherals lose - functionality. Many can't issue wakeup events unless faster - clocks are available. Some lose their operating state and - need to be completely re-initialized. +config COMMON_CLK_AT91 + bool + select COMMON_CLK -config AT91_TIMER_HZ - int "Kernel HZ (jiffies per second)" - range 32 1024 - depends on ARCH_AT91 - default "128" if SOC_AT91RM9200 - default "100" - help - On AT91rm9200 chips where you're using a system clock derived - from the 32768 Hz hardware clock, this tick rate should divide - it exactly: use a power-of-two value, such as 128 or 256, to - reduce timing errors caused by rounding. +config HAVE_AT91_SMD + bool + +config HAVE_AT91_H32MX + bool - On AT91sam926x chips, or otherwise when using a higher precision - system clock (of at least several MHz), rounding is less of a - problem so it can be safer to use a decimal values like 100. +config SOC_SAM_V4_V5 + bool -endmenu +config SOC_SAM_V7 + bool + +config SOC_SAMA5 + bool + select ATMEL_AIC5_IRQ + select ATMEL_SDRAMC + select MEMORY + select SOC_SAM_V7 + select SRAM if PM endif diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 827fdbcce1c7a69c1a8372db97c99e90e3019452..4fa8b4541e64fa06836c29863a574233a97227c8 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,20 +1,25 @@ # # Makefile for the linux kernel. # +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include +asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include -obj-y := setup.o +obj-y := soc.o obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o # CPU-specific support -obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o +obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o obj-$(CONFIG_SOC_SAMA5) += sama5.o # Power Management obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o +obj-$(CONFIG_PM) += pm_suspend.o +ifeq ($(CONFIG_CPU_V7),y) +AFLAGS_pm_suspend.o := -march=armv7-a +endif ifeq ($(CONFIG_PM_DEBUG),y) CFLAGS_pm.o += -DDEBUG endif diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 8fcfb70f712456e66a26e871dc6f524546980913..eaf58f88ef5dcd262a862e96b0656b03a31cf8b3 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -8,60 +8,42 @@ * Licensed under GPLv2 or later. */ -#include -#include -#include -#include +#include #include -#include #include -#include -#include -#include #include -#include -#include #include -#include - #include "generic.h" +#include "soc.h" -static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd) -{ - /* - * Perform a hardware reset with the use of the Watchdog timer. - */ - at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); - at91_st_write(AT91_ST_CR, AT91_ST_WDRST); -} - -static void __init at91rm9200_dt_timer_init(void) -{ - of_clk_init(NULL); - at91rm9200_timer_init(); -} +static const struct at91_soc rm9200_socs[] = { + AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"), + { /* sentinel */ }, +}; static void __init at91rm9200_dt_device_init(void) { - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + struct soc_device *soc; + struct device *soc_dev = NULL; + + soc = at91_soc_init(rm9200_socs); + if (soc != NULL) + soc_dev = soc_device_to_device(soc); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev); arm_pm_idle = at91rm9200_idle; - arm_pm_restart = at91rm9200_restart; at91rm9200_pm_init(); } - - static const char *at91rm9200_dt_board_compat[] __initconst = { "atmel,at91rm9200", NULL }; DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200") - .init_time = at91rm9200_dt_timer_init, - .map_io = at91_map_io, .init_machine = at91rm9200_dt_device_init, .dt_compat = at91rm9200_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-at91/at91sam9.c b/arch/arm/mach-at91/at91sam9.c index 56e3ba73ec407727eb0c2746b2f88c9edbe4b39a..e47a2093a0e723a1ef477dfc9954798f130b00f7 100644 --- a/arch/arm/mach-at91/at91sam9.c +++ b/arch/arm/mach-at91/at91sam9.c @@ -7,29 +7,68 @@ * Licensed under GPLv2 or later. */ -#include -#include -#include -#include #include -#include #include -#include -#include -#include -#include #include -#include -#include +#include #include "generic.h" +#include "soc.h" -static void __init at91sam9_dt_device_init(void) +static const struct at91_soc at91sam9_socs[] = { + AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL), + AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL), + AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL), + AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL), + AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL), + AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH, + "at91sam9m11", "at91sam9g45"), + AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH, + "at91sam9m10", "at91sam9g45"), + AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH, + "at91sam9g46", "at91sam9g45"), + AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH, + "at91sam9g45", "at91sam9g45"), + AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH, + "at91sam9g15", "at91sam9x5"), + AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH, + "at91sam9g35", "at91sam9x5"), + AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH, + "at91sam9x35", "at91sam9x5"), + AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH, + "at91sam9g25", "at91sam9x5"), + AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH, + "at91sam9x25", "at91sam9x5"), + AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH, + "at91sam9cn12", "at91sam9n12"), + AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH, + "at91sam9n12", "at91sam9n12"), + AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH, + "at91sam9cn11", "at91sam9n12"), + AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"), + AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"), + AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"), + { /* sentinel */ }, +}; + +static void __init at91sam9_common_init(void) { - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + struct soc_device *soc; + struct device *soc_dev = NULL; + + soc = at91_soc_init(at91sam9_socs); + if (soc != NULL) + soc_dev = soc_device_to_device(soc); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev); arm_pm_idle = at91sam9_idle; +} + +static void __init at91sam9_dt_device_init(void) +{ + at91sam9_common_init(); at91sam9260_pm_init(); } @@ -40,16 +79,13 @@ static const char *at91_dt_board_compat[] __initconst = { DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9") /* Maintainer: Atmel */ - .map_io = at91_map_io, .init_machine = at91sam9_dt_device_init, .dt_compat = at91_dt_board_compat, MACHINE_END static void __init at91sam9g45_dt_device_init(void) { - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - - arm_pm_idle = at91sam9_idle; + at91sam9_common_init(); at91sam9g45_pm_init(); } @@ -60,16 +96,13 @@ static const char *at91sam9g45_board_compat[] __initconst = { DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45") /* Maintainer: Atmel */ - .map_io = at91_map_io, .init_machine = at91sam9g45_dt_device_init, .dt_compat = at91sam9g45_board_compat, MACHINE_END static void __init at91sam9x5_dt_device_init(void) { - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - - arm_pm_idle = at91sam9_idle; + at91sam9_common_init(); at91sam9x5_pm_init(); } @@ -81,7 +114,6 @@ static const char *at91sam9x5_board_compat[] __initconst = { DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9") /* Maintainer: Atmel */ - .map_io = at91_map_io, .init_machine = at91sam9x5_dt_device_init, .dt_compat = at91sam9x5_board_compat, MACHINE_END diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 583369ffc284d5588b4c7f4c742cedbefb7614f3..b0fa7dc7286d9dc120a79c77be70fe0adb365910 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -18,17 +18,10 @@ extern void __init at91_map_io(void); extern void __init at91_alt_map_io(void); - /* Timer */ -extern void at91rm9200_timer_init(void); - /* idle */ extern void at91rm9200_idle(void); extern void at91sam9_idle(void); -/* Matrix */ -extern void at91_ioremap_matrix(u32 base_addr); - - #ifdef CONFIG_PM extern void __init at91rm9200_pm_init(void); extern void __init at91sam9260_pm_init(void); diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h deleted file mode 100644 index 42925e8f78e4b2774724bd091019b0dd2909e648..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91_dbgu.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Debug Unit (DBGU) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_DBGU_H -#define AT91_DBGU_H - -#define AT91_DBGU_CR (0x00) /* Control Register */ -#define AT91_DBGU_MR (0x04) /* Mode Register */ -#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ -#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ -#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ -#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */ -#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */ -#define AT91_DBGU_SR (0x14) /* Status Register */ -#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */ -#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ -#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */ - -#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */ -#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */ -#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ -#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ - -/* - * Some AT91 parts that don't have full DEBUG units still support the ID - * and extensions register. - */ -#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ -#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ -#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ -#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ -#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ -#define AT91_CIDR_SRAMSIZ_1K (1 << 16) -#define AT91_CIDR_SRAMSIZ_2K (2 << 16) -#define AT91_CIDR_SRAMSIZ_112K (4 << 16) -#define AT91_CIDR_SRAMSIZ_4K (5 << 16) -#define AT91_CIDR_SRAMSIZ_80K (6 << 16) -#define AT91_CIDR_SRAMSIZ_160K (7 << 16) -#define AT91_CIDR_SRAMSIZ_8K (8 << 16) -#define AT91_CIDR_SRAMSIZ_16K (9 << 16) -#define AT91_CIDR_SRAMSIZ_32K (10 << 16) -#define AT91_CIDR_SRAMSIZ_64K (11 << 16) -#define AT91_CIDR_SRAMSIZ_128K (12 << 16) -#define AT91_CIDR_SRAMSIZ_256K (13 << 16) -#define AT91_CIDR_SRAMSIZ_96K (14 << 16) -#define AT91_CIDR_SRAMSIZ_512K (15 << 16) -#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ -#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ -#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h deleted file mode 100644 index f8996c954131b1bdf88b75958b6d80527b4070a6..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91_matrix.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - * - * Under GPLv2 - */ - -#ifndef __MACH_AT91_MATRIX_H__ -#define __MACH_AT91_MATRIX_H__ - -#ifndef __ASSEMBLY__ -extern void __iomem *at91_matrix_base; - -#define at91_matrix_read(field) \ - __raw_readl(at91_matrix_base + field) - -#define at91_matrix_write(field, value) \ - __raw_writel(value, at91_matrix_base + field) - -#else -.extern at91_matrix_base -#endif - -#endif /* __MACH_AT91_MATRIX_H__ */ diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h index e4492b151fee6b80b5bd9ec238d796e80437577a..493bc486e85834c0f6c37e82b772b833f95ffbb3 100644 --- a/arch/arm/mach-at91/include/mach/at91_ramc.h +++ b/arch/arm/mach-at91/include/mach/at91_ramc.h @@ -21,10 +21,6 @@ extern void __iomem *at91_ramc_base[]; .extern at91_ramc_base #endif -#define AT91_MEMCTRL_MC 0 -#define AT91_MEMCTRL_SDRAMC 1 -#define AT91_MEMCTRL_DDRSDR 2 - #include #include #include diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h deleted file mode 100644 index 67fdbd13c3ed67db9ec426630ed4bb7e1b50bdb1..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91_st.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91_st.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * System Timer (ST) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_ST_H -#define AT91_ST_H - -#ifndef __ASSEMBLY__ -extern void __iomem *at91_st_base; - -#define at91_st_read(field) \ - __raw_readl(at91_st_base + field) - -#define at91_st_write(field, value) \ - __raw_writel(value, at91_st_base + field) -#else -.extern at91_st_base -#endif - -#define AT91_ST_CR 0x00 /* Control Register */ -#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ - -#define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */ -#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ - -#define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */ -#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ -#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ -#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ - -#define AT91_ST_RTMR 0x0c /* Real-time Mode Register */ -#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ - -#define AT91_ST_SR 0x10 /* Status Register */ -#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ -#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ -#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ -#define AT91_ST_ALMS (1 << 3) /* Alarm Status */ - -#define AT91_ST_IER 0x14 /* Interrupt Enable Register */ -#define AT91_ST_IDR 0x18 /* Interrupt Disable Register */ -#define AT91_ST_IMR 0x1c /* Interrupt Mask Register */ - -#define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */ -#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ - -#define AT91_ST_CRTR 0x24 /* Current Real-time Register */ -#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h deleted file mode 100644 index e67317c677617bd0374446e4646922eb60792ce6..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91rm9200.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Common definitions. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_H -#define AT91RM9200_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91RM9200_ID_US0 6 /* USART 0 */ -#define AT91RM9200_ID_US1 7 /* USART 1 */ -#define AT91RM9200_ID_US2 8 /* USART 2 */ -#define AT91RM9200_ID_US3 9 /* USART 3 */ -#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91RM9200_ID_UDP 11 /* USB Device Port */ -#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ -#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ -#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ -#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ -#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ -#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ -#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ -#define AT91RM9200_ID_UHP 23 /* USB Host port */ -#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ -#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ -#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ -#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ -#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ -#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ - - -/* - * Peripheral physical base addresses. - */ -#define AT91RM9200_BASE_TCB0 0xfffa0000 -#define AT91RM9200_BASE_TC0 0xfffa0000 -#define AT91RM9200_BASE_TC1 0xfffa0040 -#define AT91RM9200_BASE_TC2 0xfffa0080 -#define AT91RM9200_BASE_TCB1 0xfffa4000 -#define AT91RM9200_BASE_TC3 0xfffa4000 -#define AT91RM9200_BASE_TC4 0xfffa4040 -#define AT91RM9200_BASE_TC5 0xfffa4080 -#define AT91RM9200_BASE_UDP 0xfffb0000 -#define AT91RM9200_BASE_MCI 0xfffb4000 -#define AT91RM9200_BASE_TWI 0xfffb8000 -#define AT91RM9200_BASE_EMAC 0xfffbc000 -#define AT91RM9200_BASE_US0 0xfffc0000 -#define AT91RM9200_BASE_US1 0xfffc4000 -#define AT91RM9200_BASE_US2 0xfffc8000 -#define AT91RM9200_BASE_US3 0xfffcc000 -#define AT91RM9200_BASE_SSC0 0xfffd0000 -#define AT91RM9200_BASE_SSC1 0xfffd4000 -#define AT91RM9200_BASE_SSC2 0xfffd8000 -#define AT91RM9200_BASE_SPI 0xfffe0000 - - -/* - * System Peripherals - */ -#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ -#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ -#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */ -#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */ -#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ -#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */ -#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ -#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */ - -/* - * Internal Memory. - */ -#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ -#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ - -#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ - - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h deleted file mode 100644 index 416c7b6c56d3af85cf34eef90078de512047dbfa..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9260.h - * - * (C) 2006 Andrew Victor - * - * Common definitions. - * Based on AT91SAM9260 datasheet revision A (Preliminary). - * - * Includes also definitions for AT91SAM9XE and AT91SAM9G families - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_H -#define AT91SAM9260_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 - -/* - * System Peripherals - */ -#define AT91SAM9260_BASE_ECC 0xffffe800 -#define AT91SAM9260_BASE_SDRAMC 0xffffea00 -#define AT91SAM9260_BASE_SMC 0xffffec00 -#define AT91SAM9260_BASE_MATRIX 0xffffee00 -#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 -#define AT91SAM9260_BASE_PIOA 0xfffff400 -#define AT91SAM9260_BASE_PIOB 0xfffff600 -#define AT91SAM9260_BASE_PIOC 0xfffff800 -#define AT91SAM9260_BASE_RSTC 0xfffffd00 -#define AT91SAM9260_BASE_SHDWC 0xfffffd10 -#define AT91SAM9260_BASE_RTT 0xfffffd20 -#define AT91SAM9260_BASE_PIT 0xfffffd30 -#define AT91SAM9260_BASE_WDT 0xfffffd40 -#define AT91SAM9260_BASE_GPBR 0xfffffd50 - - -/* - * Internal Memory. - */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ -#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */ -#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */ - -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ - -#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ -#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ - -#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ -#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ -#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */ -#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h deleted file mode 100644 index f459df4206291fbecd2b8d190170454b607a57ee..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h - * - * Copyright (C) 2007 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9260 datasheet revision B. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_MATRIX_H -#define AT91SAM9260_MATRIX_H - -#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h deleted file mode 100644 index a041406d06ee1e0fba30451f3925ed657ec7f315..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9261.h - * - * Copyright (C) SAN People - * - * Common definitions. - * Based on AT91SAM9261 datasheet revision E. (Preliminary) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9261_H -#define AT91SAM9261_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9261_ID_US0 6 /* USART 0 */ -#define AT91SAM9261_ID_US1 7 /* USART 1 */ -#define AT91SAM9261_ID_US2 8 /* USART 2 */ -#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9261_ID_UHP 20 /* USB Host port */ -#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ -#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9261_BASE_TCB0 0xfffa0000 -#define AT91SAM9261_BASE_TC0 0xfffa0000 -#define AT91SAM9261_BASE_TC1 0xfffa0040 -#define AT91SAM9261_BASE_TC2 0xfffa0080 -#define AT91SAM9261_BASE_UDP 0xfffa4000 -#define AT91SAM9261_BASE_MCI 0xfffa8000 -#define AT91SAM9261_BASE_TWI 0xfffac000 -#define AT91SAM9261_BASE_US0 0xfffb0000 -#define AT91SAM9261_BASE_US1 0xfffb4000 -#define AT91SAM9261_BASE_US2 0xfffb8000 -#define AT91SAM9261_BASE_SSC0 0xfffbc000 -#define AT91SAM9261_BASE_SSC1 0xfffc0000 -#define AT91SAM9261_BASE_SSC2 0xfffc4000 -#define AT91SAM9261_BASE_SPI0 0xfffc8000 -#define AT91SAM9261_BASE_SPI1 0xfffcc000 - - -/* - * System Peripherals - */ -#define AT91SAM9261_BASE_SMC 0xffffec00 -#define AT91SAM9261_BASE_MATRIX 0xffffee00 -#define AT91SAM9261_BASE_SDRAMC 0xffffea00 -#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 -#define AT91SAM9261_BASE_PIOA 0xfffff400 -#define AT91SAM9261_BASE_PIOB 0xfffff600 -#define AT91SAM9261_BASE_PIOC 0xfffff800 -#define AT91SAM9261_BASE_RSTC 0xfffffd00 -#define AT91SAM9261_BASE_SHDWC 0xfffffd10 -#define AT91SAM9261_BASE_RTT 0xfffffd20 -#define AT91SAM9261_BASE_PIT 0xfffffd30 -#define AT91SAM9261_BASE_WDT 0xfffffd40 -#define AT91SAM9261_BASE_GPBR 0xfffffd50 - - -/* - * Internal Memory. - */ -#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ - -#define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */ -#define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */ - -#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ - - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h deleted file mode 100644 index a50cdf8b8ca49c753f1b332450f63cba443e5b2d..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9261_matrix.h - * - * Copyright (C) 2007 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9261_MATRIX_H -#define AT91SAM9261_MATRIX_H - -#define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ - -#define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_ITCM_64 (7 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) -#define AT91_MATRIX_DTCM_64 (7 << 4) - -#define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ - -#define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */ -#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h deleted file mode 100644 index d201029d60b386d9de9cefca0f4b03958aaab36d..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9263.h - * - * (C) 2007 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9263_H -#define AT91SAM9263_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ -#define AT91SAM9263_ID_US0 7 /* USART 0 */ -#define AT91SAM9263_ID_US1 8 /* USART 1 */ -#define AT91SAM9263_ID_US2 9 /* USART 2 */ -#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define AT91SAM9263_ID_CAN 12 /* CAN */ -#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ -#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ -#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ -#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ -#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ -#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ -#define AT91SAM9263_ID_UHP 29 /* USB Host port */ -#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9263_BASE_UDP 0xfff78000 -#define AT91SAM9263_BASE_TCB0 0xfff7c000 -#define AT91SAM9263_BASE_TC0 0xfff7c000 -#define AT91SAM9263_BASE_TC1 0xfff7c040 -#define AT91SAM9263_BASE_TC2 0xfff7c080 -#define AT91SAM9263_BASE_MCI0 0xfff80000 -#define AT91SAM9263_BASE_MCI1 0xfff84000 -#define AT91SAM9263_BASE_TWI 0xfff88000 -#define AT91SAM9263_BASE_US0 0xfff8c000 -#define AT91SAM9263_BASE_US1 0xfff90000 -#define AT91SAM9263_BASE_US2 0xfff94000 -#define AT91SAM9263_BASE_SSC0 0xfff98000 -#define AT91SAM9263_BASE_SSC1 0xfff9c000 -#define AT91SAM9263_BASE_AC97C 0xfffa0000 -#define AT91SAM9263_BASE_SPI0 0xfffa4000 -#define AT91SAM9263_BASE_SPI1 0xfffa8000 -#define AT91SAM9263_BASE_CAN 0xfffac000 -#define AT91SAM9263_BASE_PWMC 0xfffb8000 -#define AT91SAM9263_BASE_EMAC 0xfffbc000 -#define AT91SAM9263_BASE_ISI 0xfffc4000 -#define AT91SAM9263_BASE_2DGE 0xfffc8000 - -/* - * System Peripherals - */ -#define AT91SAM9263_BASE_ECC0 0xffffe000 -#define AT91SAM9263_BASE_SDRAMC0 0xffffe200 -#define AT91SAM9263_BASE_SMC0 0xffffe400 -#define AT91SAM9263_BASE_ECC1 0xffffe600 -#define AT91SAM9263_BASE_SDRAMC1 0xffffe800 -#define AT91SAM9263_BASE_SMC1 0xffffea00 -#define AT91SAM9263_BASE_MATRIX 0xffffec00 -#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 -#define AT91SAM9263_BASE_PIOA 0xfffff200 -#define AT91SAM9263_BASE_PIOB 0xfffff400 -#define AT91SAM9263_BASE_PIOC 0xfffff600 -#define AT91SAM9263_BASE_PIOD 0xfffff800 -#define AT91SAM9263_BASE_PIOE 0xfffffa00 -#define AT91SAM9263_BASE_RSTC 0xfffffd00 -#define AT91SAM9263_BASE_SHDWC 0xfffffd10 -#define AT91SAM9263_BASE_RTT0 0xfffffd20 -#define AT91SAM9263_BASE_PIT 0xfffffd30 -#define AT91SAM9263_BASE_WDT 0xfffffd40 -#define AT91SAM9263_BASE_RTT1 0xfffffd50 -#define AT91SAM9263_BASE_GPBR 0xfffffd60 - -#define AT91_SMC AT91_SMC0 - -/* - * Internal Memory. - */ -#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ -#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ - -#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ -#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ - -#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ -#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ -#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ - - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h deleted file mode 100644 index ebb5fdb565e0c71a9164429608913bdfce736544..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9263_matrix.h - * - * Copyright (C) 2006 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9263_MATRIX_H -#define AT91SAM9263_MATRIX_H - -#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ - -#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) - -#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) - -#define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */ -#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) - -#define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */ -#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) -#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h index 175e1fdd9fe8ade33846f2ff42441d61053bc928..ff54a0ce90e39d7c494c421068008260e862ebb7 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h @@ -16,8 +16,6 @@ #ifndef AT91SAM9_SMC_H #define AT91SAM9_SMC_H -#include - #ifndef __ASSEMBLY__ struct sam9_smc_config { /* Setup register */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h deleted file mode 100644 index 8eba1021f533ac9f87ad45da184b1301c3d98f40..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Chip-specific header file for the AT91SAM9G45 family - * - * Copyright (C) 2008-2009 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9G45 preliminary datasheet. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9G45_H -#define AT91SAM9G45_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ -#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ -#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ -#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ -#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ -#define AT91SAM9G45_ID_US0 7 /* USART 0 */ -#define AT91SAM9G45_ID_US1 8 /* USART 1 */ -#define AT91SAM9G45_ID_US2 9 /* USART 2 */ -#define AT91SAM9G45_ID_US3 10 /* USART 3 */ -#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ -#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ -#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ -#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ -#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ -#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ -#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ -#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ -#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ -#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ -#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9G45_BASE_UDPHS 0xfff78000 -#define AT91SAM9G45_BASE_TCB0 0xfff7c000 -#define AT91SAM9G45_BASE_TC0 0xfff7c000 -#define AT91SAM9G45_BASE_TC1 0xfff7c040 -#define AT91SAM9G45_BASE_TC2 0xfff7c080 -#define AT91SAM9G45_BASE_MCI0 0xfff80000 -#define AT91SAM9G45_BASE_TWI0 0xfff84000 -#define AT91SAM9G45_BASE_TWI1 0xfff88000 -#define AT91SAM9G45_BASE_US0 0xfff8c000 -#define AT91SAM9G45_BASE_US1 0xfff90000 -#define AT91SAM9G45_BASE_US2 0xfff94000 -#define AT91SAM9G45_BASE_US3 0xfff98000 -#define AT91SAM9G45_BASE_SSC0 0xfff9c000 -#define AT91SAM9G45_BASE_SSC1 0xfffa0000 -#define AT91SAM9G45_BASE_SPI0 0xfffa4000 -#define AT91SAM9G45_BASE_SPI1 0xfffa8000 -#define AT91SAM9G45_BASE_AC97C 0xfffac000 -#define AT91SAM9G45_BASE_TSC 0xfffb0000 -#define AT91SAM9G45_BASE_ISI 0xfffb4000 -#define AT91SAM9G45_BASE_PWMC 0xfffb8000 -#define AT91SAM9G45_BASE_EMAC 0xfffbc000 -#define AT91SAM9G45_BASE_AES 0xfffc0000 -#define AT91SAM9G45_BASE_TDES 0xfffc4000 -#define AT91SAM9G45_BASE_SHA 0xfffc8000 -#define AT91SAM9G45_BASE_TRNG 0xfffcc000 -#define AT91SAM9G45_BASE_MCI1 0xfffd0000 -#define AT91SAM9G45_BASE_TCB1 0xfffd4000 -#define AT91SAM9G45_BASE_TC3 0xfffd4000 -#define AT91SAM9G45_BASE_TC4 0xfffd4040 -#define AT91SAM9G45_BASE_TC5 0xfffd4080 - -/* - * System Peripherals - */ -#define AT91SAM9G45_BASE_ECC 0xffffe200 -#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400 -#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600 -#define AT91SAM9G45_BASE_DMA 0xffffec00 -#define AT91SAM9G45_BASE_SMC 0xffffe800 -#define AT91SAM9G45_BASE_MATRIX 0xffffea00 -#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 -#define AT91SAM9G45_BASE_PIOA 0xfffff200 -#define AT91SAM9G45_BASE_PIOB 0xfffff400 -#define AT91SAM9G45_BASE_PIOC 0xfffff600 -#define AT91SAM9G45_BASE_PIOD 0xfffff800 -#define AT91SAM9G45_BASE_PIOE 0xfffffa00 -#define AT91SAM9G45_BASE_RSTC 0xfffffd00 -#define AT91SAM9G45_BASE_SHDWC 0xfffffd10 -#define AT91SAM9G45_BASE_RTT 0xfffffd20 -#define AT91SAM9G45_BASE_PIT 0xfffffd30 -#define AT91SAM9G45_BASE_WDT 0xfffffd40 -#define AT91SAM9G45_BASE_RTC 0xfffffdb0 -#define AT91SAM9G45_BASE_GPBR 0xfffffd60 - -/* - * Internal Memory. - */ -#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ - -#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ - -#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ -#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */ -#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ -#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ - -/* - * DMA peripheral identifiers - * for hardware handshaking interface - */ -#define AT_DMA_ID_MCI0 0 -#define AT_DMA_ID_SPI0_TX 1 -#define AT_DMA_ID_SPI0_RX 2 -#define AT_DMA_ID_SPI1_TX 3 -#define AT_DMA_ID_SPI1_RX 4 -#define AT_DMA_ID_SSC0_TX 5 -#define AT_DMA_ID_SSC0_RX 6 -#define AT_DMA_ID_SSC1_TX 7 -#define AT_DMA_ID_SSC1_RX 8 -#define AT_DMA_ID_AC97_TX 9 -#define AT_DMA_ID_AC97_RX 10 -#define AT_DMA_ID_AES_TX 11 -#define AT_DMA_ID_AES_RX 12 -#define AT_DMA_ID_MCI1 13 - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h deleted file mode 100644 index b76e2ed2fbc2263f7a18ee3e07e9521bea2f4c48..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Matrix-centric header file for the AT91SAM9G45 family - * - * Copyright (C) 2008-2009 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9G45 preliminary datasheet. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9G45_MATRIX_H -#define AT91SAM9G45_MATRIX_H - -#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */ -#define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */ -#define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */ -#define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91_MATRIX_ULBT_128 (7 << 0) - -#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ - -#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ - -#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) -#define AT91_MATRIX_RCB11 (1 << 11) - -#define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) -#define AT91_MATRIX_DTCM_64 (7 << 4) -#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ -#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) -#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) - -#define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */ -#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ -#define AT91C_VDEC_SEL_OFF (0 << 0) -#define AT91C_VDEC_SEL_ON (1 << 0) - -#define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) -#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) -#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) - -#define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */ -#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ - -#define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */ -#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91_MATRIX_WPSR_WPV (1 << 0) -#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h deleted file mode 100644 index 0151bcf6163cddd349c5d6f8e88198c3831bf3b9..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * SoC specific header file for the AT91SAM9N12 - * - * Copyright (C) 2012 Atmel Corporation - * - * Common definitions, based on AT91SAM9N12 SoC datasheet - * - * Licensed under GPLv2 or later - */ - -#ifndef _AT91SAM9N12_H_ -#define _AT91SAM9N12_H_ - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */ -#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */ -#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */ -#define AT91SAM9N12_ID_USART0 5 /* USART 0 */ -#define AT91SAM9N12_ID_USART1 6 /* USART 1 */ -#define AT91SAM9N12_ID_USART2 7 /* USART 2 */ -#define AT91SAM9N12_ID_USART3 8 /* USART 3 */ -#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */ -#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */ -#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */ -#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */ -#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */ -#define AT91SAM9N12_ID_UART0 15 /* UART 0 */ -#define AT91SAM9N12_ID_UART1 16 /* UART 1 */ -#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */ -#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */ -#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */ -#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */ -#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */ -#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */ -#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */ -#define AT91SAM9N12_ID_TRNG 30 /* TRNG */ -#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9N12_BASE_USART0 0xf801c000 -#define AT91SAM9N12_BASE_USART1 0xf8020000 -#define AT91SAM9N12_BASE_USART2 0xf8024000 -#define AT91SAM9N12_BASE_USART3 0xf8028000 - -/* - * System Peripherals - */ -#define AT91SAM9N12_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory. - */ -#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h deleted file mode 100644 index 40060cd62fa9fb09db60155cef8c26d0b9604c67..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Matrix-centric header file for the AT91SAM9N12 - * - * Copyright (C) 2012 Atmel Corporation. - * - * Only EBI related registers. - * Write Protect register definitions may be useful. - * - * Licensed under GPLv2 or later. - */ - -#ifndef _AT91SAM9N12_MATRIX_H_ -#define _AT91SAM9N12_MATRIX_H_ - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) -#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) -#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ -#define AT91_MATRIX_NFD0_ON_D0 (0 << 24) -#define AT91_MATRIX_NFD0_ON_D16 (1 << 24) -#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */ -#define AT91_MATRIX_MP_OFF (0 << 25) -#define AT91_MATRIX_MP_ON (1 << 25) - -#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ -#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ - -#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ -#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91_MATRIX_WPSR_WPV (1 << 0) -#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h deleted file mode 100644 index a15db56d33fa86154020a3419db2a468a0f4b10f..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9260.h - * - * Copyright (C) 2007 Atmel Corporation - * - * Common definitions. - * Based on AT91SAM9RL datasheet revision A. (Preliminary) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef AT91SAM9RL_H -#define AT91SAM9RL_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91SAM9RL_ID_US0 6 /* USART 0 */ -#define AT91SAM9RL_ID_US1 7 /* USART 1 */ -#define AT91SAM9RL_ID_US2 8 /* USART 2 */ -#define AT91SAM9RL_ID_US3 9 /* USART 3 */ -#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ -#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ -#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ -#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ -#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ -#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ -#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ -#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9RL_BASE_TCB0 0xfffa0000 -#define AT91SAM9RL_BASE_TC0 0xfffa0000 -#define AT91SAM9RL_BASE_TC1 0xfffa0040 -#define AT91SAM9RL_BASE_TC2 0xfffa0080 -#define AT91SAM9RL_BASE_MCI 0xfffa4000 -#define AT91SAM9RL_BASE_TWI0 0xfffa8000 -#define AT91SAM9RL_BASE_TWI1 0xfffac000 -#define AT91SAM9RL_BASE_US0 0xfffb0000 -#define AT91SAM9RL_BASE_US1 0xfffb4000 -#define AT91SAM9RL_BASE_US2 0xfffb8000 -#define AT91SAM9RL_BASE_US3 0xfffbc000 -#define AT91SAM9RL_BASE_SSC0 0xfffc0000 -#define AT91SAM9RL_BASE_SSC1 0xfffc4000 -#define AT91SAM9RL_BASE_PWMC 0xfffc8000 -#define AT91SAM9RL_BASE_SPI 0xfffcc000 -#define AT91SAM9RL_BASE_TSC 0xfffd0000 -#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 -#define AT91SAM9RL_BASE_AC97C 0xfffd8000 - - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91SAM9RL_BASE_DMA 0xffffe600 -#define AT91SAM9RL_BASE_ECC 0xffffe800 -#define AT91SAM9RL_BASE_SDRAMC 0xffffea00 -#define AT91SAM9RL_BASE_SMC 0xffffec00 -#define AT91SAM9RL_BASE_MATRIX 0xffffee00 -#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0 -#define AT91SAM9RL_BASE_PIOA 0xfffff400 -#define AT91SAM9RL_BASE_PIOB 0xfffff600 -#define AT91SAM9RL_BASE_PIOC 0xfffff800 -#define AT91SAM9RL_BASE_PIOD 0xfffffa00 -#define AT91SAM9RL_BASE_RSTC 0xfffffd00 -#define AT91SAM9RL_BASE_SHDWC 0xfffffd10 -#define AT91SAM9RL_BASE_RTT 0xfffffd20 -#define AT91SAM9RL_BASE_PIT 0xfffffd30 -#define AT91SAM9RL_BASE_WDT 0xfffffd40 -#define AT91SAM9RL_BASE_GPBR 0xfffffd60 -#define AT91SAM9RL_BASE_RTC 0xfffffe00 - - -/* - * Internal Memory. - */ -#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ - -#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ - -#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h deleted file mode 100644 index 6d160adadafc1b068d23270322b7464e30f16abd..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h - * - * Copyright (C) 2007 Atmel Corporation - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9RL datasheet revision A. (Preliminary) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef AT91SAM9RL_MATRIX_H -#define AT91SAM9RL_MATRIX_H - -#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) - -#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) - -#define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h deleted file mode 100644 index 2fc76c49e97cf4152c9427f62a39bad4e71b51d4..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Chip-specific header file for the AT91SAM9x5 family - * - * Copyright (C) 2009-2012 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9x5 datasheet. - * - * Licensed under GPLv2 or later. - */ - -#ifndef AT91SAM9X5_H -#define AT91SAM9X5_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */ -#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */ -#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */ -#define AT91SAM9X5_ID_USART0 5 /* USART 0 */ -#define AT91SAM9X5_ID_USART1 6 /* USART 1 */ -#define AT91SAM9X5_ID_USART2 7 /* USART 2 */ -#define AT91SAM9X5_ID_USART3 8 /* USART 3 */ -#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */ -#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */ -#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */ -#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */ -#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */ -#define AT91SAM9X5_ID_UART0 15 /* UART 0 */ -#define AT91SAM9X5_ID_UART1 16 /* UART 1 */ -#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */ -#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */ -#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */ -#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */ -#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */ -#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */ -#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */ -#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */ -#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */ -#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */ -#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */ -#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9X5_BASE_USART0 0xf801c000 -#define AT91SAM9X5_BASE_USART1 0xf8020000 -#define AT91SAM9X5_BASE_USART2 0xf8024000 - -/* - * System Peripherals - */ -#define AT91SAM9X5_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory. - */ -#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h deleted file mode 100644 index a606d3966470da4fb411ca88419861f541d14a4b..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Matrix-centric header file for the AT91SAM9x5 family - * - * Copyright (C) 2009-2012 Atmel Corporation. - * - * Only EBI related registers. - * Write Protect register definitions may be useful. - * - * Licensed under GPLv2 or later. - */ - -#ifndef AT91SAM9X5_MATRIX_H -#define AT91SAM9X5_MATRIX_H - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) -#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) -#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ -#define AT91_MATRIX_NFD0_ON_D0 (0 << 24) -#define AT91_MATRIX_NFD0_ON_D16 (1 << 24) -#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */ -#define AT91_MATRIX_MP_OFF (0 << 25) -#define AT91_MATRIX_MP_ON (1 << 25) - -#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ -#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ - -#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ -#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91_MATRIX_WPSR_WPV (1 << 0) -#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h deleted file mode 100644 index ce7c80a44983f350260b1dd2441569798d84d0fa..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/cpu.h - * - * Copyright (C) 2006 SAN People - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __MACH_CPU_H__ -#define __MACH_CPU_H__ - -#define ARCH_ID_AT91RM9200 0x09290780 -#define ARCH_ID_AT91SAM9260 0x019803a0 -#define ARCH_ID_AT91SAM9261 0x019703a0 -#define ARCH_ID_AT91SAM9263 0x019607a0 -#define ARCH_ID_AT91SAM9G10 0x019903a0 -#define ARCH_ID_AT91SAM9G20 0x019905a0 -#define ARCH_ID_AT91SAM9RL64 0x019b03a0 -#define ARCH_ID_AT91SAM9G45 0x819b05a0 -#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ -#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ -#define ARCH_ID_AT91SAM9X5 0x819a05a0 -#define ARCH_ID_AT91SAM9N12 0x819a07a0 - -#define ARCH_ID_AT91SAM9XE128 0x329973a0 -#define ARCH_ID_AT91SAM9XE256 0x329a93a0 -#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 - -#define ARCH_ID_AT91M40800 0x14080044 -#define ARCH_ID_AT91R40807 0x44080746 -#define ARCH_ID_AT91M40807 0x14080745 -#define ARCH_ID_AT91R40008 0x44000840 - -#define ARCH_ID_SAMA5 0x8A5C07C0 - -#define ARCH_EXID_AT91SAM9M11 0x00000001 -#define ARCH_EXID_AT91SAM9M10 0x00000002 -#define ARCH_EXID_AT91SAM9G46 0x00000003 -#define ARCH_EXID_AT91SAM9G45 0x00000004 - -#define ARCH_EXID_AT91SAM9G15 0x00000000 -#define ARCH_EXID_AT91SAM9G35 0x00000001 -#define ARCH_EXID_AT91SAM9X35 0x00000002 -#define ARCH_EXID_AT91SAM9G25 0x00000003 -#define ARCH_EXID_AT91SAM9X25 0x00000004 - -#define ARCH_EXID_SAMA5D3 0x00004300 -#define ARCH_EXID_SAMA5D31 0x00444300 -#define ARCH_EXID_SAMA5D33 0x00414300 -#define ARCH_EXID_SAMA5D34 0x00414301 -#define ARCH_EXID_SAMA5D35 0x00584300 -#define ARCH_EXID_SAMA5D36 0x00004301 - -#define ARCH_EXID_SAMA5D4 0x00000007 -#define ARCH_EXID_SAMA5D41 0x00000001 -#define ARCH_EXID_SAMA5D42 0x00000002 -#define ARCH_EXID_SAMA5D43 0x00000003 -#define ARCH_EXID_SAMA5D44 0x00000004 - -#define ARCH_FAMILY_AT91SAM9 0x01900000 -#define ARCH_FAMILY_AT91SAM9XE 0x02900000 - -/* RM9200 type */ -#define ARCH_REVISON_9200_BGA (0 << 0) -#define ARCH_REVISON_9200_PQFP (1 << 0) - -#ifndef __ASSEMBLY__ -enum at91_soc_type { - /* 920T */ - AT91_SOC_RM9200, - - /* SAM92xx */ - AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, - - /* SAM9Gxx */ - AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45, - - /* SAM9RL */ - AT91_SOC_SAM9RL, - - /* SAM9X5 */ - AT91_SOC_SAM9X5, - - /* SAM9N12 */ - AT91_SOC_SAM9N12, - - /* SAMA5D3 */ - AT91_SOC_SAMA5D3, - - /* SAMA5D4 */ - AT91_SOC_SAMA5D4, - - /* Unknown type */ - AT91_SOC_UNKNOWN, -}; - -enum at91_soc_subtype { - /* RM9200 */ - AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, - - /* SAM9260 */ - AT91_SOC_SAM9XE, - - /* SAM9G45 */ - AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11, - - /* SAM9X5 */ - AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, - AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, - - /* SAMA5D3 */ - AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, - AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36, - - /* SAMA5D4 */ - AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43, - AT91_SOC_SAMA5D44, - - /* No subtype for this SoC */ - AT91_SOC_SUBTYPE_NONE, - - /* Unknown subtype */ - AT91_SOC_SUBTYPE_UNKNOWN, -}; - -struct at91_socinfo { - unsigned int type, subtype; - unsigned int cidr, exid; -}; - -extern struct at91_socinfo at91_soc_initdata; -const char *at91_get_soc_type(struct at91_socinfo *c); -const char *at91_get_soc_subtype(struct at91_socinfo *c); - -static inline int at91_soc_is_detected(void) -{ - return at91_soc_initdata.type != AT91_SOC_UNKNOWN; -} - -#ifdef CONFIG_SOC_AT91RM9200 -#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200) -#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA) -#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP) -#else -#define cpu_is_at91rm9200() (0) -#define cpu_is_at91rm9200_bga() (0) -#define cpu_is_at91rm9200_pqfp() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9 -#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE) -#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260) -#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) -#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261) -#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10) -#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263) -#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL) -#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45) -#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES) -#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10) -#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46) -#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11) -#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5) -#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15) -#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35) -#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35) -#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25) -#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25) -#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12) -#else -#define cpu_is_at91sam9xe() (0) -#define cpu_is_at91sam9260() (0) -#define cpu_is_at91sam9g20() (0) -#define cpu_is_at91sam9261() (0) -#define cpu_is_at91sam9g10() (0) -#define cpu_is_at91sam9263() (0) -#define cpu_is_at91sam9rl() (0) -#define cpu_is_at91sam9g45() (0) -#define cpu_is_at91sam9g45es() (0) -#define cpu_is_at91sam9m10() (0) -#define cpu_is_at91sam9g46() (0) -#define cpu_is_at91sam9m11() (0) -#define cpu_is_at91sam9x5() (0) -#define cpu_is_at91sam9g15() (0) -#define cpu_is_at91sam9g35() (0) -#define cpu_is_at91sam9x35() (0) -#define cpu_is_at91sam9g25() (0) -#define cpu_is_at91sam9x25() (0) -#define cpu_is_at91sam9n12() (0) -#endif - -#ifdef CONFIG_SOC_SAMA5D3 -#define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3) -#else -#define cpu_is_sama5d3() (0) -#endif - -#ifdef CONFIG_SOC_SAMA5D4 -#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4) -#else -#define cpu_is_sama5d4() (0) -#endif - -/* - * Since this is ARM, we will never run on any AVR32 CPU. But these - * definitions may reduce clutter in common drivers. - */ -#define cpu_is_at32ap7000() (0) -#endif /* __ASSEMBLY__ */ - -#endif /* __MACH_CPU_H__ */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h deleted file mode 100644 index cacbaa52418f6b17af3b2a1824fcf732871e0c49..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/hardware.h - * - * Copyright (C) 2003 SAN People - * Copyright (C) 2003 ATMEL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include - -/* DBGU base */ -/* rm9200, 9260/9g20, 9261/9g10, 9rl */ -#define AT91_BASE_DBGU0 0xfffff200 -/* 9263, 9g45, sama5d3 */ -#define AT91_BASE_DBGU1 0xffffee00 -/* sama5d4 */ -#define AT91_BASE_DBGU2 0xfc069000 - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * On all at91 except rm9200 and x40 have the System Controller starts - * at address 0xffffc000 and has a size of 16KiB. - * - * On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting - * at 0xfffff000 - * - * Removes the individual definitions of AT91_BASE_SYS and - * replaces them with a common version at base 0xfffffc000 and size 16KiB - * and map the same memory space - */ -#define AT91_BASE_SYS 0xffffc000 - -/* - * On sama5d4 there is no system controller, we map some needed peripherals - */ -#define AT91_ALT_BASE_SYS 0xfc069000 - -/* - * On all at91 have the Advanced Interrupt Controller starts at address - * 0xfffff000 and the Power Management Controller starts at 0xfffffc00 - */ -#define AT91_AIC 0xfffff000 -#define AT91_PMC 0xfffffc00 - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ - -#ifdef CONFIG_MMU -/* - * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF - * to 0xFEF78000 .. 0xFF000000. (544Kb) - */ -#define AT91_IO_PHYS_BASE 0xFFF78000 -#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE) - -/* - * On sama5d4, remap the peripherals from address 0xFC069000 .. 0xFC06F000 - * to 0xFB069000 .. 0xFB06F000. (24Kb) - */ -#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS -#define AT91_ALT_IO_VIRT_BASE IOMEM(0xFB069000) -#else -/* - * Identity mapping for the non MMU case. - */ -#define AT91_IO_PHYS_BASE AT91_BASE_SYS -#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE) - -#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS -#define AT91_ALT_IO_VIRT_BASE IOMEM(AT91_ALT_BASE_SYS) -#endif - -#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) - - /* Convert a physical IO address to virtual IO address */ -#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) -#define AT91_ALT_IO_P2V(x) ((x) - AT91_ALT_IO_PHYS_BASE + AT91_ALT_IO_VIRT_BASE) - -/* - * Virtual to Physical Address mapping for IO devices. - */ -#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) -#define AT91_ALT_VA_BASE_SYS AT91_ALT_IO_P2V(AT91_ALT_BASE_SYS) - - /* Internal SRAM is mapped below the IO devices */ -#define AT91_SRAM_MAX SZ_1M -#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX) - -/* External Memory Map */ -#define AT91_CHIPSELECT_0 0x10000000 -#define AT91_CHIPSELECT_1 0x20000000 -#define AT91_CHIPSELECT_2 0x30000000 -#define AT91_CHIPSELECT_3 0x40000000 -#define AT91_CHIPSELECT_4 0x50000000 -#define AT91_CHIPSELECT_5 0x60000000 -#define AT91_CHIPSELECT_6 0x70000000 -#define AT91_CHIPSELECT_7 0x80000000 - -/* Clocks */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -/* - * FIXME: this is needed to communicate between the pinctrl driver and - * the PM implementation in the machine. Possibly part of the PM - * implementation should be moved down into the pinctrl driver and get - * called as part of the generic suspend/resume path. - */ -#ifndef __ASSEMBLY__ -extern void at91_pinctrl_gpio_suspend(void); -extern void at91_pinctrl_gpio_resume(void); -#endif - -#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h deleted file mode 100644 index 25613d8c6dcd6687dd0b896883aedbe52f3461c6..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Chip-specific header file for the SAMA5D3 family - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - * - * Common definitions. - * Based on SAMA5D3 datasheet. - * - * Licensed under GPLv2 or later. - */ - -#ifndef SAMA5D3_H -#define SAMA5D3_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */ -#define AT91_ID_PIT 3 /* PIT */ -#define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */ -#define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */ -#define SAMA5D3_ID_PIOA 6 /* PIOA */ -#define SAMA5D3_ID_PIOB 7 /* PIOB */ -#define SAMA5D3_ID_PIOC 8 /* PIOC */ -#define SAMA5D3_ID_PIOD 9 /* PIOD */ -#define SAMA5D3_ID_PIOE 10 /* PIOE */ -#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */ -#define SAMA5D3_ID_USART0 12 /* USART0 */ -#define SAMA5D3_ID_USART1 13 /* USART1 */ -#define SAMA5D3_ID_USART2 14 /* USART2 */ -#define SAMA5D3_ID_USART3 15 /* USART3 */ -#define SAMA5D3_ID_UART0 16 /* UART 0 */ -#define SAMA5D3_ID_UART1 17 /* UART 1 */ -#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */ -#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */ -#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */ -#define SAMA5D3_ID_HSMCI0 21 /* MCI */ -#define SAMA5D3_ID_HSMCI1 22 /* MCI */ -#define SAMA5D3_ID_HSMCI2 23 /* MCI */ -#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */ -#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */ -#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */ -#define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */ -#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */ -#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */ -#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */ -#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */ -#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */ -#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */ -#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */ -#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */ -#define SAMA5D3_ID_LCDC 36 /* LCD Controller */ -#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */ -#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */ -#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */ -#define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */ -#define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */ -#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */ -#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */ -#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */ -#define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */ -#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */ - -/* - * User Peripheral physical base addresses. - */ -#define SAMA5D3_BASE_USART0 0xf001c000 -#define SAMA5D3_BASE_USART1 0xf0020000 -#define SAMA5D3_BASE_USART2 0xf8020000 -#define SAMA5D3_BASE_USART3 0xf8024000 - -/* - * System Peripherals - */ -#define SAMA5D3_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory - */ -#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h deleted file mode 100644 index f256a45d98540cd13089e90877c91bbd09fbaa1a..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Chip-specific header file for the SAMA5D4 family - * - * Copyright (C) 2013 Atmel Corporation, - * Nicolas Ferre - * - * Common definitions. - * Based on SAMA5D4 datasheet. - * - * Licensed under GPLv2 or later. - */ - -#ifndef SAMA5D4_H -#define SAMA5D4_H - -/* - * User Peripheral physical base addresses. - */ -#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3 non-secure) Base Address */ -#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */ -#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */ -#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */ - -/* Some other peripherals */ -#define SAMA5D4_BASE_SYS2 SAMA5D4_BASE_PIOD - -/* - * Internal Memory. - */ -#define SAMA5D4_NS_SRAM_BASE 0x00210000 /* Internal SRAM base address Non-Secure */ -#define SAMA5D4_NS_SRAM_SIZE (64 * SZ_1K) /* Internal SRAM size Non-Secure part (64Kb) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h deleted file mode 100644 index 4ebb609369e36895e0da7e68021eb6cbc962532e..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/include/mach/uncompress.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/uncompress.h - * - * Copyright (C) 2003 SAN People - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include -#include -#include - -#include -#include - -void __iomem *at91_uart; - -static const u32 uarts_rm9200[] = { - AT91_BASE_DBGU0, - AT91RM9200_BASE_US0, - AT91RM9200_BASE_US1, - AT91RM9200_BASE_US2, - AT91RM9200_BASE_US3, - 0, -}; - -static const u32 uarts_sam9260[] = { - AT91_BASE_DBGU0, - AT91SAM9260_BASE_US0, - AT91SAM9260_BASE_US1, - AT91SAM9260_BASE_US2, - AT91SAM9260_BASE_US3, - AT91SAM9260_BASE_US4, - AT91SAM9260_BASE_US5, - 0, -}; - -static const u32 uarts_sam9261[] = { - AT91_BASE_DBGU0, - AT91SAM9261_BASE_US0, - AT91SAM9261_BASE_US1, - AT91SAM9261_BASE_US2, - 0, -}; - -static const u32 uarts_sam9263[] = { - AT91_BASE_DBGU1, - AT91SAM9263_BASE_US0, - AT91SAM9263_BASE_US1, - AT91SAM9263_BASE_US2, - 0, -}; - -static const u32 uarts_sam9g45[] = { - AT91_BASE_DBGU1, - AT91SAM9G45_BASE_US0, - AT91SAM9G45_BASE_US1, - AT91SAM9G45_BASE_US2, - AT91SAM9G45_BASE_US3, - 0, -}; - -static const u32 uarts_sam9rl[] = { - AT91_BASE_DBGU0, - AT91SAM9RL_BASE_US0, - AT91SAM9RL_BASE_US1, - AT91SAM9RL_BASE_US2, - AT91SAM9RL_BASE_US3, - 0, -}; - -static const u32 uarts_sam9x5[] = { - AT91_BASE_DBGU0, - AT91SAM9X5_BASE_USART0, - AT91SAM9X5_BASE_USART1, - AT91SAM9X5_BASE_USART2, - 0, -}; - -static const u32 uarts_sama5d3[] = { - AT91_BASE_DBGU1, - SAMA5D3_BASE_USART0, - SAMA5D3_BASE_USART1, - SAMA5D3_BASE_USART2, - SAMA5D3_BASE_USART3, - 0, -}; - -static const u32 uarts_sama5d4[] = { - AT91_BASE_DBGU2, - SAMA5D4_BASE_USART3, - 0, -}; - -static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) -{ - u32 cidr, socid; - - cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR); - socid = cidr & ~AT91_CIDR_VERSION; - - switch (socid) { - case ARCH_ID_AT91RM9200: - return uarts_rm9200; - - case ARCH_ID_AT91SAM9G20: - case ARCH_ID_AT91SAM9260: - return uarts_sam9260; - - case ARCH_ID_AT91SAM9261: - return uarts_sam9261; - - case ARCH_ID_AT91SAM9263: - return uarts_sam9263; - - case ARCH_ID_AT91SAM9G45: - return uarts_sam9g45; - - case ARCH_ID_AT91SAM9RL64: - return uarts_sam9rl; - - case ARCH_ID_AT91SAM9N12: - case ARCH_ID_AT91SAM9X5: - return uarts_sam9x5; - - case ARCH_ID_SAMA5: - cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID); - if (cidr & ARCH_EXID_SAMA5D3) - return uarts_sama5d3; - else if (cidr & ARCH_EXID_SAMA5D4) - return uarts_sama5d4; - - break; - } - - /* at91sam9g10 */ - if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { - return uarts_sam9261; - } - /* at91sam9xe */ - else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) { - return uarts_sam9260; - } - - return NULL; -} - -static inline void arch_decomp_setup(void) -{ - int i = 0; - const u32* usarts; - - usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0); - if (!usarts) - usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1); - if (!usarts) - usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2); - if (!usarts) { - at91_uart = NULL; - return; - } - - do { - /* physical address */ - at91_uart = (void __iomem *)usarts[i]; - - if (__raw_readl(at91_uart + ATMEL_US_BRGR)) - return; - i++; - } while (usarts[i]); - - at91_uart = NULL; -} - -/* - * The following code assumes the serial port has already been - * initialized by the bootloader. If you didn't setup a port in - * your bootloader then nothing will appear (which might be desired). - * - * This does not append a newline - */ -static void putc(int c) -{ - if (!at91_uart) - return; - - while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY)) - barrier(); - __raw_writel(c, at91_uart + ATMEL_US_THR); -} - -static inline void flush(void) -{ - if (!at91_uart) - return; - - /* wait for transmission to complete */ - while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) - barrier(); -} - -#endif diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index aa4116e9452f725e0f63241cfc083576c665be19..5062699cbb1258697c8f95046f30a125e4e14cae 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -29,19 +29,26 @@ #include #include #include - -#include -#include +#include +#include #include "generic.h" #include "pm.h" +/* + * FIXME: this is needed to communicate between the pinctrl driver and + * the PM implementation in the machine. Possibly part of the PM + * implementation should be moved down into the pinctrl driver and get + * called as part of the generic suspend/resume path. + */ +extern void at91_pinctrl_gpio_suspend(void); +extern void at91_pinctrl_gpio_resume(void); + static struct { unsigned long uhp_udp_mask; int memctrl; } at91_pm_data; -static void (*at91_pm_standby)(void); void __iomem *at91_ramc_base[2]; static int at91_pm_valid_state(suspend_state_t state) @@ -119,76 +126,67 @@ int at91_suspend_entering_slow_clock(void) } EXPORT_SYMBOL(at91_suspend_entering_slow_clock); - -static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0, +static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0, void __iomem *ramc1, int memctrl); -#ifdef CONFIG_AT91_SLOW_CLOCK -extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0, +extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0, void __iomem *ramc1, int memctrl); -extern u32 at91_slow_clock_sz; -#endif +extern u32 at91_pm_suspend_in_sram_sz; + +static void at91_pm_suspend(suspend_state_t state) +{ + unsigned int pm_data = at91_pm_data.memctrl; + + pm_data |= (state == PM_SUSPEND_MEM) ? + AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0; + + flush_cache_all(); + outer_disable(); + + at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0], + at91_ramc_base[1], pm_data); + + outer_resume(); +} static int at91_pm_enter(suspend_state_t state) { at91_pinctrl_gpio_suspend(); switch (state) { + /* + * Suspend-to-RAM is like STANDBY plus slow clock mode, so + * drivers must suspend more deeply, the master clock switches + * to the clk32k and turns off the main oscillator + */ + case PM_SUSPEND_MEM: /* - * Suspend-to-RAM is like STANDBY plus slow clock mode, so - * drivers must suspend more deeply: only the master clock - * controller may be using the main oscillator. + * Ensure that clocks are in a valid state. */ - case PM_SUSPEND_MEM: - /* - * Ensure that clocks are in a valid state. - */ - if (!at91_pm_verify_clocks()) - goto error; - - /* - * Enter slow clock mode by switching over to clk32k and - * turning off the main oscillator; reverse on wakeup. - */ - if (slow_clock) { -#ifdef CONFIG_AT91_SLOW_CLOCK - /* copy slow_clock handler to SRAM, and call it */ - memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); -#endif - slow_clock(at91_pmc_base, at91_ramc_base[0], - at91_ramc_base[1], - at91_pm_data.memctrl); - break; - } else { - pr_info("AT91: PM - no slow clock mode enabled ...\n"); - /* FALLTHROUGH leaving master clock alone */ - } + if (!at91_pm_verify_clocks()) + goto error; - /* - * STANDBY mode has *all* drivers suspended; ignores irqs not - * marked as 'wakeup' event sources; and reduces DRAM power. - * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and - * nothing fancy done with main or cpu clocks. - */ - case PM_SUSPEND_STANDBY: - /* - * NOTE: the Wait-for-Interrupt instruction needs to be - * in icache so no SDRAM accesses are needed until the - * wakeup IRQ occurs and self-refresh is terminated. - * For ARM 926 based chips, this requirement is weaker - * as at91sam9 can access a RAM in self-refresh mode. - */ - if (at91_pm_standby) - at91_pm_standby(); - break; + at91_pm_suspend(state); - case PM_SUSPEND_ON: - cpu_do_idle(); - break; + break; - default: - pr_debug("AT91: PM - bogus suspend state %d\n", state); - goto error; + /* + * STANDBY mode has *all* drivers suspended; ignores irqs not + * marked as 'wakeup' event sources; and reduces DRAM power. + * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and + * nothing fancy done with main or cpu clocks. + */ + case PM_SUSPEND_STANDBY: + at91_pm_suspend(state); + break; + + case PM_SUSPEND_ON: + cpu_do_idle(); + break; + + default: + pr_debug("AT91: PM - bogus suspend state %d\n", state); + goto error; } error: @@ -218,12 +216,99 @@ static struct platform_device at91_cpuidle_device = { .name = "cpuidle-at91", }; -void at91_pm_set_standby(void (*at91_standby)(void)) +static void at91_pm_set_standby(void (*at91_standby)(void)) { - if (at91_standby) { + if (at91_standby) at91_cpuidle_device.dev.platform_data = at91_standby; - at91_pm_standby = at91_standby; +} + +/* + * The AT91RM9200 goes into self-refresh mode with this command, and will + * terminate self-refresh automatically on the next SDRAM access. + * + * Self-refresh mode is exited as soon as a memory access is made, but we don't + * know for sure when that happens. However, we need to restore the low-power + * mode if it was enabled before going idle. Restoring low-power mode while + * still in self-refresh is "not recommended", but seems to work. + */ +static void at91rm9200_standby(void) +{ + u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); + + asm volatile( + "b 1f\n\t" + ".align 5\n\t" + "1: mcr p15, 0, %0, c7, c10, 4\n\t" + " str %0, [%1, %2]\n\t" + " str %3, [%1, %4]\n\t" + " mcr p15, 0, %0, c7, c0, 4\n\t" + " str %5, [%1, %2]" + : + : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR), + "r" (1), "r" (AT91RM9200_SDRAMC_SRR), + "r" (lpr)); +} + +/* We manage both DDRAM/SDRAM controllers, we need more than one value to + * remember. + */ +static void at91_ddr_standby(void) +{ + /* Those two values allow us to delay self-refresh activation + * to the maximum. */ + u32 lpr0, lpr1 = 0; + u32 saved_lpr0, saved_lpr1 = 0; + + if (at91_ramc_base[1]) { + saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); + lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; + lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; + } + + saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); + lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; + lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; + + /* self-refresh mode now */ + at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); + + cpu_do_idle(); + + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); +} + +/* We manage both DDRAM/SDRAM controllers, we need more than one value to + * remember. + */ +static void at91sam9_sdram_standby(void) +{ + u32 lpr0, lpr1 = 0; + u32 saved_lpr0, saved_lpr1 = 0; + + if (at91_ramc_base[1]) { + saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); + lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; + lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; } + + saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); + lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; + lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; + + /* self-refresh mode now */ + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); + + cpu_do_idle(); + + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); } static const struct of_device_id ramc_ids[] __initconst = { @@ -263,7 +348,6 @@ static __init void at91_dt_ramc(void) at91_pm_set_standby(standby); } -#ifdef CONFIG_AT91_SLOW_CLOCK static void __init at91_pm_sram_init(void) { struct gen_pool *sram_pool; @@ -291,30 +375,36 @@ static void __init at91_pm_sram_init(void) return; } - sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz); + sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); if (!sram_base) { - pr_warn("%s: unable to alloc ocram!\n", __func__); + pr_warn("%s: unable to alloc sram!\n", __func__); return; } sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); - slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false); -} -#endif + at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, + at91_pm_suspend_in_sram_sz, false); + if (!at91_suspend_sram_fn) { + pr_warn("SRAM: Could not map\n"); + return; + } + /* Copy the pm suspend handler to SRAM */ + at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, + &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); +} static void __init at91_pm_init(void) { -#ifdef CONFIG_AT91_SLOW_CLOCK at91_pm_sram_init(); -#endif - - pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); if (at91_cpuidle_device.dev.platform_data) platform_device_register(&at91_cpuidle_device); - suspend_set_ops(&at91_pm_ops); + if (at91_suspend_sram_fn) + suspend_set_ops(&at91_pm_ops); + else + pr_info("AT91: PM not supported, due to no SRAM allocated\n"); } void __init at91rm9200_pm_init(void) diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 86c0aa819d2590aae5af7146e5e3a4ebeb086e35..ecd875a91d5218281049b6b4b36924ddcc62b1d3 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -15,100 +15,16 @@ #include -#ifdef CONFIG_PM -extern void at91_pm_set_standby(void (*at91_standby)(void)); -#else -static inline void at91_pm_set_standby(void (*at91_standby)(void)) { } -#endif - -/* - * The AT91RM9200 goes into self-refresh mode with this command, and will - * terminate self-refresh automatically on the next SDRAM access. - * - * Self-refresh mode is exited as soon as a memory access is made, but we don't - * know for sure when that happens. However, we need to restore the low-power - * mode if it was enabled before going idle. Restoring low-power mode while - * still in self-refresh is "not recommended", but seems to work. - */ - -static inline void at91rm9200_standby(void) -{ - u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); - - asm volatile( - "b 1f\n\t" - ".align 5\n\t" - "1: mcr p15, 0, %0, c7, c10, 4\n\t" - " str %0, [%1, %2]\n\t" - " str %3, [%1, %4]\n\t" - " mcr p15, 0, %0, c7, c0, 4\n\t" - " str %5, [%1, %2]" - : - : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR), - "r" (1), "r" (AT91RM9200_SDRAMC_SRR), - "r" (lpr)); -} - -/* We manage both DDRAM/SDRAM controllers, we need more than one value to - * remember. - */ -static inline void at91_ddr_standby(void) -{ - /* Those two values allow us to delay self-refresh activation - * to the maximum. */ - u32 lpr0, lpr1 = 0; - u32 saved_lpr0, saved_lpr1 = 0; - - if (at91_ramc_base[1]) { - saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); - lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; - lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; - } - - saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); - lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; - lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; - - /* self-refresh mode now */ - at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); - - cpu_do_idle(); - - at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); -} - -/* We manage both DDRAM/SDRAM controllers, we need more than one value to - * remember. - */ -static inline void at91sam9_sdram_standby(void) -{ - u32 lpr0, lpr1 = 0; - u32 saved_lpr0, saved_lpr1 = 0; - - if (at91_ramc_base[1]) { - saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); - lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; - lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; - } - - saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); - lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; - lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; +#define AT91_MEMCTRL_MC 0 +#define AT91_MEMCTRL_SDRAMC 1 +#define AT91_MEMCTRL_DDRSDR 2 - /* self-refresh mode now */ - at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); +#define AT91_PM_MEMTYPE_MASK 0x0f - cpu_do_idle(); +#define AT91_PM_MODE_OFFSET 4 +#define AT91_PM_MODE_MASK 0x01 +#define AT91_PM_MODE(x) (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET) - at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); -} +#define AT91_PM_SLOW_CLOCK 0x01 #endif diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S deleted file mode 100644 index 931f0e302c035ecc33a138ec0bd61dc910321c66..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/pm_slowclock.S +++ /dev/null @@ -1,335 +0,0 @@ -/* - * arch/arm/mach-at91/pm_slow_clock.S - * - * Copyright (C) 2006 Savin Zlobec - * - * AT91SAM9 support: - * Copyright (C) 2007 Anti Sullin -#include -#include -#include - -/* - * When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master - * clock during suspend by adjusting its prescalar and divisor. - * NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there - * are errata regarding adjusting the prescalar and divisor. - */ -#undef SLOWDOWN_MASTER_CLOCK - -pmc .req r0 -sdramc .req r1 -ramc1 .req r2 -memctrl .req r3 -tmp1 .req r4 -tmp2 .req r5 - -/* - * Wait until master clock is ready (after switching master clock source) - */ - .macro wait_mckrdy -1: ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_MCKRDY - beq 1b - .endm - -/* - * Wait until master oscillator has stabilized. - */ - .macro wait_moscrdy -1: ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_MOSCS - beq 1b - .endm - -/* - * Wait until PLLA has locked. - */ - .macro wait_pllalock -1: ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_LOCKA - beq 1b - .endm - -/* - * Wait until PLLB has locked. - */ - .macro wait_pllblock -1: ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_LOCKB - beq 1b - .endm - - .text - - .arm - -/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc, - * void __iomem *ramc1, int memctrl) - */ -ENTRY(at91_slow_clock) - /* Save registers on stack */ - stmfd sp!, {r4 - r12, lr} - - /* - * Register usage: - * R0 = Base address of AT91_PMC - * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) - * R2 = Base address of second RAM Controller or 0 if not present - * R3 = Memory controller - * R4 = temporary register - * R5 = temporary register - */ - - /* Drain write buffer */ - mov tmp1, #0 - mcr p15, 0, tmp1, c7, c10, 4 - - cmp memctrl, #AT91_MEMCTRL_MC - bne ddr_sr_enable - - /* - * at91rm9200 Memory controller - */ - /* Put SDRAM in self-refresh mode */ - mov tmp1, #1 - str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR] - b sdr_sr_done - - /* - * DDRSDR Memory controller - */ -ddr_sr_enable: - cmp memctrl, #AT91_MEMCTRL_DDRSDR - bne sdr_sr_enable - - /* LPDDR1 --> force DDR2 mode during self-refresh */ - ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR] - str tmp1, .saved_sam9_mdr - bic tmp1, tmp1, #~AT91_DDRSDRC_MD - cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR - ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR] - biceq tmp1, tmp1, #AT91_DDRSDRC_MD - orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2 - streq tmp1, [sdramc, #AT91_DDRSDRC_MDR] - - /* prepare for DDRAM self-refresh mode */ - ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR] - str tmp1, .saved_sam9_lpr - bic tmp1, #AT91_DDRSDRC_LPCB - orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH - - /* figure out if we use the second ram controller */ - cmp ramc1, #0 - beq ddr_no_2nd_ctrl - - ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR] - str tmp2, .saved_sam9_mdr1 - bic tmp2, tmp2, #~AT91_DDRSDRC_MD - cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR - ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR] - biceq tmp2, tmp2, #AT91_DDRSDRC_MD - orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2 - streq tmp2, [ramc1, #AT91_DDRSDRC_MDR] - - ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR] - str tmp2, .saved_sam9_lpr1 - bic tmp2, #AT91_DDRSDRC_LPCB - orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH - - /* Enable DDRAM self-refresh mode */ - str tmp2, [ramc1, #AT91_DDRSDRC_LPR] -ddr_no_2nd_ctrl: - str tmp1, [sdramc, #AT91_DDRSDRC_LPR] - - b sdr_sr_done - - /* - * SDRAMC Memory controller - */ -sdr_sr_enable: - /* Enable SDRAM self-refresh mode */ - ldr tmp1, [sdramc, #AT91_SDRAMC_LPR] - str tmp1, .saved_sam9_lpr - - bic tmp1, #AT91_SDRAMC_LPCB - orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH - str tmp1, [sdramc, #AT91_SDRAMC_LPR] - -sdr_sr_done: - /* Save Master clock setting */ - ldr tmp1, [pmc, #AT91_PMC_MCKR] - str tmp1, .saved_mckr - - /* - * Set the Master clock source to slow clock - */ - bic tmp1, tmp1, #AT91_PMC_CSS - str tmp1, [pmc, #AT91_PMC_MCKR] - - wait_mckrdy - -#ifdef SLOWDOWN_MASTER_CLOCK - /* - * Set the Master Clock PRES and MDIV fields. - * - * See AT91RM9200 errata #27 and #28 for details. - */ - mov tmp1, #0 - str tmp1, [pmc, #AT91_PMC_MCKR] - - wait_mckrdy -#endif - - /* Save PLLA setting and disable it */ - ldr tmp1, [pmc, #AT91_CKGR_PLLAR] - str tmp1, .saved_pllar - - mov tmp1, #AT91_PMC_PLLCOUNT - orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ - str tmp1, [pmc, #AT91_CKGR_PLLAR] - - /* Save PLLB setting and disable it */ - ldr tmp1, [pmc, #AT91_CKGR_PLLBR] - str tmp1, .saved_pllbr - - mov tmp1, #AT91_PMC_PLLCOUNT - str tmp1, [pmc, #AT91_CKGR_PLLBR] - - /* Turn off the main oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] - bic tmp1, tmp1, #AT91_PMC_MOSCEN - orr tmp1, tmp1, #AT91_PMC_KEY - str tmp1, [pmc, #AT91_CKGR_MOR] - - /* Wait for interrupt */ - mcr p15, 0, tmp1, c7, c0, 4 - - /* Turn on the main oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] - orr tmp1, tmp1, #AT91_PMC_MOSCEN - orr tmp1, tmp1, #AT91_PMC_KEY - str tmp1, [pmc, #AT91_CKGR_MOR] - - wait_moscrdy - - /* Restore PLLB setting */ - ldr tmp1, .saved_pllbr - str tmp1, [pmc, #AT91_CKGR_PLLBR] - - tst tmp1, #(AT91_PMC_MUL & 0xff0000) - bne 1f - tst tmp1, #(AT91_PMC_MUL & ~0xff0000) - beq 2f -1: - wait_pllblock -2: - - /* Restore PLLA setting */ - ldr tmp1, .saved_pllar - str tmp1, [pmc, #AT91_CKGR_PLLAR] - - tst tmp1, #(AT91_PMC_MUL & 0xff0000) - bne 3f - tst tmp1, #(AT91_PMC_MUL & ~0xff0000) - beq 4f -3: - wait_pllalock -4: - -#ifdef SLOWDOWN_MASTER_CLOCK - /* - * First set PRES if it was not 0, - * than set CSS and MDIV fields. - * - * See AT91RM9200 errata #27 and #28 for details. - */ - ldr tmp1, .saved_mckr - tst tmp1, #AT91_PMC_PRES - beq 2f - and tmp1, tmp1, #AT91_PMC_PRES - str tmp1, [pmc, #AT91_PMC_MCKR] - - wait_mckrdy -#endif - - /* - * Restore master clock setting - */ -2: ldr tmp1, .saved_mckr - str tmp1, [pmc, #AT91_PMC_MCKR] - - wait_mckrdy - - /* - * at91rm9200 Memory controller - * Do nothing - self-refresh is automatically disabled. - */ - cmp memctrl, #AT91_MEMCTRL_MC - beq ram_restored - - /* - * DDRSDR Memory controller - */ - cmp memctrl, #AT91_MEMCTRL_DDRSDR - bne sdr_en_restore - /* Restore MDR in case of LPDDR1 */ - ldr tmp1, .saved_sam9_mdr - str tmp1, [sdramc, #AT91_DDRSDRC_MDR] - /* Restore LPR on AT91 with DDRAM */ - ldr tmp1, .saved_sam9_lpr - str tmp1, [sdramc, #AT91_DDRSDRC_LPR] - - /* if we use the second ram controller */ - cmp ramc1, #0 - ldrne tmp2, .saved_sam9_mdr1 - strne tmp2, [ramc1, #AT91_DDRSDRC_MDR] - ldrne tmp2, .saved_sam9_lpr1 - strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] - - b ram_restored - - /* - * SDRAMC Memory controller - */ -sdr_en_restore: - /* Restore LPR on AT91 with SDRAM */ - ldr tmp1, .saved_sam9_lpr - str tmp1, [sdramc, #AT91_SDRAMC_LPR] - -ram_restored: - /* Restore registers, and return */ - ldmfd sp!, {r4 - r12, pc} - - -.saved_mckr: - .word 0 - -.saved_pllar: - .word 0 - -.saved_pllbr: - .word 0 - -.saved_sam9_lpr: - .word 0 - -.saved_sam9_lpr1: - .word 0 - -.saved_sam9_mdr: - .word 0 - -.saved_sam9_mdr1: - .word 0 - -ENTRY(at91_slow_clock_sz) - .word .-at91_slow_clock diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S new file mode 100644 index 0000000000000000000000000000000000000000..bd22b2c8a05190423c84d71ca76b114a88c27571 --- /dev/null +++ b/arch/arm/mach-at91/pm_suspend.S @@ -0,0 +1,337 @@ +/* + * arch/arm/mach-at91/pm_slow_clock.S + * + * Copyright (C) 2006 Savin Zlobec + * + * AT91SAM9 support: + * Copyright (C) 2007 Anti Sullin +#include +#include +#include "pm.h" + +#define SRAMC_SELF_FRESH_ACTIVE 0x01 +#define SRAMC_SELF_FRESH_EXIT 0x00 + +pmc .req r0 +tmp1 .req r4 +tmp2 .req r5 + +/* + * Wait until master clock is ready (after switching master clock source) + */ + .macro wait_mckrdy +1: ldr tmp1, [pmc, #AT91_PMC_SR] + tst tmp1, #AT91_PMC_MCKRDY + beq 1b + .endm + +/* + * Wait until master oscillator has stabilized. + */ + .macro wait_moscrdy +1: ldr tmp1, [pmc, #AT91_PMC_SR] + tst tmp1, #AT91_PMC_MOSCS + beq 1b + .endm + +/* + * Wait until PLLA has locked. + */ + .macro wait_pllalock +1: ldr tmp1, [pmc, #AT91_PMC_SR] + tst tmp1, #AT91_PMC_LOCKA + beq 1b + .endm + +/* + * Put the processor to enter the idle state + */ + .macro at91_cpu_idle + +#if defined(CONFIG_CPU_V7) + mov tmp1, #AT91_PMC_PCK + str tmp1, [pmc, #AT91_PMC_SCDR] + + dsb + + wfi @ Wait For Interrupt +#else + mcr p15, 0, tmp1, c7, c0, 4 +#endif + + .endm + + .text + + .arm + +/* + * void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc, + * void __iomem *ramc1, int memctrl) + * @input param: + * @r0: base address of AT91_PMC + * @r1: base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS) + * @r2: base address of second SDRAM Controller or 0 if not present + * @r3: pm information + */ +ENTRY(at91_pm_suspend_in_sram) + /* Save registers on stack */ + stmfd sp!, {r4 - r12, lr} + + /* Drain write buffer */ + mov tmp1, #0 + mcr p15, 0, tmp1, c7, c10, 4 + + str r0, .pmc_base + str r1, .sramc_base + str r2, .sramc1_base + + and r0, r3, #AT91_PM_MEMTYPE_MASK + str r0, .memtype + + lsr r0, r3, #AT91_PM_MODE_OFFSET + and r0, r0, #AT91_PM_MODE_MASK + str r0, .pm_mode + + /* Active the self-refresh mode */ + mov r0, #SRAMC_SELF_FRESH_ACTIVE + bl at91_sramc_self_refresh + + ldr r0, .pm_mode + tst r0, #AT91_PM_SLOW_CLOCK + beq skip_disable_main_clock + + ldr pmc, .pmc_base + + /* Save Master clock setting */ + ldr tmp1, [pmc, #AT91_PMC_MCKR] + str tmp1, .saved_mckr + + /* + * Set the Master clock source to slow clock + */ + bic tmp1, tmp1, #AT91_PMC_CSS + str tmp1, [pmc, #AT91_PMC_MCKR] + + wait_mckrdy + + /* Save PLLA setting and disable it */ + ldr tmp1, [pmc, #AT91_CKGR_PLLAR] + str tmp1, .saved_pllar + + mov tmp1, #AT91_PMC_PLLCOUNT + orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ + str tmp1, [pmc, #AT91_CKGR_PLLAR] + + /* Turn off the main oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + bic tmp1, tmp1, #AT91_PMC_MOSCEN + orr tmp1, tmp1, #AT91_PMC_KEY + str tmp1, [pmc, #AT91_CKGR_MOR] + +skip_disable_main_clock: + ldr pmc, .pmc_base + + /* Wait for interrupt */ + at91_cpu_idle + + ldr r0, .pm_mode + tst r0, #AT91_PM_SLOW_CLOCK + beq skip_enable_main_clock + + ldr pmc, .pmc_base + + /* Turn on the main oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + orr tmp1, tmp1, #AT91_PMC_MOSCEN + orr tmp1, tmp1, #AT91_PMC_KEY + str tmp1, [pmc, #AT91_CKGR_MOR] + + wait_moscrdy + + /* Restore PLLA setting */ + ldr tmp1, .saved_pllar + str tmp1, [pmc, #AT91_CKGR_PLLAR] + + tst tmp1, #(AT91_PMC_MUL & 0xff0000) + bne 3f + tst tmp1, #(AT91_PMC_MUL & ~0xff0000) + beq 4f +3: + wait_pllalock +4: + + /* + * Restore master clock setting + */ + ldr tmp1, .saved_mckr + str tmp1, [pmc, #AT91_PMC_MCKR] + + wait_mckrdy + +skip_enable_main_clock: + /* Exit the self-refresh mode */ + mov r0, #SRAMC_SELF_FRESH_EXIT + bl at91_sramc_self_refresh + + /* Restore registers, and return */ + ldmfd sp!, {r4 - r12, pc} +ENDPROC(at91_pm_suspend_in_sram) + +/* + * void at91_sramc_self_refresh(unsigned int is_active) + * + * @input param: + * @r0: 1 - active self-refresh mode + * 0 - exit self-refresh mode + * register usage: + * @r1: memory type + * @r2: base address of the sram controller + */ + +ENTRY(at91_sramc_self_refresh) + ldr r1, .memtype + ldr r2, .sramc_base + + cmp r1, #AT91_MEMCTRL_MC + bne ddrc_sf + + /* + * at91rm9200 Memory controller + */ + + /* + * For exiting the self-refresh mode, do nothing, + * automatically exit the self-refresh mode. + */ + tst r0, #SRAMC_SELF_FRESH_ACTIVE + beq exit_sramc_sf + + /* Active SDRAM self-refresh mode */ + mov r3, #1 + str r3, [r2, #AT91RM9200_SDRAMC_SRR] + b exit_sramc_sf + +ddrc_sf: + cmp r1, #AT91_MEMCTRL_DDRSDR + bne sdramc_sf + + /* + * DDR Memory controller + */ + tst r0, #SRAMC_SELF_FRESH_ACTIVE + beq ddrc_exit_sf + + /* LPDDR1 --> force DDR2 mode during self-refresh */ + ldr r3, [r2, #AT91_DDRSDRC_MDR] + str r3, .saved_sam9_mdr + bic r3, r3, #~AT91_DDRSDRC_MD + cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR + ldreq r3, [r2, #AT91_DDRSDRC_MDR] + biceq r3, r3, #AT91_DDRSDRC_MD + orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 + streq r3, [r2, #AT91_DDRSDRC_MDR] + + /* Active DDRC self-refresh mode */ + ldr r3, [r2, #AT91_DDRSDRC_LPR] + str r3, .saved_sam9_lpr + bic r3, r3, #AT91_DDRSDRC_LPCB + orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH + str r3, [r2, #AT91_DDRSDRC_LPR] + + /* If using the 2nd ddr controller */ + ldr r2, .sramc1_base + cmp r2, #0 + beq no_2nd_ddrc + + ldr r3, [r2, #AT91_DDRSDRC_MDR] + str r3, .saved_sam9_mdr1 + bic r3, r3, #~AT91_DDRSDRC_MD + cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR + ldreq r3, [r2, #AT91_DDRSDRC_MDR] + biceq r3, r3, #AT91_DDRSDRC_MD + orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 + streq r3, [r2, #AT91_DDRSDRC_MDR] + + /* Active DDRC self-refresh mode */ + ldr r3, [r2, #AT91_DDRSDRC_LPR] + str r3, .saved_sam9_lpr1 + bic r3, r3, #AT91_DDRSDRC_LPCB + orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH + str r3, [r2, #AT91_DDRSDRC_LPR] + +no_2nd_ddrc: + b exit_sramc_sf + +ddrc_exit_sf: + /* Restore MDR in case of LPDDR1 */ + ldr r3, .saved_sam9_mdr + str r3, [r2, #AT91_DDRSDRC_MDR] + /* Restore LPR on AT91 with DDRAM */ + ldr r3, .saved_sam9_lpr + str r3, [r2, #AT91_DDRSDRC_LPR] + + /* If using the 2nd ddr controller */ + ldr r2, .sramc1_base + cmp r2, #0 + ldrne r3, .saved_sam9_mdr1 + strne r3, [r2, #AT91_DDRSDRC_MDR] + ldrne r3, .saved_sam9_lpr1 + strne r3, [r2, #AT91_DDRSDRC_LPR] + + b exit_sramc_sf + + /* + * SDRAMC Memory controller + */ +sdramc_sf: + tst r0, #SRAMC_SELF_FRESH_ACTIVE + beq sdramc_exit_sf + + /* Active SDRAMC self-refresh mode */ + ldr r3, [r2, #AT91_SDRAMC_LPR] + str r3, .saved_sam9_lpr + bic r3, r3, #AT91_SDRAMC_LPCB + orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH + str r3, [r2, #AT91_SDRAMC_LPR] + +sdramc_exit_sf: + ldr r3, .saved_sam9_lpr + str r3, [r2, #AT91_SDRAMC_LPR] + +exit_sramc_sf: + mov pc, lr +ENDPROC(at91_sramc_self_refresh) + +.pmc_base: + .word 0 +.sramc_base: + .word 0 +.sramc1_base: + .word 0 +.memtype: + .word 0 +.pm_mode: + .word 0 +.saved_mckr: + .word 0 +.saved_pllar: + .word 0 +.saved_sam9_lpr: + .word 0 +.saved_sam9_lpr1: + .word 0 +.saved_sam9_mdr: + .word 0 +.saved_sam9_mdr1: + .word 0 + +ENTRY(at91_pm_suspend_in_sram_sz) + .word .-at91_pm_suspend_in_sram diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c index 03dcb441f3d24662c3e7b00b8eea136426723a86..41d829d8e7d51045cc2fc38758302e13fd55b554 100644 --- a/arch/arm/mach-at91/sama5.c +++ b/arch/arm/mach-at91/sama5.c @@ -7,48 +7,48 @@ * Licensed under GPLv2 or later. */ -#include -#include -#include -#include -#include #include -#include #include -#include -#include -#include -#include - -#include -#include #include #include -#include +#include #include "generic.h" +#include "soc.h" -static int ksz8081_phy_fixup(struct phy_device *phy) -{ - int value; - - value = phy_read(phy, 0x16); - value &= ~0x20; - phy_write(phy, 0x16, value); - - return 0; -} +static const struct at91_soc sama5_socs[] = { + AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH, + "sama5d31", "sama5d3"), + AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH, + "sama5d33", "sama5d3"), + AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH, + "sama5d34", "sama5d3"), + AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH, + "sama5d35", "sama5d3"), + AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH, + "sama5d36", "sama5d3"), + AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH, + "sama5d41", "sama5d4"), + AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH, + "sama5d42", "sama5d4"), + AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH, + "sama5d43", "sama5d4"), + AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH, + "sama5d44", "sama5d4"), + { /* sentinel */ }, +}; static void __init sama5_dt_device_init(void) { - if (of_machine_is_compatible("atmel,sama5d4ek") && - IS_ENABLED(CONFIG_PHYLIB)) { - phy_register_fixup_for_id("fc028000.etherne:00", - ksz8081_phy_fixup); - } + struct soc_device *soc; + struct device *soc_dev = NULL; - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + soc = at91_soc_init(sama5_socs); + if (soc != NULL) + soc_dev = soc_device_to_device(soc); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev); at91sam9x5_pm_init(); } @@ -59,44 +59,10 @@ static const char *sama5_dt_board_compat[] __initconst = { DT_MACHINE_START(sama5_dt, "Atmel SAMA5") /* Maintainer: Atmel */ - .map_io = at91_map_io, .init_machine = sama5_dt_device_init, .dt_compat = sama5_dt_board_compat, MACHINE_END -static struct map_desc at91_io_desc[] __initdata = { - { - .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC), - .pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC), - .length = SZ_512, - .type = MT_DEVICE, - }, - { - .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC), - .pfn = __phys_to_pfn(SAMA5D4_BASE_PMC), - .length = SZ_512, - .type = MT_DEVICE, - }, - { /* On sama5d4, we use USART3 as serial console */ - .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3), - .pfn = __phys_to_pfn(SAMA5D4_BASE_USART3), - .length = SZ_256, - .type = MT_DEVICE, - }, - { /* A bunch of peripheral with fine grained IO space */ - .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2), - .pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2), - .length = SZ_2K, - .type = MT_DEVICE, - }, -}; - -static void __init sama5_alt_map_io(void) -{ - at91_alt_map_io(); - iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc)); -} - static const char *sama5_alt_dt_board_compat[] __initconst = { "atmel,sama5d4", NULL @@ -104,7 +70,6 @@ static const char *sama5_alt_dt_board_compat[] __initconst = { DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5") /* Maintainer: Atmel */ - .map_io = sama5_alt_map_io, .init_machine = sama5_dt_device_init, .dt_compat = sama5_alt_dt_board_compat, .l2c_aux_mask = ~0UL, diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c deleted file mode 100644 index 4e58bc90ed218291b30bfe44b4a5969a80134a40..0000000000000000000000000000000000000000 --- a/arch/arm/mach-at91/setup.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * Copyright (C) 2007 Atmel Corporation. - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - * - * Under GPLv2 - */ - -#define pr_fmt(fmt) "AT91: " fmt - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "generic.h" -#include "pm.h" - -struct at91_socinfo at91_soc_initdata; -EXPORT_SYMBOL(at91_soc_initdata); - -static struct map_desc at91_io_desc __initdata __maybe_unused = { - .virtual = (unsigned long)AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_16K, - .type = MT_DEVICE, -}; - -static struct map_desc at91_alt_io_desc __initdata __maybe_unused = { - .virtual = (unsigned long)AT91_ALT_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_ALT_BASE_SYS), - .length = 24 * SZ_1K, - .type = MT_DEVICE, -}; - -static void __init soc_detect(u32 dbgu_base) -{ - u32 cidr, socid; - - cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR); - socid = cidr & ~AT91_CIDR_VERSION; - - switch (socid) { - case ARCH_ID_AT91RM9200: - at91_soc_initdata.type = AT91_SOC_RM9200; - if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN) - at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; - break; - - case ARCH_ID_AT91SAM9260: - at91_soc_initdata.type = AT91_SOC_SAM9260; - at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; - break; - - case ARCH_ID_AT91SAM9261: - at91_soc_initdata.type = AT91_SOC_SAM9261; - at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; - break; - - case ARCH_ID_AT91SAM9263: - at91_soc_initdata.type = AT91_SOC_SAM9263; - at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; - break; - - case ARCH_ID_AT91SAM9G20: - at91_soc_initdata.type = AT91_SOC_SAM9G20; - at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; - break; - - case ARCH_ID_AT91SAM9G45: - at91_soc_initdata.type = AT91_SOC_SAM9G45; - if (cidr == ARCH_ID_AT91SAM9G45ES) - at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES; - break; - - case ARCH_ID_AT91SAM9RL64: - at91_soc_initdata.type = AT91_SOC_SAM9RL; - at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; - break; - - case ARCH_ID_AT91SAM9X5: - at91_soc_initdata.type = AT91_SOC_SAM9X5; - break; - - case ARCH_ID_AT91SAM9N12: - at91_soc_initdata.type = AT91_SOC_SAM9N12; - break; - - case ARCH_ID_SAMA5: - at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID); - if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) { - at91_soc_initdata.type = AT91_SOC_SAMA5D3; - } - break; - } - - /* at91sam9g10 */ - if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { - at91_soc_initdata.type = AT91_SOC_SAM9G10; - at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; - } - /* at91sam9xe */ - else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) { - at91_soc_initdata.type = AT91_SOC_SAM9260; - at91_soc_initdata.subtype = AT91_SOC_SAM9XE; - } - - if (!at91_soc_is_detected()) - return; - - at91_soc_initdata.cidr = cidr; - - /* sub version of soc */ - if (!at91_soc_initdata.exid) - at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID); - - if (at91_soc_initdata.type == AT91_SOC_SAM9G45) { - switch (at91_soc_initdata.exid) { - case ARCH_EXID_AT91SAM9M10: - at91_soc_initdata.subtype = AT91_SOC_SAM9M10; - break; - case ARCH_EXID_AT91SAM9G46: - at91_soc_initdata.subtype = AT91_SOC_SAM9G46; - break; - case ARCH_EXID_AT91SAM9M11: - at91_soc_initdata.subtype = AT91_SOC_SAM9M11; - break; - } - } - - if (at91_soc_initdata.type == AT91_SOC_SAM9X5) { - switch (at91_soc_initdata.exid) { - case ARCH_EXID_AT91SAM9G15: - at91_soc_initdata.subtype = AT91_SOC_SAM9G15; - break; - case ARCH_EXID_AT91SAM9G35: - at91_soc_initdata.subtype = AT91_SOC_SAM9G35; - break; - case ARCH_EXID_AT91SAM9X35: - at91_soc_initdata.subtype = AT91_SOC_SAM9X35; - break; - case ARCH_EXID_AT91SAM9G25: - at91_soc_initdata.subtype = AT91_SOC_SAM9G25; - break; - case ARCH_EXID_AT91SAM9X25: - at91_soc_initdata.subtype = AT91_SOC_SAM9X25; - break; - } - } - - if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) { - switch (at91_soc_initdata.exid) { - case ARCH_EXID_SAMA5D31: - at91_soc_initdata.subtype = AT91_SOC_SAMA5D31; - break; - case ARCH_EXID_SAMA5D33: - at91_soc_initdata.subtype = AT91_SOC_SAMA5D33; - break; - case ARCH_EXID_SAMA5D34: - at91_soc_initdata.subtype = AT91_SOC_SAMA5D34; - break; - case ARCH_EXID_SAMA5D35: - at91_soc_initdata.subtype = AT91_SOC_SAMA5D35; - break; - case ARCH_EXID_SAMA5D36: - at91_soc_initdata.subtype = AT91_SOC_SAMA5D36; - break; - } - } -} - -static void __init alt_soc_detect(u32 dbgu_base) -{ - u32 cidr, socid; - - /* SoC ID */ - cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR); - socid = cidr & ~AT91_CIDR_VERSION; - - switch (socid) { - case ARCH_ID_SAMA5: - at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID); - if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) { - at91_soc_initdata.type = AT91_SOC_SAMA5D3; - } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) { - at91_soc_initdata.type = AT91_SOC_SAMA5D4; - } - break; - } - - if (!at91_soc_is_detected()) - return; - - at91_soc_initdata.cidr = cidr; - - /* sub version of soc */ - if (!at91_soc_initdata.exid) - at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID); - - if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) { - switch (at91_soc_initdata.exid) { - case ARCH_EXID_SAMA5D41: - at91_soc_initdata.subtype = AT91_SOC_SAMA5D41; - break; - case ARCH_EXID_SAMA5D42: - at91_soc_initdata.subtype = AT91_SOC_SAMA5D42; - break; - case ARCH_EXID_SAMA5D43: - at91_soc_initdata.subtype = AT91_SOC_SAMA5D43; - break; - case ARCH_EXID_SAMA5D44: - at91_soc_initdata.subtype = AT91_SOC_SAMA5D44; - break; - } - } -} - -static const char *soc_name[] = { - [AT91_SOC_RM9200] = "at91rm9200", - [AT91_SOC_SAM9260] = "at91sam9260", - [AT91_SOC_SAM9261] = "at91sam9261", - [AT91_SOC_SAM9263] = "at91sam9263", - [AT91_SOC_SAM9G10] = "at91sam9g10", - [AT91_SOC_SAM9G20] = "at91sam9g20", - [AT91_SOC_SAM9G45] = "at91sam9g45", - [AT91_SOC_SAM9RL] = "at91sam9rl", - [AT91_SOC_SAM9X5] = "at91sam9x5", - [AT91_SOC_SAM9N12] = "at91sam9n12", - [AT91_SOC_SAMA5D3] = "sama5d3", - [AT91_SOC_SAMA5D4] = "sama5d4", - [AT91_SOC_UNKNOWN] = "Unknown", -}; - -const char *at91_get_soc_type(struct at91_socinfo *c) -{ - return soc_name[c->type]; -} -EXPORT_SYMBOL(at91_get_soc_type); - -static const char *soc_subtype_name[] = { - [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA", - [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP", - [AT91_SOC_SAM9XE] = "at91sam9xe", - [AT91_SOC_SAM9G45ES] = "at91sam9g45es", - [AT91_SOC_SAM9M10] = "at91sam9m10", - [AT91_SOC_SAM9G46] = "at91sam9g46", - [AT91_SOC_SAM9M11] = "at91sam9m11", - [AT91_SOC_SAM9G15] = "at91sam9g15", - [AT91_SOC_SAM9G35] = "at91sam9g35", - [AT91_SOC_SAM9X35] = "at91sam9x35", - [AT91_SOC_SAM9G25] = "at91sam9g25", - [AT91_SOC_SAM9X25] = "at91sam9x25", - [AT91_SOC_SAMA5D31] = "sama5d31", - [AT91_SOC_SAMA5D33] = "sama5d33", - [AT91_SOC_SAMA5D34] = "sama5d34", - [AT91_SOC_SAMA5D35] = "sama5d35", - [AT91_SOC_SAMA5D36] = "sama5d36", - [AT91_SOC_SAMA5D41] = "sama5d41", - [AT91_SOC_SAMA5D42] = "sama5d42", - [AT91_SOC_SAMA5D43] = "sama5d43", - [AT91_SOC_SAMA5D44] = "sama5d44", - [AT91_SOC_SUBTYPE_NONE] = "None", - [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown", -}; - -const char *at91_get_soc_subtype(struct at91_socinfo *c) -{ - return soc_subtype_name[c->subtype]; -} -EXPORT_SYMBOL(at91_get_soc_subtype); - -void __init at91_map_io(void) -{ - /* Map peripherals */ - iotable_init(&at91_io_desc, 1); - - at91_soc_initdata.type = AT91_SOC_UNKNOWN; - at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN; - - soc_detect(AT91_BASE_DBGU0); - if (!at91_soc_is_detected()) - soc_detect(AT91_BASE_DBGU1); - - if (!at91_soc_is_detected()) - panic(pr_fmt("Impossible to detect the SOC type")); - - pr_info("Detected soc type: %s\n", - at91_get_soc_type(&at91_soc_initdata)); - if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE) - pr_info("Detected soc subtype: %s\n", - at91_get_soc_subtype(&at91_soc_initdata)); -} - -void __init at91_alt_map_io(void) -{ - /* Map peripherals */ - iotable_init(&at91_alt_io_desc, 1); - - at91_soc_initdata.type = AT91_SOC_UNKNOWN; - at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN; - - alt_soc_detect(AT91_BASE_DBGU2); - if (!at91_soc_is_detected()) - panic("AT91: Impossible to detect the SOC type"); - - pr_info("AT91: Detected soc type: %s\n", - at91_get_soc_type(&at91_soc_initdata)); - if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE) - pr_info("AT91: Detected soc subtype: %s\n", - at91_get_soc_subtype(&at91_soc_initdata)); -} - -void __iomem *at91_matrix_base; -EXPORT_SYMBOL_GPL(at91_matrix_base); - -void __init at91_ioremap_matrix(u32 base_addr) -{ - at91_matrix_base = ioremap(base_addr, 512); - if (!at91_matrix_base) - panic(pr_fmt("Impossible to ioremap at91_matrix_base\n")); -} diff --git a/arch/arm/mach-at91/soc.c b/arch/arm/mach-at91/soc.c new file mode 100644 index 0000000000000000000000000000000000000000..54343ffa3e53352ba142c7ed1894f00f37193bc3 --- /dev/null +++ b/arch/arm/mach-at91/soc.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2015 Atmel + * + * Alexandre Belloni +#include +#include +#include +#include +#include + +#include "soc.h" + +#define AT91_DBGU_CIDR 0x40 +#define AT91_DBGU_CIDR_VERSION(x) ((x) & 0x1f) +#define AT91_DBGU_CIDR_EXT BIT(31) +#define AT91_DBGU_CIDR_MATCH_MASK 0x7fffffe0 +#define AT91_DBGU_EXID 0x44 + +struct soc_device * __init at91_soc_init(const struct at91_soc *socs) +{ + struct soc_device_attribute *soc_dev_attr; + const struct at91_soc *soc; + struct soc_device *soc_dev; + struct device_node *np; + void __iomem *regs; + u32 cidr, exid; + + np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu"); + if (!np) + np = of_find_compatible_node(NULL, NULL, + "atmel,at91sam9260-dbgu"); + + if (!np) { + pr_warn("Could not find DBGU node"); + return NULL; + } + + regs = of_iomap(np, 0); + of_node_put(np); + + if (!regs) { + pr_warn("Could not map DBGU iomem range"); + return NULL; + } + + cidr = readl(regs + AT91_DBGU_CIDR); + exid = readl(regs + AT91_DBGU_EXID); + + iounmap(regs); + + for (soc = socs; soc->name; soc++) { + if (soc->cidr_match != (cidr & AT91_DBGU_CIDR_MATCH_MASK)) + continue; + + if (!(cidr & AT91_DBGU_CIDR_EXT) || soc->exid_match == exid) + break; + } + + if (!soc->name) { + pr_warn("Could not find matching SoC description\n"); + return NULL; + } + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return NULL; + + soc_dev_attr->family = soc->family; + soc_dev_attr->soc_id = soc->name; + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", + AT91_DBGU_CIDR_VERSION(cidr)); + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->revision); + kfree(soc_dev_attr); + pr_warn("Could not register SoC device\n"); + return NULL; + } + + if (soc->family) + pr_info("Detected SoC family: %s\n", soc->family); + pr_info("Detected SoC: %s, revision %X\n", soc->name, + AT91_DBGU_CIDR_VERSION(cidr)); + + return soc_dev; +} diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h new file mode 100644 index 0000000000000000000000000000000000000000..be23c400596b4eff8ac68600a208a4b3d6b5a55b --- /dev/null +++ b/arch/arm/mach-at91/soc.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2015 Atmel + * + * Boris Brezillon + +struct at91_soc { + u32 cidr_match; + u32 exid_match; + const char *name; + const char *family; +}; + +#define AT91_SOC(__cidr, __exid, __name, __family) \ + { \ + .cidr_match = (__cidr), \ + .exid_match = (__exid), \ + .name = (__name), \ + .family = (__family), \ + } + +struct soc_device * __init +at91_soc_init(const struct at91_soc *socs); + +#define AT91RM9200_CIDR_MATCH 0x09290780 + +#define AT91SAM9260_CIDR_MATCH 0x019803a0 +#define AT91SAM9261_CIDR_MATCH 0x019703a0 +#define AT91SAM9263_CIDR_MATCH 0x019607a0 +#define AT91SAM9G20_CIDR_MATCH 0x019905a0 +#define AT91SAM9RL64_CIDR_MATCH 0x019b03a0 +#define AT91SAM9G45_CIDR_MATCH 0x019b05a0 +#define AT91SAM9X5_CIDR_MATCH 0x019a05a0 +#define AT91SAM9N12_CIDR_MATCH 0x019a07a0 + +#define AT91SAM9M11_EXID_MATCH 0x00000001 +#define AT91SAM9M10_EXID_MATCH 0x00000002 +#define AT91SAM9G46_EXID_MATCH 0x00000003 +#define AT91SAM9G45_EXID_MATCH 0x00000004 + +#define AT91SAM9G15_EXID_MATCH 0x00000000 +#define AT91SAM9G35_EXID_MATCH 0x00000001 +#define AT91SAM9X35_EXID_MATCH 0x00000002 +#define AT91SAM9G25_EXID_MATCH 0x00000003 +#define AT91SAM9X25_EXID_MATCH 0x00000004 + +#define AT91SAM9CN12_EXID_MATCH 0x00000005 +#define AT91SAM9N12_EXID_MATCH 0x00000006 +#define AT91SAM9CN11_EXID_MATCH 0x00000009 + +#define AT91SAM9XE128_CIDR_MATCH 0x329973a0 +#define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 +#define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 + +#define SAMA5D3_CIDR_MATCH 0x0a5c07c0 +#define SAMA5D31_EXID_MATCH 0x00444300 +#define SAMA5D33_EXID_MATCH 0x00414300 +#define SAMA5D34_EXID_MATCH 0x00414301 +#define SAMA5D35_EXID_MATCH 0x00584300 +#define SAMA5D36_EXID_MATCH 0x00004301 + +#define SAMA5D4_CIDR_MATCH 0x0a5c07c0 +#define SAMA5D41_EXID_MATCH 0x00000001 +#define SAMA5D42_EXID_MATCH 0x00000002 +#define SAMA5D43_EXID_MATCH 0x00000003 +#define SAMA5D44_EXID_MATCH 0x00000004 + +#endif /* __AT91_SOC_H */ diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c index 30dc58be51b8e70f49074ee47523e534d6676337..7ae894c7849b7cde3bc61b952868652b0fc29c22 100644 --- a/arch/arm/mach-bcm/bcm_cygnus.c +++ b/arch/arm/mach-bcm/bcm_cygnus.c @@ -13,7 +13,7 @@ #include -static const char const *bcm_cygnus_dt_compat[] = { +static const char * const bcm_cygnus_dt_compat[] __initconst = { "brcm,cygnus", NULL, }; diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c index fb38c726e9877d5472608cedf237913cf0efa23f..f46b78dd613655e0b2ec2acdfea7f9ccdeee710d 100644 --- a/arch/arm/mach-cns3xxx/pm.c +++ b/arch/arm/mach-cns3xxx/pm.c @@ -73,7 +73,6 @@ static void cns3xxx_pwr_soft_rst_force(unsigned int block) __raw_writel(reg, PM_SOFT_RST_REG); } -EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force); void cns3xxx_pwr_soft_rst(unsigned int block) { diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index cd30f6f5f2ff15723a2abae07b471b03f65f9b11..dd8f5312b2c0e5d15e38b42dbaaee88a4718ce61 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -200,17 +200,6 @@ config DA850_UI_SD_VIDEO_PORT endchoice -config DA850_WL12XX - bool "AM18x wl1271 daughter board" - depends on MACH_DAVINCI_DA850_EVM - help - The wl1271 daughter card for AM18x EVMs is a combo wireless - connectivity add-on card, based on the LS Research TiWi module with - Texas Instruments' wl1271 solution. - Say Y if you want to use a wl1271 expansion card connected to the - AM18x EVM. - - config MACH_MITYOMAPL138 bool "Critical Link MityDSP-L138/MityARM-1808 SoM" depends on ARCH_DAVINCI_DA850 diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h index d9b2acd12393ab0e8f4968403ce5ad901553d146..1128e1d8e4b46690f3af8909c5e5d6829d642219 100644 --- a/arch/arm/mach-davinci/asp.h +++ b/arch/arm/mach-davinci/asp.h @@ -21,6 +21,9 @@ /* Bases of da830 McASP1 register banks */ #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 +/* Bases of da830 McASP2 register banks */ +#define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000 + /* EDMA channels of dm644x and dm355 */ #define DAVINCI_DMA_ASP0_TX 2 #define DAVINCI_DMA_ASP0_RX 3 @@ -40,6 +43,10 @@ #define DAVINCI_DA830_DMA_MCASP1_AREVT 2 #define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 +/* EDMA channels of da830 McASP2 */ +#define DAVINCI_DA830_DMA_MCASP2_AREVT 4 +#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5 + /* Interrupts */ #define DAVINCI_ASP0_RX_INT IRQ_MBRINT #define DAVINCI_ASP0_TX_INT IRQ_MBXINT diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 6b5a97da9fe39da65df47b5c9bbe8fd1359666d8..1ed545cc2b83452954cc4a2217ac1be324237775 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include @@ -60,9 +59,6 @@ #define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) #define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) -#define DA850_WLAN_EN GPIO_TO_PIN(6, 9) -#define DA850_WLAN_IRQ GPIO_TO_PIN(6, 10) - #define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) static struct mtd_partition da850evm_spiflash_part[] = { @@ -1343,109 +1339,6 @@ static __init void da850_vpif_init(void) static __init void da850_vpif_init(void) {} #endif -#ifdef CONFIG_DA850_WL12XX - -static void wl12xx_set_power(int index, bool power_on) -{ - static bool power_state; - - pr_debug("Powering %s wl12xx", power_on ? "on" : "off"); - - if (power_on == power_state) - return; - power_state = power_on; - - if (power_on) { - /* Power up sequence required for wl127x devices */ - gpio_set_value(DA850_WLAN_EN, 1); - usleep_range(15000, 15000); - gpio_set_value(DA850_WLAN_EN, 0); - usleep_range(1000, 1000); - gpio_set_value(DA850_WLAN_EN, 1); - msleep(70); - } else { - gpio_set_value(DA850_WLAN_EN, 0); - } -} - -static struct davinci_mmc_config da850_wl12xx_mmc_config = { - .set_power = wl12xx_set_power, - .wires = 4, - .max_freq = 25000000, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE | - MMC_CAP_POWER_OFF_CARD, -}; - -static const short da850_wl12xx_pins[] __initconst = { - DA850_MMCSD1_DAT_0, DA850_MMCSD1_DAT_1, DA850_MMCSD1_DAT_2, - DA850_MMCSD1_DAT_3, DA850_MMCSD1_CLK, DA850_MMCSD1_CMD, - DA850_GPIO6_9, DA850_GPIO6_10, - -1 -}; - -static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = { - .irq = -1, - .board_ref_clock = WL12XX_REFCLOCK_38, - .platform_quirks = WL12XX_PLATFORM_QUIRK_EDGE_IRQ, -}; - -static __init int da850_wl12xx_init(void) -{ - int ret; - - ret = davinci_cfg_reg_list(da850_wl12xx_pins); - if (ret) { - pr_err("wl12xx/mmc mux setup failed: %d\n", ret); - goto exit; - } - - ret = da850_register_mmcsd1(&da850_wl12xx_mmc_config); - if (ret) { - pr_err("wl12xx/mmc registration failed: %d\n", ret); - goto exit; - } - - ret = gpio_request_one(DA850_WLAN_EN, GPIOF_OUT_INIT_LOW, "wl12xx_en"); - if (ret) { - pr_err("Could not request wl12xx enable gpio: %d\n", ret); - goto exit; - } - - ret = gpio_request_one(DA850_WLAN_IRQ, GPIOF_IN, "wl12xx_irq"); - if (ret) { - pr_err("Could not request wl12xx irq gpio: %d\n", ret); - goto free_wlan_en; - } - - da850_wl12xx_wlan_data.irq = gpio_to_irq(DA850_WLAN_IRQ); - - ret = wl12xx_set_platform_data(&da850_wl12xx_wlan_data); - if (ret) { - pr_err("Could not set wl12xx data: %d\n", ret); - goto free_wlan_irq; - } - - return 0; - -free_wlan_irq: - gpio_free(DA850_WLAN_IRQ); - -free_wlan_en: - gpio_free(DA850_WLAN_EN); - -exit: - return ret; -} - -#else /* CONFIG_DA850_WL12XX */ - -static __init int da850_wl12xx_init(void) -{ - return 0; -} - -#endif /* CONFIG_DA850_WL12XX */ - #define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000) static __init void da850_evm_init(void) @@ -1502,11 +1395,6 @@ static __init void da850_evm_init(void) if (ret) pr_warn("%s: MMCSD0 registration failed: %d\n", __func__, ret); - - ret = da850_wl12xx_init(); - if (ret) - pr_warn("%s: WL12xx initialization failed: %d\n", - __func__, ret); } davinci_serial_init(da8xx_serial_device); diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index b85b781b05fdf7d89d7a3c256727ea9024b6d0d8..ddfdd820e6f2b99f6bfa80a51a287255794d74d5 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -463,16 +463,23 @@ static struct resource da830_mcasp1_resources[] = { }, /* TX event */ { + .name = "tx", .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, .flags = IORESOURCE_DMA, }, /* RX event */ { + .name = "rx", .start = DAVINCI_DA830_DMA_MCASP1_AREVT, .end = DAVINCI_DA830_DMA_MCASP1_AREVT, .flags = IORESOURCE_DMA, }, + { + .name = "common", + .start = IRQ_DA8XX_MCASPINT, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device da830_mcasp1_device = { @@ -482,6 +489,41 @@ static struct platform_device da830_mcasp1_device = { .resource = da830_mcasp1_resources, }; +static struct resource da830_mcasp2_resources[] = { + { + .name = "mpu", + .start = DAVINCI_DA830_MCASP2_REG_BASE, + .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1, + .flags = IORESOURCE_MEM, + }, + /* TX event */ + { + .name = "tx", + .start = DAVINCI_DA830_DMA_MCASP2_AXEVT, + .end = DAVINCI_DA830_DMA_MCASP2_AXEVT, + .flags = IORESOURCE_DMA, + }, + /* RX event */ + { + .name = "rx", + .start = DAVINCI_DA830_DMA_MCASP2_AREVT, + .end = DAVINCI_DA830_DMA_MCASP2_AREVT, + .flags = IORESOURCE_DMA, + }, + { + .name = "common", + .start = IRQ_DA8XX_MCASPINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da830_mcasp2_device = { + .name = "davinci-mcasp", + .id = 2, + .num_resources = ARRAY_SIZE(da830_mcasp2_resources), + .resource = da830_mcasp2_resources, +}; + static struct resource da850_mcasp_resources[] = { { .name = "mpu", @@ -491,16 +533,23 @@ static struct resource da850_mcasp_resources[] = { }, /* TX event */ { + .name = "tx", .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, .flags = IORESOURCE_DMA, }, /* RX event */ { + .name = "rx", .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, .flags = IORESOURCE_DMA, }, + { + .name = "common", + .start = IRQ_DA8XX_MCASPINT, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device da850_mcasp_device = { @@ -512,14 +561,31 @@ static struct platform_device da850_mcasp_device = { void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) { - /* DA830/OMAP-L137 has 3 instances of McASP */ - if (cpu_is_davinci_da830() && id == 1) { - da830_mcasp1_device.dev.platform_data = pdata; - platform_device_register(&da830_mcasp1_device); - } else if (cpu_is_davinci_da850()) { - da850_mcasp_device.dev.platform_data = pdata; - platform_device_register(&da850_mcasp_device); + struct platform_device *pdev; + + switch (id) { + case 0: + /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */ + pdev = &da850_mcasp_device; + break; + case 1: + /* Valid for DA830/OMAP-L137 only */ + if (!cpu_is_davinci_da830()) + return; + pdev = &da830_mcasp1_device; + break; + case 2: + /* Valid for DA830/OMAP-L137 only */ + if (!cpu_is_davinci_da830()) + return; + pdev = &da830_mcasp2_device; + break; + default: + return; } + + pdev->dev.platform_data = pdata; + platform_device_register(pdev); } static struct resource da8xx_pruss_resources[] = { diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 6c3bbea7d77d8f8f2432ec9321936cedf2e942f5..3f842bb266d6ebe6226209433dca0b805398afaa 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { [IRQ_DM646X_EMACMISCINT] = 7, [IRQ_DM646X_MCASP0TXINT] = 7, [IRQ_DM646X_MCASP0RXINT] = 7, - [IRQ_AEMIFINT] = 7, [IRQ_DM646X_RESERVED_3] = 7, [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ [IRQ_TINT0_TINT34] = 7, /* clocksource */ @@ -610,19 +609,31 @@ static struct resource dm646x_mcasp0_resources[] = { .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, .flags = IORESOURCE_MEM, }, - /* first TX, then RX */ { + .name = "tx", .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, .flags = IORESOURCE_DMA, }, { + .name = "rx", .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0, .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0, .flags = IORESOURCE_DMA, }, + { + .name = "tx", + .start = IRQ_DM646X_MCASP0TXINT, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = IRQ_DM646X_MCASP0RXINT, + .flags = IORESOURCE_IRQ, + }, }; +/* DIT mode only, rx is not supported */ static struct resource dm646x_mcasp1_resources[] = { { .name = "mpu", @@ -630,17 +641,16 @@ static struct resource dm646x_mcasp1_resources[] = { .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, .flags = IORESOURCE_MEM, }, - /* DIT mode, only TX event */ { + .name = "tx", .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, .flags = IORESOURCE_DMA, }, - /* DIT mode, dummy entry */ { - .start = -1, - .end = -1, - .flags = IORESOURCE_DMA, + .name = "tx", + .start = IRQ_DM646X_MCASP1TXINT, + .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index 354af71798dcd4e09206ae6e82bfa862b4ccb0a1..edb2ca62321ae141ed6e5a9afe910e88b423bbe9 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -129,8 +129,8 @@ #define IRQ_DM646X_EMACMISCINT 27 #define IRQ_DM646X_MCASP0TXINT 28 #define IRQ_DM646X_MCASP0RXINT 29 +#define IRQ_DM646X_MCASP1TXINT 30 #define IRQ_DM646X_RESERVED_3 31 -#define IRQ_DM646X_MCASP1TXINT 32 #define IRQ_DM646X_VLQINT 38 #define IRQ_DM646X_UARTINT2 42 #define IRQ_DM646X_SPINT0 43 diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 603820e5aba79bc17bab7acd56f87a69af087c45..81064cd61a0a9e72536d6dd6df56555bae352d61 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -123,7 +123,7 @@ config SOC_EXYNOS5800 config EXYNOS5420_MCPM bool "Exynos5420 Multi-Cluster PM support" depends on MCPM && SOC_EXYNOS5420 - select ARM_CCI + select ARM_CCI400_PORT_CTRL select ARM_CPU_SUSPEND help This is needed to provide CPU and cluster power management diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index f70eca7ee705fd26490d3ce7bbdc1988cbdf8752..5f5cd562c593ef5f6a9224254c146e7d3d0136a3 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -126,6 +126,12 @@ enum { void exynos_firmware_init(void); +/* CPU BOOT mode flag for Exynos3250 SoC bootloader */ +#define C2_STATE (1 << 3) + +void exynos_set_boot_flag(unsigned int cpu, unsigned int mode); +void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode); + extern u32 exynos_get_eint_wake_mask(void); #ifdef CONFIG_PM_SLEEP @@ -153,6 +159,8 @@ extern void exynos_enter_aftr(void); extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data; +extern void exynos_set_delayed_reset_assertion(bool enable); + extern void s5p_init_cpu(void __iomem *cpuid_addr); extern unsigned int samsung_rev(void); extern void __iomem *cpu_boot_reg_base(void); diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index f44c2e05c82e36ae3598ebf7ffe60e54a14235cc..5917a30eee33f286c80708dfb84cdd610bd2dd9d 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -166,6 +166,33 @@ static void __init exynos_init_io(void) exynos_map_io(); } +/* + * Set or clear the USE_DELAYED_RESET_ASSERTION option. Used by smp code + * and suspend. + * + * This is necessary only on Exynos4 SoCs. When system is running + * USE_DELAYED_RESET_ASSERTION should be set so the ARM CLK clock down + * feature could properly detect global idle state when secondary CPU is + * powered down. + * + * However this should not be set when such system is going into suspend. + */ +void exynos_set_delayed_reset_assertion(bool enable) +{ + if (of_machine_is_compatible("samsung,exynos4")) { + unsigned int tmp, core_id; + + for (core_id = 0; core_id < num_possible_cpus(); core_id++) { + tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id)); + if (enable) + tmp |= S5P_USE_DELAYED_RESET_ASSERTION; + else + tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION); + pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id)); + } + } +} + /* * Apparently, these SoCs are not able to wake-up from suspend using * the PMU. Too bad. Should they suddenly become capable of such a @@ -206,7 +233,7 @@ static void __init exynos_dt_machine_init(void) if (!IS_ENABLED(CONFIG_SMP)) exynos_sysram_init(); -#ifdef CONFIG_ARM_EXYNOS_CPUIDLE +#if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE) if (of_machine_is_compatible("samsung,exynos4210")) exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data; #endif @@ -214,6 +241,7 @@ static void __init exynos_dt_machine_init(void) of_machine_is_compatible("samsung,exynos4212") || (of_machine_is_compatible("samsung,exynos4412") && of_machine_is_compatible("samsung,trats2")) || + of_machine_is_compatible("samsung,exynos3250") || of_machine_is_compatible("samsung,exynos5250")) platform_device_register(&exynos_cpuidle); diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 4791a3cc00f9d40e71c474d6130c02697ebcd090..1bd35763f12ec04d712ace47f0f88bd2f9c95c89 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -48,7 +48,13 @@ static int exynos_do_idle(unsigned long mode) __raw_writel(virt_to_phys(exynos_cpu_resume_ns), sysram_ns_base_addr + 0x24); __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20); - exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0); + if (soc_is_exynos3250()) { + exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE, + SMC_POWERSTATE_IDLE, 0); + exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER, + SMC_POWERSTATE_IDLE, 0); + } else + exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0); break; case FW_DO_IDLE_SLEEP: exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); @@ -206,3 +212,28 @@ void __init exynos_firmware_init(void) outer_cache.configure = exynos_l2_configure; } } + +#define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28) +#define BOOT_MODE_MASK 0x1f + +void exynos_set_boot_flag(unsigned int cpu, unsigned int mode) +{ + unsigned int tmp; + + tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); + + if (mode & BOOT_MODE_MASK) + tmp &= ~BOOT_MODE_MASK; + + tmp |= mode; + __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); +} + +void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode) +{ + unsigned int tmp; + + tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); + tmp &= ~mode; + __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); +} diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index b0d3c2e876fbe9227d651b8c2bcc86de22fc0fc7..9bdf54795f05de26283881729a4427bd781ea2eb 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -61,25 +61,7 @@ static void __iomem *ns_sram_base_addr; : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ "r9", "r10", "lr", "memory") -/* - * We can't use regular spinlocks. In the switcher case, it is possible - * for an outbound CPU to call power_down() after its inbound counterpart - * is already live using the same logical CPU number which trips lockdep - * debugging. - */ -static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED; -static int -cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS]; - -#define exynos_cluster_usecnt(cluster) \ - (cpu_use_count[0][cluster] + \ - cpu_use_count[1][cluster] + \ - cpu_use_count[2][cluster] + \ - cpu_use_count[3][cluster]) - -#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster) - -static int exynos_power_up(unsigned int cpu, unsigned int cluster) +static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) { unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); @@ -88,127 +70,65 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster) cluster >= EXYNOS5420_NR_CLUSTERS) return -EINVAL; - /* - * Since this is called with IRQs enabled, and no arch_spin_lock_irq - * variant exists, we need to disable IRQs manually here. - */ - local_irq_disable(); - arch_spin_lock(&exynos_mcpm_lock); - - cpu_use_count[cpu][cluster]++; - if (cpu_use_count[cpu][cluster] == 1) { - bool was_cluster_down = - (exynos_cluster_usecnt(cluster) == 1); - - /* - * Turn on the cluster (L2/COMMON) and then power on the - * cores. - */ - if (was_cluster_down) - exynos_cluster_power_up(cluster); - - exynos_cpu_power_up(cpunr); - } else if (cpu_use_count[cpu][cluster] != 2) { - /* - * The only possible values are: - * 0 = CPU down - * 1 = CPU (still) up - * 2 = CPU requested to be up before it had a chance - * to actually make itself down. - * Any other value is a bug. - */ - BUG(); - } + exynos_cpu_power_up(cpunr); + return 0; +} - arch_spin_unlock(&exynos_mcpm_lock); - local_irq_enable(); +static int exynos_cluster_powerup(unsigned int cluster) +{ + pr_debug("%s: cluster %u\n", __func__, cluster); + if (cluster >= EXYNOS5420_NR_CLUSTERS) + return -EINVAL; + exynos_cluster_power_up(cluster); return 0; } -/* - * NOTE: This function requires the stack data to be visible through power down - * and can only be executed on processors like A15 and A7 that hit the cache - * with the C bit clear in the SCTLR register. - */ -static void exynos_power_down(void) +static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) { - unsigned int mpidr, cpu, cluster; - bool last_man = false, skip_wfi = false; - unsigned int cpunr; - - mpidr = read_cpuid_mpidr(); - cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); - cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); - cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); + unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER || cluster >= EXYNOS5420_NR_CLUSTERS); + exynos_cpu_power_down(cpunr); +} - __mcpm_cpu_going_down(cpu, cluster); - - arch_spin_lock(&exynos_mcpm_lock); - BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP); - cpu_use_count[cpu][cluster]--; - if (cpu_use_count[cpu][cluster] == 0) { - exynos_cpu_power_down(cpunr); - - if (exynos_cluster_unused(cluster)) { - exynos_cluster_power_down(cluster); - last_man = true; - } - } else if (cpu_use_count[cpu][cluster] == 1) { - /* - * A power_up request went ahead of us. - * Even if we do not want to shut this CPU down, - * the caller expects a certain state as if the WFI - * was aborted. So let's continue with cache cleaning. - */ - skip_wfi = true; - } else { - BUG(); - } - - if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { - arch_spin_unlock(&exynos_mcpm_lock); - - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { - /* - * On the Cortex-A15 we need to disable - * L2 prefetching before flushing the cache. - */ - asm volatile( - "mcr p15, 1, %0, c15, c0, 3\n\t" - "isb\n\t" - "dsb" - : : "r" (0x400)); - } +static void exynos_cluster_powerdown_prepare(unsigned int cluster) +{ + pr_debug("%s: cluster %u\n", __func__, cluster); + BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS); + exynos_cluster_power_down(cluster); +} - /* Flush all cache levels for this cluster. */ - exynos_v7_exit_coherency_flush(all); +static void exynos_cpu_cache_disable(void) +{ + /* Disable and flush the local CPU cache. */ + exynos_v7_exit_coherency_flush(louis); +} +static void exynos_cluster_cache_disable(void) +{ + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { /* - * Disable cluster-level coherency by masking - * incoming snoops and DVM messages: + * On the Cortex-A15 we need to disable + * L2 prefetching before flushing the cache. */ - cci_disable_port_by_cpu(mpidr); - - __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN); - } else { - arch_spin_unlock(&exynos_mcpm_lock); - - /* Disable and flush the local CPU cache. */ - exynos_v7_exit_coherency_flush(louis); + asm volatile( + "mcr p15, 1, %0, c15, c0, 3\n\t" + "isb\n\t" + "dsb" + : : "r" (0x400)); } - __mcpm_cpu_down(cpu, cluster); - - /* Now we are prepared for power-down, do it: */ - if (!skip_wfi) - wfi(); + /* Flush all cache levels for this cluster. */ + exynos_v7_exit_coherency_flush(all); - /* Not dead at this point? Let our caller cope. */ + /* + * Disable cluster-level coherency by masking + * incoming snoops and DVM messages: + */ + cci_disable_port_by_cpu(read_cpuid_mpidr()); } static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster) @@ -222,10 +142,8 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster) /* Wait for the core state to be OFF */ while (tries--) { - if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) { - if ((exynos_cpu_power_state(cpunr) == 0)) - return 0; /* success: the CPU is halted */ - } + if ((exynos_cpu_power_state(cpunr) == 0)) + return 0; /* success: the CPU is halted */ /* Otherwise, wait and retry: */ msleep(1); @@ -234,63 +152,23 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster) return -ETIMEDOUT; /* timeout */ } -static void exynos_powered_up(void) -{ - unsigned int mpidr, cpu, cluster; - - mpidr = read_cpuid_mpidr(); - cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); - cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); - - arch_spin_lock(&exynos_mcpm_lock); - if (cpu_use_count[cpu][cluster] == 0) - cpu_use_count[cpu][cluster] = 1; - arch_spin_unlock(&exynos_mcpm_lock); -} - -static void exynos_suspend(u64 residency) +static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster) { - unsigned int mpidr, cpunr; - - exynos_power_down(); - - /* - * Execution reaches here only if cpu did not power down. - * Hence roll back the changes done in exynos_power_down function. - * - * CAUTION: "This function requires the stack data to be visible through - * power down and can only be executed on processors like A15 and A7 - * that hit the cache with the C bit clear in the SCTLR register." - */ - mpidr = read_cpuid_mpidr(); - cpunr = exynos_pmu_cpunr(mpidr); - - exynos_cpu_power_up(cpunr); + /* especially when resuming: make sure power control is set */ + exynos_cpu_powerup(cpu, cluster); } static const struct mcpm_platform_ops exynos_power_ops = { - .power_up = exynos_power_up, - .power_down = exynos_power_down, + .cpu_powerup = exynos_cpu_powerup, + .cluster_powerup = exynos_cluster_powerup, + .cpu_powerdown_prepare = exynos_cpu_powerdown_prepare, + .cluster_powerdown_prepare = exynos_cluster_powerdown_prepare, + .cpu_cache_disable = exynos_cpu_cache_disable, + .cluster_cache_disable = exynos_cluster_cache_disable, .wait_for_powerdown = exynos_wait_for_powerdown, - .suspend = exynos_suspend, - .powered_up = exynos_powered_up, + .cpu_is_up = exynos_cpu_is_up, }; -static void __init exynos_mcpm_usage_count_init(void) -{ - unsigned int mpidr, cpu, cluster; - - mpidr = read_cpuid_mpidr(); - cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); - cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); - - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER || - cluster >= EXYNOS5420_NR_CLUSTERS); - - cpu_use_count[cpu][cluster] = 1; -} - /* * Enable cluster-level coherency, in preparation for turning on the MMU. */ @@ -302,19 +180,6 @@ static void __naked exynos_pm_power_up_setup(unsigned int affinity_level) "b cci_enable_port_for_self"); } -static void __init exynos_cache_off(void) -{ - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { - /* disable L2 prefetching on the Cortex-A15 */ - asm volatile( - "mcr p15, 1, %0, c15, c0, 3\n\t" - "isb\n\t" - "dsb" - : : "r" (0x400)); - } - exynos_v7_exit_coherency_flush(all); -} - static const struct of_device_id exynos_dt_mcpm_match[] = { { .compatible = "samsung,exynos5420" }, { .compatible = "samsung,exynos5800" }, @@ -370,13 +235,11 @@ static int __init exynos_mcpm_init(void) */ pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3); - exynos_mcpm_usage_count_init(); - ret = mcpm_platform_register(&exynos_power_ops); if (!ret) ret = mcpm_sync_init(exynos_pm_power_up_setup); if (!ret) - ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */ + ret = mcpm_loopback(exynos_cluster_cache_disable); /* turn on the CCI */ if (ret) { iounmap(ns_sram_base_addr); return ret; diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index d2e9f12d12f187e1e2c40f11748f75bbe0a283f2..a825bca2a2b699490809676cef6f66d4eb86fd21 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -34,30 +34,6 @@ extern void exynos4_secondary_startup(void); -/* - * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs - * during hot-(un)plugging CPUx. - * - * The feature can be cleared safely during first boot of secondary CPU. - * - * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering - * down a CPU so the CPU idle clock down feature could properly detect global - * idle state when CPUx is off. - */ -static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable) -{ - if (soc_is_exynos4()) { - unsigned int tmp; - - tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id)); - if (enable) - tmp |= S5P_USE_DELAYED_RESET_ASSERTION; - else - tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION); - pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id)); - } -} - #ifdef CONFIG_HOTPLUG_CPU static inline void cpu_leave_lowpower(u32 core_id) { @@ -73,8 +49,6 @@ static inline void cpu_leave_lowpower(u32 core_id) : "=&r" (v) : "Ir" (CR_C), "Ir" (0x40) : "cc"); - - exynos_set_delayed_reset_assertion(core_id, false); } static inline void platform_do_lowpower(unsigned int cpu, int *spurious) @@ -87,14 +61,6 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious) /* Turn the CPU off on next WFI instruction. */ exynos_cpu_power_down(core_id); - /* - * Exynos4 SoCs require setting - * USE_DELAYED_RESET_ASSERTION so the CPU idle - * clock down feature could properly detect - * global idle state when CPUx is off. - */ - exynos_set_delayed_reset_assertion(core_id, true); - wfi(); if (pen_release == core_id) { @@ -126,6 +92,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious) */ void exynos_cpu_power_down(int cpu) { + u32 core_conf; + if (cpu == 0 && (soc_is_exynos5420() || soc_is_exynos5800())) { /* * Bypass power down for CPU0 during suspend. Check for @@ -137,7 +105,10 @@ void exynos_cpu_power_down(int cpu) if (!(val & S5P_CORE_LOCAL_PWR_EN)) return; } - pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); + + core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu)); + core_conf &= ~S5P_CORE_LOCAL_PWR_EN; + pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); } /** @@ -148,7 +119,12 @@ void exynos_cpu_power_down(int cpu) */ void exynos_cpu_power_up(int cpu) { - pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN, + u32 core_conf = S5P_CORE_LOCAL_PWR_EN; + + if (soc_is_exynos3250()) + core_conf |= S5P_CORE_AUTOWAKEUP_EN; + + pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); } @@ -226,6 +202,10 @@ static void exynos_core_restart(u32 core_id) if (!of_machine_is_compatible("samsung,exynos3250")) return; + while (!pmu_raw_readl(S5P_PMU_SPARE2)) + udelay(10); + udelay(10); + val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id)); val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG; pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id)); @@ -346,7 +326,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) call_firmware_op(cpu_boot, core_id); - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + if (soc_is_exynos3250()) + dsb_sev(); + else + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); if (pen_release == -1) break; @@ -354,9 +337,6 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) udelay(10); } - /* No harm if this is called during first boot of secondary CPU */ - exynos_set_delayed_reset_assertion(core_id, false); - /* * now the secondary core is starting up let it run its * calibrations, then wait for it to finish @@ -403,6 +383,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) exynos_sysram_init(); + exynos_set_delayed_reset_assertion(true); + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) scu_enable(scu_base_addr()); diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index e6209dadc00d483c6e85b2b2870bc82828ad749d..cc75ab448be3b4ce9b3c0fc2e626da4ed3d6e6ca 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -127,6 +127,8 @@ int exynos_pm_central_resume(void) static void exynos_set_wakeupmask(long mask) { pmu_raw_writel(mask, S5P_WAKEUP_MASK); + if (soc_is_exynos3250()) + pmu_raw_writel(0x0, S5P_WAKEUP_MASK2); } static void exynos_cpu_set_boot_vector(long flags) @@ -140,7 +142,7 @@ static int exynos_aftr_finisher(unsigned long flags) { int ret; - exynos_set_wakeupmask(0x0000ff3e); + exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0x0000ff3e); /* Set value of power down register for aftr mode */ exynos_sys_powerdown_conf(SYS_AFTR); @@ -157,8 +159,13 @@ static int exynos_aftr_finisher(unsigned long flags) void exynos_enter_aftr(void) { + unsigned int cpuid = smp_processor_id(); + cpu_pm_enter(); + if (soc_is_exynos3250()) + exynos_set_boot_flag(cpuid, C2_STATE); + exynos_pm_central_suspend(); if (of_machine_is_compatible("samsung,exynos4212") || @@ -178,9 +185,13 @@ void exynos_enter_aftr(void) exynos_pm_central_resume(); + if (soc_is_exynos3250()) + exynos_clear_boot_flag(cpuid, C2_STATE); + cpu_pm_exit(); } +#if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE) static atomic_t cpu1_wakeup = ATOMIC_INIT(0); static int exynos_cpu0_enter_aftr(void) @@ -302,3 +313,4 @@ struct cpuidle_exynos_data cpuidle_coupled_exynos_data = { .pre_enter_aftr = exynos_pre_enter_aftr, .post_enter_aftr = exynos_post_enter_aftr, }; +#endif /* CONFIG_SMP && CONFIG_ARM_EXYNOS_CPUIDLE */ diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 37266a8264372a9d8ab898aec6389476f707869f..a9686535f9ed460706a41a99dc60d6d4f575ab3b 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -37,6 +37,7 @@ struct exynos_pm_domain { struct clk *oscclk; struct clk *clk[MAX_CLK_PER_DOMAIN]; struct clk *pclk[MAX_CLK_PER_DOMAIN]; + struct clk *asb_clk[MAX_CLK_PER_DOMAIN]; }; static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) @@ -45,14 +46,19 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) void __iomem *base; u32 timeout, pwr; char *op; + int i; pd = container_of(domain, struct exynos_pm_domain, pd); base = pd->base; + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { + if (IS_ERR(pd->asb_clk[i])) + break; + clk_prepare_enable(pd->asb_clk[i]); + } + /* Set oscclk before powering off a domain*/ if (!power_on) { - int i; - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { if (IS_ERR(pd->clk[i])) break; @@ -81,8 +87,6 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) /* Restore clocks after powering on a domain*/ if (power_on) { - int i; - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { if (IS_ERR(pd->clk[i])) break; @@ -92,6 +96,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) } } + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { + if (IS_ERR(pd->asb_clk[i])) + break; + clk_disable_unprepare(pd->asb_clk[i]); + } + return 0; } @@ -125,12 +135,21 @@ static __init int exynos4_pm_init_power_domain(void) return -ENOMEM; } - pd->pd.name = kstrdup(np->name, GFP_KERNEL); + pd->pd.name = kstrdup(dev_name(dev), GFP_KERNEL); pd->name = pd->pd.name; pd->base = of_iomap(np, 0); pd->pd.power_off = exynos_pd_power_off; pd->pd.power_on = exynos_pd_power_on; + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { + char clk_name[8]; + + snprintf(clk_name, sizeof(clk_name), "asb%d", i); + pd->asb_clk[i] = clk_get(dev, clk_name); + if (IS_ERR(pd->asb_clk[i])) + break; + } + pd->oscclk = clk_get(dev, "oscclk"); if (IS_ERR(pd->oscclk)) goto no_clk; @@ -169,7 +188,7 @@ static __init int exynos4_pm_init_power_domain(void) args.np = np; args.args_count = 0; child_domain = of_genpd_get_from_provider(&args); - if (!child_domain) + if (IS_ERR(child_domain)) continue; if (of_parse_phandle_with_args(np, "power-domains", @@ -177,7 +196,7 @@ static __init int exynos4_pm_init_power_domain(void) continue; parent_domain = of_genpd_get_from_provider(&args); - if (!parent_domain) + if (IS_ERR(parent_domain)) continue; if (pm_genpd_add_subdomain(parent_domain, child_domain)) diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index eb461e1c325ad96952495dad756af1d6b9c8a049..b7614333d2968befa767109f693bf7947528db4a 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -43,12 +43,14 @@ #define S5P_WAKEUP_STAT 0x0600 #define S5P_EINT_WAKEUP_MASK 0x0604 #define S5P_WAKEUP_MASK 0x0608 +#define S5P_WAKEUP_MASK2 0x0614 #define S5P_INFORM0 0x0800 #define S5P_INFORM1 0x0804 #define S5P_INFORM5 0x0814 #define S5P_INFORM6 0x0818 #define S5P_INFORM7 0x081C +#define S5P_PMU_SPARE2 0x0908 #define S5P_PMU_SPARE3 0x090C #define EXYNOS_IROM_DATA2 0x0988 @@ -182,6 +184,7 @@ #define S5P_CORE_LOCAL_PWR_EN 0x3 #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8) +#define S5P_CORE_AUTOWAKEUP_EN (1 << 31) /* Only for EXYNOS4210 */ #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h index f7b82f9c1e213053c53aaab321fb0e9f558b8b73..c2845717bc8fd9860d62ee14191556854a484d7d 100644 --- a/arch/arm/mach-exynos/smc.h +++ b/arch/arm/mach-exynos/smc.h @@ -17,6 +17,8 @@ #define SMC_CMD_SLEEP (-3) #define SMC_CMD_CPU1BOOT (-4) #define SMC_CMD_CPU0AFTR (-5) +#define SMC_CMD_SAVE (-6) +#define SMC_CMD_SHUTDOWN (-7) /* For CP15 Access */ #define SMC_CMD_C15RESUME (-11) /* For L2 Cache Access */ @@ -32,4 +34,11 @@ extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3); #endif /* __ASSEMBLY__ */ +/* op type for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */ +#define OP_TYPE_CORE 0x0 +#define OP_TYPE_CLUSTER 0x1 + +/* Power State required for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */ +#define SMC_POWERSTATE_IDLE 0x1 + #endif diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 2146d918aedd265623cd3a7cb1393e4437095f3b..7d23ce04cad5201919a58aefccafc88e882dd844 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -65,8 +65,6 @@ static struct sleep_save exynos_core_save[] = { struct exynos_pm_data { const struct exynos_wkup_irq *wkup_irq; - struct sleep_save *extra_save; - int num_extra_save; unsigned int wake_disable_mask; unsigned int *release_ret_regs; @@ -77,7 +75,7 @@ struct exynos_pm_data { int (*cpu_suspend)(unsigned long); }; -struct exynos_pm_data *pm_data; +static const struct exynos_pm_data *pm_data; static int exynos5420_cpu_state; static unsigned int exynos_pmu_spare3; @@ -89,8 +87,8 @@ static unsigned int exynos_pmu_spare3; static u32 exynos_irqwake_intmask = 0xffffffff; static const struct exynos_wkup_irq exynos3250_wkup_irq[] = { - { 105, BIT(1) }, /* RTC alarm */ - { 106, BIT(2) }, /* RTC tick */ + { 73, BIT(1) }, /* RTC alarm */ + { 74, BIT(2) }, /* RTC tick */ { /* sentinel */ }, }; @@ -106,7 +104,7 @@ static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { { /* sentinel */ }, }; -unsigned int exynos_release_ret_regs[] = { +static unsigned int exynos_release_ret_regs[] = { S5P_PAD_RET_MAUDIO_OPTION, S5P_PAD_RET_GPIO_OPTION, S5P_PAD_RET_UART_OPTION, @@ -117,7 +115,7 @@ unsigned int exynos_release_ret_regs[] = { REG_TABLE_END, }; -unsigned int exynos3250_release_ret_regs[] = { +static unsigned int exynos3250_release_ret_regs[] = { S5P_PAD_RET_MAUDIO_OPTION, S5P_PAD_RET_GPIO_OPTION, S5P_PAD_RET_UART_OPTION, @@ -130,7 +128,7 @@ unsigned int exynos3250_release_ret_regs[] = { REG_TABLE_END, }; -unsigned int exynos5420_release_ret_regs[] = { +static unsigned int exynos5420_release_ret_regs[] = { EXYNOS_PAD_RET_DRAM_OPTION, EXYNOS_PAD_RET_MAUDIO_OPTION, EXYNOS_PAD_RET_JTAG_OPTION, @@ -344,15 +342,13 @@ static void exynos_pm_enter_sleep_mode(void) static void exynos_pm_prepare(void) { + exynos_set_delayed_reset_assertion(false); + /* Set wake-up mask registers */ exynos_pm_set_wakeup_mask(); s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - if (pm_data->extra_save) - s3c_pm_do_save(pm_data->extra_save, - pm_data->num_extra_save); - exynos_pm_enter_sleep_mode(); /* ensure at least INFORM0 has the resume address */ @@ -475,10 +471,6 @@ static void exynos_pm_resume(void) /* For release retention */ exynos_pm_release_retention(); - if (pm_data->extra_save) - s3c_pm_do_restore_core(pm_data->extra_save, - pm_data->num_extra_save); - s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); if (cpuid == ARM_CPU_PART_CORTEX_A9) @@ -492,6 +484,7 @@ static void exynos_pm_resume(void) /* Clear SLEEP mode set in INFORM1 */ pmu_raw_writel(0x0, S5P_INFORM1); + exynos_set_delayed_reset_assertion(true); } static void exynos3250_pm_resume(void) @@ -685,7 +678,7 @@ static const struct exynos_pm_data exynos5250_pm_data = { .cpu_suspend = exynos_cpu_suspend, }; -static struct exynos_pm_data exynos5420_pm_data = { +static const struct exynos_pm_data exynos5420_pm_data = { .wkup_irq = exynos5250_wkup_irq, .wake_disable_mask = (0x7F << 7) | (0x1F << 1), .release_ret_regs = exynos5420_release_ret_regs, @@ -733,10 +726,12 @@ void __init exynos_pm_init(void) return; } - if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) + if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); + return; + } - pm_data = (struct exynos_pm_data *) match->data; + pm_data = (const struct exynos_pm_data *) match->data; /* All wakeup disable */ tmp = pmu_raw_readl(S5P_WAKEUP_MASK); diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h index 38a45260a7c8b522dc3b8c163a19d4debe711ca9..dd883698ff7eafe977d2a220468d5aad876ce5ce 100644 --- a/arch/arm/mach-gemini/common.h +++ b/arch/arm/mach-gemini/common.h @@ -12,6 +12,8 @@ #ifndef __GEMINI_COMMON_H__ #define __GEMINI_COMMON_H__ +#include + struct mtd_partition; extern void gemini_map_io(void); @@ -26,6 +28,6 @@ extern int platform_register_pflash(unsigned int size, struct mtd_partition *parts, unsigned int nr_parts); -extern void gemini_restart(char mode, const char *cmd); +extern void gemini_restart(enum reboot_mode mode, const char *cmd); #endif /* __GEMINI_COMMON_H__ */ diff --git a/arch/arm/mach-gemini/reset.c b/arch/arm/mach-gemini/reset.c index b26659759e2750bfef5f171b7d770905019e58ed..21a6d6d4f9c43d1ab8a608962761098bc847e35f 100644 --- a/arch/arm/mach-gemini/reset.c +++ b/arch/arm/mach-gemini/reset.c @@ -14,7 +14,9 @@ #include #include -void gemini_restart(char mode, const char *cmd) +#include "common.h" + +void gemini_restart(enum reboot_mode mode, const char *cmd) { __raw_writel(RESET_GLOBAL | RESET_CPU1, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c8dffcee97363eec0cb898f73973088496a3b0c6..3a3d3e9d7bfd6eb7f781bfa904df5caede06a33c 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -21,6 +21,7 @@ config MXC_AVIC config MXC_DEBUG_BOARD bool "Enable MXC debug board(for 3-stack)" + depends on MACH_MX27_3DS || MACH_MX31_3DS || MACH_MX35_3DS help The debug board is an integral part of the MXC 3-stack(PDK) platforms, it can be attached or removed from the peripheral @@ -50,6 +51,7 @@ config HAVE_IMX_ANATOP config HAVE_IMX_GPC bool + select PM_GENERIC_DOMAINS if PM config HAVE_IMX_MMDC bool @@ -77,13 +79,6 @@ config SOC_IMX21 select IMX_HAVE_IOMUX_V1 select MXC_AVIC -config SOC_IMX25 - bool - select ARCH_MXC_IOMUX_V3 - select CPU_ARM926T - select MXC_AVIC - select PINCTRL_IMX25 - config SOC_IMX27 bool select CPU_ARM926T @@ -149,62 +144,6 @@ config MACH_MX21ADS Include support for MX21ADS platform. This includes specific configurations for the board and its peripherals. -comment "MX25 platforms:" - -config MACH_MX25_3DS - bool "Support MX25PDK (3DS) Platform" - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMXDI_RTC - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select SOC_IMX25 - -config MACH_EUKREA_CPUIMX25SD - bool "Support Eukrea CPUIMX25 Platform" - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMXDI_RTC - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX25 - -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX25SD - default MACH_EUKREA_MBIMXSD25_BASEBOARD - -config MACH_EUKREA_MBIMXSD25_BASEBOARD - bool "Eukrea MBIMXSD development board" - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - help - This adds board specific devices that can be found on Eukrea's - MBIMXSD evaluation board. - -endchoice - -config MACH_IMX25_DT - bool "Support i.MX25 platforms from device tree" - select SOC_IMX25 - help - Include support for Freescale i.MX25 based platforms - using the device tree for discovery - comment "MX27 platforms:" config MACH_MX27ADS @@ -557,6 +496,20 @@ config MACH_VPR200 endif +if ARCH_MULTI_V5 + +comment "Device tree only" + +config SOC_IMX25 + bool "i.MX25 support" + select ARCH_MXC_IOMUX_V3 + select CPU_ARM926T + select MXC_AVIC + select PINCTRL_IMX25 + help + This enables support for Freescale i.MX25 processor +endif + if ARCH_MULTI_V7 comment "Device tree only" @@ -635,9 +588,10 @@ config SOC_VF610 select ARM_GIC select PINCTRL_VF610 select PL310_ERRATA_769419 if CACHE_L2X0 + select SMP_ON_UP if SMP help - This enable support for Freescale Vybrid VF610 processor. + This enables support for Freescale Vybrid VF610 processor. choice prompt "Clocksource for scheduler clock" @@ -667,7 +621,7 @@ config SOC_LS1021A select ZONE_DMA if ARM_LPAE help - This enable support for Freescale LS1021A processor. + This enables support for Freescale LS1021A processor. endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 8d1b1018090898d9d1698b6bb39825a99d540001..3244cf1d2773f1c20836b6b96e60f4d054aa67f0 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -3,7 +3,7 @@ obj-y := time.o cpu.o system.o irq-common.o obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o -obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o +obj-$(CONFIG_SOC_IMX25) += clk-imx25.o cpu-imx25.o mach-imx25.o obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o @@ -48,12 +48,6 @@ obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o # i.MX21 based machines obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o -# i.MX25 based machines -obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o -obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o -obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o - # i.MX27 based machines obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 59c0c8558c6bf5d5212c5e88083a55f859f01287..9c2633a9de9f0ec53dfdc20677eb709488b7824a 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -30,7 +30,6 @@ #include "clk.h" #include "common.h" #include "hardware.h" -#include "mx25.h" #define CCM_MPCTL 0x00 #define CCM_UPCTL 0x04 @@ -239,80 +238,6 @@ static int __init __mx25_clocks_init(unsigned long osc_rate, return 0; } -int __init mx25_clocks_init(void) -{ - void __iomem *ccm; - - ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K); - - __mx25_clocks_init(24000000, ccm); - - clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); - /* i.mx25 has the i.mx21 type uart */ - clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0"); - clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1"); - clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2"); - clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3"); - clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3"); - clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4"); - clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); - clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); - clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); - clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27"); - clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); - clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0"); - /* i.mx25 has the i.mx35 type cspi */ - clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0"); - clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1"); - clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2"); - clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad"); - clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc"); - clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1"); - clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2"); - clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0"); - clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0"); - clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0"); - clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx21-fb.0"); - clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx21-fb.0"); - clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx21-fb.0"); - clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1"); - clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0"); - clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0"); - clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0"); - clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1"); - clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1"); - clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1"); - clk_register_clkdev(clk[csi_ipg_per], "per", "imx25-camera.0"); - clk_register_clkdev(clk[csi_ipg], "ipg", "imx25-camera.0"); - clk_register_clkdev(clk[csi_ahb], "ahb", "imx25-camera.0"); - clk_register_clkdev(clk[dummy], "audmux", NULL); - clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0"); - clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1"); - /* i.mx25 has the i.mx35 type sdma */ - clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma"); - clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma"); - clk_register_clkdev(clk[iim_ipg], "iim", NULL); - - mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1); - - return 0; -} - static void __init mx25_clocks_init_dt(struct device_node *np) { struct device_node *refnp; diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index d04a430607b8af66ef71ba3f01ff8e151738eeb1..469a150bf98f98cbb5521343e81d531c7fc34e91 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -119,6 +119,7 @@ static unsigned int share_count_asrc; static unsigned int share_count_ssi1; static unsigned int share_count_ssi2; static unsigned int share_count_ssi3; +static unsigned int share_count_mipi_core_cfg; static void __init imx6q_clocks_init(struct device_node *ccm_node) { @@ -246,6 +247,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); + clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); if (cpu_is_imx6dl()) { clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); @@ -400,7 +402,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); - clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); + clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4); clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); @@ -415,7 +417,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); - clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); + clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg); + clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg); + clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); if (cpu_is_imx6dl()) /* * The multiplexer and divider of the imx6q clock gpu2d get diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 1028b6c505c496b315b90c65911e1cda403ac4fe..0f04e30b726d22e43ad725427bf2731295a705e7 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -23,13 +23,11 @@ struct of_device_id; void mx1_map_io(void); void mx21_map_io(void); -void mx25_map_io(void); void mx27_map_io(void); void mx31_map_io(void); void mx35_map_io(void); void imx1_init_early(void); void imx21_init_early(void); -void imx25_init_early(void); void imx27_init_early(void); void imx31_init_early(void); void imx35_init_early(void); @@ -37,13 +35,11 @@ void mxc_init_irq(void __iomem *); void tzic_init_irq(void); void mx1_init_irq(void); void mx21_init_irq(void); -void mx25_init_irq(void); void mx27_init_irq(void); void mx31_init_irq(void); void mx35_init_irq(void); void imx1_soc_init(void); void imx21_soc_init(void); -void imx25_soc_init(void); void imx27_soc_init(void); void imx31_soc_init(void); void imx35_soc_init(void); @@ -51,7 +47,6 @@ void epit_timer_init(void __iomem *base, int irq); void mxc_timer_init(void __iomem *, int); int mx1_clocks_init(unsigned long fref); int mx21_clocks_init(unsigned long lref, unsigned long fref); -int mx25_clocks_init(void); int mx27_clocks_init(unsigned long fref); int mx31_clocks_init(unsigned long fref); int mx35_clocks_init(void); @@ -71,6 +66,7 @@ unsigned int imx_get_soc_revision(void); void imx_init_revision_from_anatop(void); struct device *imx_soc_device_init(void); void imx6_enable_rbc(bool enable); +void imx_gpc_check_dt(void); void imx_gpc_set_arm_power_in_lpm(bool power_off); void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); @@ -106,7 +102,6 @@ static inline void imx_scu_map_io(void) {} static inline void imx_smp_prepare(void) {} #endif void imx_src_init(void); -void imx_gpc_init(void); void imx_gpc_pre_suspend(bool arm_power_off); void imx_gpc_post_resume(void); void imx_gpc_mask_all(void); diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c index 96ec64b5ff7d3e056ddfdea0f3918278732ea0c1..d0ad67e802d33962c1f10f9bfabe9e3b01c7c903 100644 --- a/arch/arm/mach-imx/cpu-imx25.c +++ b/arch/arm/mach-imx/cpu-imx25.c @@ -11,6 +11,8 @@ */ #include #include +#include +#include #include "iim.h" #include "hardware.h" @@ -20,8 +22,15 @@ static int mx25_cpu_rev = -1; static int mx25_read_cpu_rev(void) { u32 rev; + void __iomem *iim_base; + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim"); + iim_base = of_iomap(np, 0); + BUG_ON(!iim_base); + rev = readl(iim_base + MXC_IIMSREV); + iounmap(iim_base); - rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV)); switch (rev) { case 0x00: return IMX_CHIP_REVISION_1_0; diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h deleted file mode 100644 index 61a114cddc3966110cdecd368c76f4be4f48a3e2..0000000000000000000000000000000000000000 --- a/arch/arm/mach-imx/devices-imx25.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "devices/devices-common.h" - -extern const struct imx_fec_data imx25_fec_data; -#define imx25_add_fec(pdata) \ - imx_add_fec(&imx25_fec_data, pdata) - -extern const struct imx_flexcan_data imx25_flexcan_data[]; -#define imx25_add_flexcan(id) \ - imx_add_flexcan(&imx25_flexcan_data[id]) -#define imx25_add_flexcan0() imx25_add_flexcan(0) -#define imx25_add_flexcan1() imx25_add_flexcan(1) - -extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data; -#define imx25_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) - -extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data; -#define imx25_add_imxdi_rtc() \ - imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) - -extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data; -#define imx25_add_imx2_wdt() \ - imx_add_imx2_wdt(&imx25_imx2_wdt_data) - -extern const struct imx_imx_fb_data imx25_imx_fb_data; -#define imx25_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx25_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx25_imx_i2c_data[]; -#define imx25_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata) -#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata) -#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) -#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) - -extern const struct imx_imx_keypad_data imx25_imx_keypad_data; -#define imx25_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx25_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx25_imx_ssi_data[]; -#define imx25_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[]; -#define imx25_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata) -#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata) -#define imx25_add_imx_uart1(pdata) imx25_add_imx_uart(1, pdata) -#define imx25_add_imx_uart2(pdata) imx25_add_imx_uart(2, pdata) -#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) -#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) - -extern const struct imx_mx2_camera_data imx25_mx2_camera_data; -#define imx25_add_mx2_camera(pdata) \ - imx_add_mx2_camera(&imx25_mx2_camera_data, pdata) - -extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data; -#define imx25_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data; -#define imx25_add_mxc_ehci_hs(pdata) \ - imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata) - -extern const struct imx_mxc_nand_data imx25_mxc_nand_data; -#define imx25_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) - -extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[]; -#define imx25_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx25_cspi_data[]; -#define imx25_add_spi_imx(id, pdata) \ - imx_add_spi_imx(&imx25_cspi_data[id], pdata) -#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) -#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) -#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig index 1d2cc1805f3e51d00f4f7db8d0e3f1cad318a0f0..3a552989248ed309020a0c159480f8c569f71dc9 100644 --- a/arch/arm/mach-imx/devices/Kconfig +++ b/arch/arm/mach-imx/devices/Kconfig @@ -21,9 +21,6 @@ config IMX_HAVE_PLATFORM_IMX27_CODA config IMX_HAVE_PLATFORM_IMX2_WDT bool -config IMX_HAVE_PLATFORM_IMXDI_RTC - bool - config IMX_HAVE_PLATFORM_IMX_FB bool diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile index 8fdb12b4ca7ee12d12b9798e66d60c3dbac998fe..e5cf587bc1a0ed346ec128e3ff7cff3f990a477d 100644 --- a/arch/arm/mach-imx/devices/Makefile +++ b/arch/arm/mach-imx/devices/Makefile @@ -8,7 +8,6 @@ obj-y += platform-gpio-mxc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o obj-y += platform-imx-dma.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c index d86f9250b4ee87292ce8758a4538cd64a8b4ac92..b403a4fe2892b3773f3b92ea6f8520b077269588 100644 --- a/arch/arm/mach-imx/devices/platform-fec.c +++ b/arch/arm/mach-imx/devices/platform-fec.c @@ -19,11 +19,6 @@ .irq = soc ## _INT_FEC, \ } -#ifdef CONFIG_SOC_IMX25 -const struct imx_fec_data imx25_fec_data __initconst = - imx_fec_data_entry_single(MX25, "imx25-fec"); -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_fec_data imx27_fec_data __initconst = imx_fec_data_entry_single(MX27, "imx27-fec"); diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c index 23b0061347cba81f5fd8c63add9d8d57b7585d82..25e1de6f3a47fd5ebca7f7c0164e7706b4bece8c 100644 --- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c +++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c @@ -18,11 +18,6 @@ .irq = soc ## _INT_USB_OTG, \ } -#ifdef CONFIG_SOC_IMX25 -const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27"); -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27"); diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c index 25a47c616b2d7c2b855eaf510b84b4d466b51d62..7df6328306f964dcf5c698f30c2bf4aeabb757f1 100644 --- a/arch/arm/mach-imx/devices/platform-imx-fb.c +++ b/arch/arm/mach-imx/devices/platform-imx-fb.c @@ -29,11 +29,6 @@ const struct imx_imx_fb_data imx21_imx_fb_data __initconst = imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx_fb_data imx25_imx_fb_data __initconst = - imx_imx_fb_data_entry_single(MX25, "imx21-fb", SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_imx_fb_data imx27_imx_fb_data __initconst = imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K); diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c index 644ac26898823ac617c5892a5c41571af254cf00..ae9791522fc80e70ac8df2dcd2791f8a3f341a6a 100644 --- a/arch/arm/mach-imx/devices/platform-imx-i2c.c +++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c @@ -31,16 +31,6 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { -#define imx25_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX25, "imx21-i2c", _id, _hwid, SZ_16K) - imx25_imx_i2c_data_entry(0, 1), - imx25_imx_i2c_data_entry(1, 2), - imx25_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { #define imx27_imx_i2c_data_entry(_id, _hwid) \ diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c index f42200b7aca96044b8d10dbedb10cfe680ab5a80..479e4d70dbf92c43812124f72add5cd6d87d21c0 100644 --- a/arch/arm/mach-imx/devices/platform-imx-keypad.c +++ b/arch/arm/mach-imx/devices/platform-imx-keypad.c @@ -21,11 +21,6 @@ const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = imx_imx_keypad_data_entry_single(MX21, SZ_16); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX25, SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = imx_imx_keypad_data_entry_single(MX27, SZ_16); diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c index 1c7c721ebff1ba04ef2f73e1025aace0758769c1..6f0e94eb29eeec2c549a0110beb3234357e9c08d 100644 --- a/arch/arm/mach-imx/devices/platform-imx-ssi.c +++ b/arch/arm/mach-imx/devices/platform-imx-ssi.c @@ -30,15 +30,6 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { -#define imx25_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) - imx25_imx_ssi_data_entry(0, 1), - imx25_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { #define imx27_imx_ssi_data_entry(_id, _hwid) \ diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c index 8c01836bc1d4b03c8df84a28cda9cc433d9a825c..6962cff4a9504569cc333b6e538bdbc54dfa1a36 100644 --- a/arch/arm/mach-imx/devices/platform-imx-uart.c +++ b/arch/arm/mach-imx/devices/platform-imx-uart.c @@ -47,18 +47,6 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { }; #endif -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { -#define imx25_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) - imx25_imx_uart_data_entry(0, 1), - imx25_imx_uart_data_entry(1, 2), - imx25_imx_uart_data_entry(2, 3), - imx25_imx_uart_data_entry(3, 4), - imx25_imx_uart_data_entry(4, 5), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { #define imx27_imx_uart_data_entry(_id, _hwid) \ diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c index 54f63bc25ca4d1e7974668577324ef2b61285a07..8c134c8d7500349f1040cca3fcad40ea851a1bcd 100644 --- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c +++ b/arch/arm/mach-imx/devices/platform-imx2-wdt.c @@ -25,11 +25,6 @@ const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K); diff --git a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c b/arch/arm/mach-imx/devices/platform-imxdi_rtc.c deleted file mode 100644 index 5bb490d556eaa9dab0d26ba77ba5d77e4aba1d5b..0000000000000000000000000000000000000000 --- a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imxdi_rtc_data_entry_single(soc) \ - { \ - .iobase = soc ## _DRYICE_BASE_ADDR, \ - .irq = soc ## _INT_DRYICE, \ - } - -#ifdef CONFIG_SOC_IMX25 -const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst = - imx_imxdi_rtc_data_entry_single(MX25); -#endif /* ifdef CONFIG_SOC_IMX25 */ - -struct platform_device *__init imx_add_imxdi_rtc( - const struct imx_imxdi_rtc_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("imxdi_rtc", 0, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c index b53e1f348f518f5de7ec9aa8745a7299d5c26df4..4c377c33242c75b31bfe8849a5662cb770486223 100644 --- a/arch/arm/mach-imx/devices/platform-mx2-camera.c +++ b/arch/arm/mach-imx/devices/platform-mx2-camera.c @@ -27,11 +27,6 @@ .irqemmaprp = soc ## _INT_EMMAPRP, \ } -#ifdef CONFIG_SOC_IMX25 -const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst = - imx_mx2_camera_data_entry_single(MX25, "imx25-camera"); -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera"); diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c index 296353662ff025dac519c7cffbb112f601dc007f..4537abd2a8f23df0d8323165473f65aca6258015 100644 --- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c +++ b/arch/arm/mach-imx/devices/platform-mxc-ehci.c @@ -18,13 +18,6 @@ .irq = soc ## _INT_USB_ ## hs, \ } -#ifdef CONFIG_SOC_IMX25 -const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst = - imx_mxc_ehci_data_entry_single(MX25, 0, OTG); -const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst = - imx_mxc_ehci_data_entry_single(MX25, 1, HS); -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = imx_mxc_ehci_data_entry_single(MX27, 0, OTG); diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c index fa618a34f4625f6df8a5759116434fcd682eda18..676df4920c7b6d6e06a7e86309c5d1455a3c1648 100644 --- a/arch/arm/mach-imx/devices/platform-mxc_nand.c +++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c @@ -34,11 +34,6 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_SOC_IMX25 -const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K); -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K); diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c index fb8d4a2ad48c0629b3cfbbe7c2b76c6646c9b436..a5edd7d60266985472ac9de11e6fb9801f8eadeb 100644 --- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c +++ b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Pengutronix, Wolfram Sang + * Copyright (C) 2010 Pengutronix, Wolfram Sang * * This program is free software; you can redistribute it and/or modify it under * the terms of the GNU General Public License version 2 as published by the diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c index aca825d74c48761dabcecc6f54467520036bc698..5e9707b47f92925078200bdd363982617ece4996 100644 --- a/arch/arm/mach-imx/devices/platform-spi_imx.c +++ b/arch/arm/mach-imx/devices/platform-spi_imx.c @@ -39,17 +39,6 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { }; #endif -#ifdef CONFIG_SOC_IMX25 -/* i.mx25 has the i.mx35 type cspi */ -const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { -#define imx25_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX25, CSPI, "imx35-cspi", _id, _hwid, SZ_16K) - imx25_cspi_data_entry(0, 1), - imx25_cspi_data_entry(1, 2), - imx25_cspi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - #ifdef CONFIG_SOC_IMX27 const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { #define imx27_cspi_data_entry(_id, _hwid) \ diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c deleted file mode 100644 index 42a5a3d14c5f32d3804a78b58e9c7730eea39206..0000000000000000000000000000000000000000 --- a/arch/arm/mach-imx/ehci-imx25.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include -#include -#include - -#include "ehci.h" -#include "hardware.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX25_OTG_SIC_SHIFT 29 -#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) -#define MX25_OTG_PM_BIT (1 << 24) -#define MX25_OTG_PP_BIT (1 << 11) -#define MX25_OTG_OCPOL_BIT (1 << 3) - -#define MX25_H1_SIC_SHIFT 21 -#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) -#define MX25_H1_PP_BIT (1 << 18) -#define MX25_H1_PM_BIT (1 << 16) -#define MX25_H1_IPPUE_UP_BIT (1 << 7) -#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX25_H1_TLL_BIT (1 << 5) -#define MX25_H1_USBTE_BIT (1 << 4) -#define MX25_H1_OCPOL_BIT (1 << 2) - -int mx25_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | - MX25_OTG_OCPOL_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX25_OTG_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX25_OTG_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX25_OTG_OCPOL_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | - MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT | - MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX25_H1_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX25_H1_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX25_H1_OCPOL_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX25_H1_TLL_BIT; - - if (flags & MXC_EHCI_INTERNAL_PHY) - v |= MX25_H1_USBTE_BIT; - - if (flags & MXC_EHCI_IPPUE_DOWN) - v |= MX25_H1_IPPUE_DOWN_BIT; - - if (flags & MXC_EHCI_IPPUE_UP) - v |= MX25_H1_IPPUE_UP_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} - diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c deleted file mode 100644 index e77cc3af6db2b4f3a4b7d5bceac36c53660283d4..0000000000000000000000000000000000000000 --- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * - * Based on pcm970-baseboard.c which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include -#include -#include -#include -#include -#include