Commit 2021d5b7 authored by Neil Armstrong's avatar Neil Armstrong
Browse files

drm/meson: Convert existing documentation to actual kerneldoc 



Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
parent 8cceda53

drivers/gpu/drm/meson/meson_canvas.c

+3 −1
Original line number Diff line number Diff line
@@ -24,7 +24,9 @@ 
#include "meson_canvas.h"

#include "meson_registers.h"



/*

/**

 * DOC: Canvas

 *

 * CANVAS is a memory zone where physical memory frames information

 * are stored for the VIU to scanout.

 */

drivers/gpu/drm/meson/meson_drv.c

+3 −2
Original line number Diff line number Diff line
@@ -52,13 +52,14 @@ 
#define DRIVER_NAME "meson"

#define DRIVER_DESC "Amlogic Meson DRM driver"



/*

 * Video Processing Unit

/**

 * DOC: Video Processing Unit

 *

 * VPU Handles the Global Video Processing, it includes management of the

 * clocks gates, blocks reset lines and power domains.

 *

 * What is missing :

 *

 * - Full reset of entire video processing HW blocks

 * - Scaling and setup of the VPU clock

 * - Bus clock gates

drivers/gpu/drm/meson/meson_dw_hdmi.c

+17 −8
Original line number Diff line number Diff line
@@ -42,11 +42,17 @@ 
#define DRIVER_NAME "meson-dw-hdmi"

#define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"



/*

/**

 * DOC: HDMI Output

 *

 * HDMI Output is composed of :

 *

 * - A Synopsys DesignWare HDMI Controller IP

 * - A TOP control block controlling the Clocks and PHY

 * - A custom HDMI PHY in order convert video to TMDS signal

 *

 * .. code::

 *

 *    ___________________________________

 *   |            HDMI TOP               |<= HPD

 *   |___________________________________|
@@ -55,6 +61,7 @@ 
 *   |    Controller    |________________|

 *   |___________________________________|<=> DDC

 *

 *

 * The HDMI TOP block only supports HPD sensing.

 * The Synopsys HDMI Controller interrupt is routed

 * through the TOP Block interrupt.
@@ -78,6 +85,7 @@ 
 * audio source interfaces.

 *

 * We handle the following features :

 *

 * - HPD Rise & Fall interrupt

 * - HDMI Controller Interrupt

 * - HDMI PHY Init for 480i to 1080p60
@@ -85,6 +93,7 @@ 
 * - VENC Mode setup for 480i to 1080p60

 *

 * What is missing :

 *

 * - PHY, Clock and Mode setup for 2k && 4k modes

 * - SDDC Scrambling mode for HDMI 2.0a

 * - HDCP Setup

drivers/gpu/drm/meson/meson_vclk.c

+15 −7
Original line number Diff line number Diff line
@@ -23,15 +23,23 @@ 
#include "meson_drv.h"

#include "meson_vclk.h"



/*

/**

 * DOC: Video Clocks

 *

 * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.

 * We handle the following encodings :

 *

 * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks

 * - HDMI Pixel Clocks generation

 *

 * What is missing :

 *

 * - Genenate Pixel clocks for 2K/4K 10bit formats

 *

 * Clock generator scheme :

 *

 * .. code::

 *

 *    __________   _________            _____

 *   |          | |         |          |     |--ENCI

 *   | HDMI PLL |-| PLL_DIV |--- VCLK--|     |--ENCL

drivers/gpu/drm/meson/meson_venc.c

+16 −9
Original line number Diff line number Diff line
@@ -26,23 +26,30 @@ 
#include "meson_vclk.h"

#include "meson_registers.h"



/*

/**

 * DOC: Video Encoder

 *

 * VENC Handle the pixels encoding to the output formats.

 * We handle the following encodings :

 *

 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter

 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP

 * - Setup of more clock rates for HDMI modes

 *

 * What is missing :

 *

 * - LCD Panel encoding via ENCL

 * - TV Panel encoding via ENCT

 *

 * VENC paths :

 *

 * .. code::

 *

 *          _____   _____   ____________________

 *   vd1---|     |-|     | | VENC     /---------|----VDAC

 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|\

 *   vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|

 *   osd1--|     |-|     | | \                  | X--HDMI-TX

 * osd2--|_____|-|_____| |  |\-ENCP--ENCP_DVI-|/

 *   osd2--|_____|-|_____| |  |\-ENCP--ENCP_DVI-|-|

 *                         |  |                 |

 *                         |  \--ENCL-----------|----LVDS

 *                         |____________________|