Commit 1f9ca184 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/process' into x86/mm, to create new base for further patches 



Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents b23adb7d d582799f

arch/um/include/shared/os.h

+2 −2
Original line number Diff line number Diff line
@@ -302,8 +302,8 @@ extern int ignore_sigio_fd(int fd); 
extern void maybe_sigio_broken(int fd, int read);

extern void sigio_broken(int fd, int read);



/* sys-x86_64/prctl.c */

extern int os_arch_prctl(int pid, int code, unsigned long *addr);

/* prctl.c */

extern int os_arch_prctl(int pid, int option, unsigned long *arg2);



/* tty.c */

extern int get_pty(void);

arch/x86/entry/syscalls/syscall_32.tbl

+1 −0
Original line number Diff line number Diff line
@@ -390,3 +390,4 @@ 
381	i386	pkey_alloc		sys_pkey_alloc

382	i386	pkey_free		sys_pkey_free

383	i386	statx			sys_statx

384	i386	arch_prctl		sys_arch_prctl			compat_sys_arch_prctl

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -187,6 +187,7 @@ 
 * Reuse free bits when adding new feature flags!

 */

#define X86_FEATURE_RING3MWAIT	( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */

#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */

#define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_CAT_L3	( 7*32+ 4) /* Cache Allocation Technology L3 */

arch/x86/include/asm/msr-index.h

+8 −3
Original line number Diff line number Diff line
@@ -45,6 +45,8 @@ 
#define MSR_IA32_PERFCTR1		0x000000c2

#define MSR_FSB_FREQ			0x000000cd

#define MSR_PLATFORM_INFO		0x000000ce

#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT	31

#define MSR_PLATFORM_INFO_CPUID_FAULT		BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)



#define MSR_PKG_CST_CONFIG_CONTROL	0x000000e2

#define NHM_C3_AUTO_DEMOTE		(1UL << 25)
@@ -127,6 +129,7 @@ 


/* DEBUGCTLMSR bits (others vary by model): */

#define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */

#define DEBUGCTLMSR_BTF_SHIFT		1

#define DEBUGCTLMSR_BTF			(1UL <<  1) /* single-step on branches */

#define DEBUGCTLMSR_TR			(1UL <<  6)

#define DEBUGCTLMSR_BTS			(1UL <<  7)
@@ -552,10 +555,12 @@ 
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT	39

#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)



/* MISC_FEATURE_ENABLES non-architectural features */

#define MSR_MISC_FEATURE_ENABLES	0x00000140

/* MISC_FEATURES_ENABLES non-architectural features */

#define MSR_MISC_FEATURES_ENABLES	0x00000140



#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT		1

#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT	0

#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT		BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)

#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT	1



#define MSR_IA32_TSC_DEADLINE		0x000006E0

arch/x86/include/asm/processor.h

+2 −0
Original line number Diff line number Diff line
@@ -888,6 +888,8 @@ extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 
extern int get_tsc_mode(unsigned long adr);

extern int set_tsc_mode(unsigned int val);



DECLARE_PER_CPU(u64, msr_misc_features_shadow);



/* Register/unregister a process' MPX related resource */

#define MPX_ENABLE_MANAGEMENT()	mpx_enable_management()

#define MPX_DISABLE_MANAGEMENT()	mpx_disable_management()