Loading arch/arm/kernel/debug.S +2 −11 Original line number Diff line number Diff line Loading @@ -22,11 +22,11 @@ #if defined(CONFIG_DEBUG_ICEDCC) @@ debug using ARM EmbeddedICE DCC channel #if defined(CONFIG_CPU_V6) .macro addruart, rx, tmp .endm #if defined(CONFIG_CPU_V6) .macro senduart, rd, rx mcr p14, 0, \rd, c0, c5, 0 .endm Loading @@ -51,9 +51,6 @@ #elif defined(CONFIG_CPU_V7) .macro addruart, rx, tmp .endm .macro senduart, rd, rx mcr p14, 0, \rd, c0, c5, 0 .endm Loading @@ -71,9 +68,6 @@ wait: mrc p14, 0, pc, c0, c1, 0 #elif defined(CONFIG_CPU_XSCALE) .macro addruart, rx, tmp .endm .macro senduart, rd, rx mcr p14, 0, \rd, c8, c0, 0 .endm Loading @@ -98,9 +92,6 @@ wait: mrc p14, 0, pc, c0, c1, 0 #else .macro addruart, rx, tmp .endm .macro senduart, rd, rx mcr p14, 0, \rd, c1, c0, 0 .endm Loading Loading
arch/arm/kernel/debug.S +2 −11 Original line number Diff line number Diff line Loading @@ -22,11 +22,11 @@ #if defined(CONFIG_DEBUG_ICEDCC) @@ debug using ARM EmbeddedICE DCC channel #if defined(CONFIG_CPU_V6) .macro addruart, rx, tmp .endm #if defined(CONFIG_CPU_V6) .macro senduart, rd, rx mcr p14, 0, \rd, c0, c5, 0 .endm Loading @@ -51,9 +51,6 @@ #elif defined(CONFIG_CPU_V7) .macro addruart, rx, tmp .endm .macro senduart, rd, rx mcr p14, 0, \rd, c0, c5, 0 .endm Loading @@ -71,9 +68,6 @@ wait: mrc p14, 0, pc, c0, c1, 0 #elif defined(CONFIG_CPU_XSCALE) .macro addruart, rx, tmp .endm .macro senduart, rd, rx mcr p14, 0, \rd, c8, c0, 0 .endm Loading @@ -98,9 +92,6 @@ wait: mrc p14, 0, pc, c0, c1, 0 #else .macro addruart, rx, tmp .endm .macro senduart, rd, rx mcr p14, 0, \rd, c1, c0, 0 .endm Loading