Commit 1382ea63 authored by Loc Ho's avatar Loc Ho Committed by Stephen Boyd
Browse files

clk: xgene: Fix divider with non-zero shift value 



The X-Gene clock driver missed the divider shift operation when
set the divider value.

Signed-off-by: default avatarLoc Ho <lho@apm.com>
Fixes: 308964ca ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 6dc669a2

drivers/clk/clk-xgene.c

+2 −1
Original line number Diff line number Diff line
@@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate, 
		/* Set new divider */

		data = xgene_clk_read(pclk->param.divider_reg +

				pclk->param.reg_divider_offset);

		data &= ~((1 << pclk->param.reg_divider_width) - 1);

		data &= ~((1 << pclk->param.reg_divider_width) - 1)

				<< pclk->param.reg_divider_shift;

		data |= divider;

		xgene_clk_write(data, pclk->param.divider_reg +

					pclk->param.reg_divider_offset);