Loading arch/sh/Kconfig +1 −13 Original line number Diff line number Diff line Loading @@ -479,7 +479,7 @@ config SH_CLK_MD int "CPU Mode Pin Setting" depends on CPU_SUBTYPE_SH7619 || CPU_SUBTYPE_SH7206 help MD2 - MD0 Setting. MD2 - MD0 pin setting. menu "CPU Frequency scaling" Loading Loading @@ -580,18 +580,6 @@ config NR_CPUS source "kernel/Kconfig.preempt" config CPU_HAS_SR_RB bool "CPU has SR.RB" depends on CPU_SH3 || CPU_SH4 default y help This will enable the use of SR.RB register bank usage. Processors that are lacking this bit must have another method in place for accomplishing what is taken care of by the banked registers. See <file:Documentation/sh/register-banks.txt> for further information on SR.RB and register banking in the kernel in general. config NODES_SHIFT int default "1" Loading arch/sh/Kconfig.debug +2 −1 Original line number Diff line number Diff line Loading @@ -31,7 +31,8 @@ config EARLY_SCIF_CONSOLE_PORT hex "SCIF port for early console" depends on EARLY_SCIF_CONSOLE default "0xffe00000" if CPU_SUBTYPE_SH7780 default "0xfffe9800" if CPU_SUBTYPE_SH72060 default "0xfffe9800" if CPU_SUBTYPE_SH7206 default "0xf8420000" if CPU_SUBTYPE_SH7619 default "0xffe80000" if CPU_SH4 config EARLY_PRINTK Loading arch/sh/kernel/signal.c +1 −1 Original line number Diff line number Diff line Loading @@ -101,7 +101,7 @@ sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss, */ #define MOVW(n) (0x9300|((n)-2)) /* Move mem word at PC+n to R3 */ #if defined(CONFIG_CPU_SH2) || defined(CONFIG_CPU_SH2A) #if defined(CONFIG_CPU_SH2) #define TRAP_NOARG 0xc320 /* Syscall w/no args (NR in R3) */ #else #define TRAP_NOARG 0xc310 /* Syscall w/no args (NR in R3) */ Loading arch/sh/kernel/sys_sh.c +1 −1 Original line number Diff line number Diff line Loading @@ -324,7 +324,7 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[]) register long __sc4 __asm__ ("r4") = (long) filename; register long __sc5 __asm__ ("r5") = (long) argv; register long __sc6 __asm__ ("r6") = (long) envp; __asm__ __volatile__ ("trapa #0x13" : "=z" (__sc0) __asm__ __volatile__ (SYSCALL_ARG3 : "=z" (__sc0) : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) : "memory"); return __sc0; Loading arch/sh/mm/init.c +2 −0 Original line number Diff line number Diff line Loading @@ -77,6 +77,7 @@ void show_mem(void) printk("%d pages swap cached\n",cached); } #ifdef CONFIG_MMU static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot) { pgd_t *pgd; Loading Loading @@ -139,6 +140,7 @@ void __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t prot) set_pte_phys(address, phys, prot); } #endif /* CONFIG_MMU */ /* References to section boundaries */ Loading Loading
arch/sh/Kconfig +1 −13 Original line number Diff line number Diff line Loading @@ -479,7 +479,7 @@ config SH_CLK_MD int "CPU Mode Pin Setting" depends on CPU_SUBTYPE_SH7619 || CPU_SUBTYPE_SH7206 help MD2 - MD0 Setting. MD2 - MD0 pin setting. menu "CPU Frequency scaling" Loading Loading @@ -580,18 +580,6 @@ config NR_CPUS source "kernel/Kconfig.preempt" config CPU_HAS_SR_RB bool "CPU has SR.RB" depends on CPU_SH3 || CPU_SH4 default y help This will enable the use of SR.RB register bank usage. Processors that are lacking this bit must have another method in place for accomplishing what is taken care of by the banked registers. See <file:Documentation/sh/register-banks.txt> for further information on SR.RB and register banking in the kernel in general. config NODES_SHIFT int default "1" Loading
arch/sh/Kconfig.debug +2 −1 Original line number Diff line number Diff line Loading @@ -31,7 +31,8 @@ config EARLY_SCIF_CONSOLE_PORT hex "SCIF port for early console" depends on EARLY_SCIF_CONSOLE default "0xffe00000" if CPU_SUBTYPE_SH7780 default "0xfffe9800" if CPU_SUBTYPE_SH72060 default "0xfffe9800" if CPU_SUBTYPE_SH7206 default "0xf8420000" if CPU_SUBTYPE_SH7619 default "0xffe80000" if CPU_SH4 config EARLY_PRINTK Loading
arch/sh/kernel/signal.c +1 −1 Original line number Diff line number Diff line Loading @@ -101,7 +101,7 @@ sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss, */ #define MOVW(n) (0x9300|((n)-2)) /* Move mem word at PC+n to R3 */ #if defined(CONFIG_CPU_SH2) || defined(CONFIG_CPU_SH2A) #if defined(CONFIG_CPU_SH2) #define TRAP_NOARG 0xc320 /* Syscall w/no args (NR in R3) */ #else #define TRAP_NOARG 0xc310 /* Syscall w/no args (NR in R3) */ Loading
arch/sh/kernel/sys_sh.c +1 −1 Original line number Diff line number Diff line Loading @@ -324,7 +324,7 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[]) register long __sc4 __asm__ ("r4") = (long) filename; register long __sc5 __asm__ ("r5") = (long) argv; register long __sc6 __asm__ ("r6") = (long) envp; __asm__ __volatile__ ("trapa #0x13" : "=z" (__sc0) __asm__ __volatile__ (SYSCALL_ARG3 : "=z" (__sc0) : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) : "memory"); return __sc0; Loading
arch/sh/mm/init.c +2 −0 Original line number Diff line number Diff line Loading @@ -77,6 +77,7 @@ void show_mem(void) printk("%d pages swap cached\n",cached); } #ifdef CONFIG_MMU static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot) { pgd_t *pgd; Loading Loading @@ -139,6 +140,7 @@ void __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t prot) set_pte_phys(address, phys, prot); } #endif /* CONFIG_MMU */ /* References to section boundaries */ Loading