Loading include/asm-x86/seccomp_64.h +1 −0 Original line number Diff line number Diff line #ifndef _ASM_SECCOMP_H #define _ASM_SECCOMP_H #include <linux/thread_info.h> Loading include/asm-x86/suspend_32.h +5 −0 Original line number Diff line number Diff line Loading @@ -3,6 +3,9 @@ * Based on code * Copyright 2001 Patrick Mochel <mochel@osdl.org> */ #ifndef __ASM_X86_32_SUSPEND_H #define __ASM_X86_32_SUSPEND_H #include <asm/desc.h> #include <asm/i387.h> Loading Loading @@ -44,3 +47,5 @@ static inline void acpi_save_register_state(unsigned long return_point) /* routines for saving/restoring kernel state */ extern int acpi_save_state_mem(void); #endif #endif /* __ASM_X86_32_SUSPEND_H */ include/asm-x86/xor_32.h +5 −0 Original line number Diff line number Diff line #ifndef ASM_X86__XOR_32_H #define ASM_X86__XOR_32_H /* * Optimized RAID-5 checksumming functions for MMX and SSE. * Loading Loading @@ -881,3 +884,5 @@ do { \ deals with a load to a line that is being prefetched. */ #define XOR_SELECT_TEMPLATE(FASTEST) \ (cpu_has_xmm ? &xor_block_pIII_sse : FASTEST) #endif /* ASM_X86__XOR_32_H */ include/asm-x86/xor_64.h +5 −0 Original line number Diff line number Diff line #ifndef ASM_X86__XOR_64_H #define ASM_X86__XOR_64_H /* * Optimized RAID-5 checksumming functions for MMX and SSE. * Loading Loading @@ -354,3 +357,5 @@ do { \ We may also be able to load into the L1 only depending on how the cpu deals with a load to a line that is being prefetched. */ #define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse) #endif /* ASM_X86__XOR_64_H */ Loading
include/asm-x86/seccomp_64.h +1 −0 Original line number Diff line number Diff line #ifndef _ASM_SECCOMP_H #define _ASM_SECCOMP_H #include <linux/thread_info.h> Loading
include/asm-x86/suspend_32.h +5 −0 Original line number Diff line number Diff line Loading @@ -3,6 +3,9 @@ * Based on code * Copyright 2001 Patrick Mochel <mochel@osdl.org> */ #ifndef __ASM_X86_32_SUSPEND_H #define __ASM_X86_32_SUSPEND_H #include <asm/desc.h> #include <asm/i387.h> Loading Loading @@ -44,3 +47,5 @@ static inline void acpi_save_register_state(unsigned long return_point) /* routines for saving/restoring kernel state */ extern int acpi_save_state_mem(void); #endif #endif /* __ASM_X86_32_SUSPEND_H */
include/asm-x86/xor_32.h +5 −0 Original line number Diff line number Diff line #ifndef ASM_X86__XOR_32_H #define ASM_X86__XOR_32_H /* * Optimized RAID-5 checksumming functions for MMX and SSE. * Loading Loading @@ -881,3 +884,5 @@ do { \ deals with a load to a line that is being prefetched. */ #define XOR_SELECT_TEMPLATE(FASTEST) \ (cpu_has_xmm ? &xor_block_pIII_sse : FASTEST) #endif /* ASM_X86__XOR_32_H */
include/asm-x86/xor_64.h +5 −0 Original line number Diff line number Diff line #ifndef ASM_X86__XOR_64_H #define ASM_X86__XOR_64_H /* * Optimized RAID-5 checksumming functions for MMX and SSE. * Loading Loading @@ -354,3 +357,5 @@ do { \ We may also be able to load into the L1 only depending on how the cpu deals with a load to a line that is being prefetched. */ #define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse) #endif /* ASM_X86__XOR_64_H */