Commit 094ab1db authored by H. Peter Anvin's avatar H. Peter Anvin
Browse files

x86, 386 removal: Remove CONFIG_INVLPG 



All 486+ CPUs support INVLPG, so remove the fallback 386 support
code.

Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
Link: http://lkml.kernel.org/r/1354132230-21854-6-git-send-email-hpa@linux.intel.com
parent e5bb8ad8

arch/x86/Kconfig.cpu

+0 −4
Original line number Diff line number Diff line
@@ -328,10 +328,6 @@ config X86_INVD_BUG 
config X86_WP_WORKS_OK

	def_bool y



config X86_INVLPG

	def_bool y

	depends on X86_32



config X86_POPAD_OK

	def_bool y

	depends on X86_32

arch/x86/include/asm/cpufeature.h

+0 −6
Original line number Diff line number Diff line
@@ -312,12 +312,6 @@ extern const char * const x86_power_flags[32]; 
#define cpu_has_cx16		boot_cpu_has(X86_FEATURE_CX16)

#define cpu_has_eager_fpu	boot_cpu_has(X86_FEATURE_EAGER_FPU)



#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)

# define cpu_has_invlpg		1

#else

# define cpu_has_invlpg		(boot_cpu_data.x86 > 3)

#endif



#ifdef CONFIG_X86_64



#undef  cpu_has_vme

arch/x86/include/asm/tlbflush.h

+0 −3
Original line number Diff line number Diff line
@@ -56,10 +56,7 @@ static inline void __flush_tlb_all(void) 


static inline void __flush_tlb_one(unsigned long addr)

{

	if (cpu_has_invlpg)

		__flush_tlb_single(addr);

	else

		__flush_tlb();

}



#define TLB_FLUSH_ALL	-1UL

arch/x86/kernel/cpu/amd.c

+0 −3
Original line number Diff line number Diff line
@@ -753,9 +753,6 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, 


static void __cpuinit cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c)

{

	if (!cpu_has_invlpg)

		return;



	tlb_flushall_shift = 5;



	if (c->x86 <= 0x11)

arch/x86/kernel/cpu/intel.c

+0 −4
Original line number Diff line number Diff line
@@ -612,10 +612,6 @@ static void __cpuinit intel_tlb_lookup(const unsigned char desc) 


static void __cpuinit intel_tlb_flushall_shift_set(struct cpuinfo_x86 *c)

{

	if (!cpu_has_invlpg) {

		tlb_flushall_shift = -1;

		return;

	}

	switch ((c->x86 << 8) + c->x86_model) {

	case 0x60f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */

	case 0x616: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */