Commit 072a551f authored by Jeffrey Hugo's avatar Jeffrey Hugo Committed by Stephen Boyd
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dt-bindings: clock: Document gpucc for msm8998 



The GPU for msm8998 has its own clock controller.  Document it.

Signed-off-by: default avatarJeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent a188339c

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

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@@ -2,13 +2,15 @@ Qualcomm Graphics Clock & Reset Controller Binding 
--------------------------------------------------



Required properties :

- compatible : shall contain "qcom,sdm845-gpucc"

- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"

- reg : shall contain base register location and length

- #clock-cells : from common clock binding, shall contain 1

- #reset-cells : from common reset binding, shall contain 1

- #power-domain-cells : from generic power domain binding, shall contain 1

- clocks : shall contain the XO clock

	   shall contain the gpll0 out main clock (msm8998)

- clock-names : shall be "xo"

		shall be "gpll0" (msm8998)



Example:

	gpucc: clock-controller@5090000 {

include/dt-bindings/clock/qcom,gpucc-msm8998.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2019, Jeffrey Hugo

 */



#ifndef _DT_BINDINGS_CLK_MSM_GPUCC_8998_H

#define _DT_BINDINGS_CLK_MSM_GPUCC_8998_H



#define GPUPLL0						0

#define GPUPLL0_OUT_EVEN				1

#define RBCPR_CLK_SRC					2

#define GFX3D_CLK_SRC					3

#define RBBMTIMER_CLK_SRC				4

#define GFX3D_ISENSE_CLK_SRC				5

#define RBCPR_CLK					6

#define GFX3D_CLK					7

#define RBBMTIMER_CLK					8

#define GFX3D_ISENSE_CLK				9

#define GPUCC_CXO_CLK					10



#define GPU_CX_BCR					0

#define RBCPR_BCR					1

#define GPU_GX_BCR					2

#define GPU_ISENSE_BCR					3



#define GPU_CX_GDSC					1

#define GPU_GX_GDSC					2



#endif