Commit 013be5ad authored by Stephen Boyd's avatar Stephen Boyd Committed by Daniel Lezcano
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clocksource: qcom: Implement read_current_timer for udelay



Setup the same timer used as the clocksource to be used as the
read_current_timer implementation. This allows us to support a
stable udelay implementation on MSMs where it's possible for the
CPUs to scale speeds independently of one another.

Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
parent 3f04e3d3
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+13 −0
Original line number Original line Diff line number Diff line
@@ -26,6 +26,8 @@
#include <linux/of_irq.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#include <linux/sched_clock.h>


#include <asm/delay.h>

#define TIMER_MATCH_VAL			0x0000
#define TIMER_MATCH_VAL			0x0000
#define TIMER_COUNT_VAL			0x0004
#define TIMER_COUNT_VAL			0x0004
#define TIMER_ENABLE			0x0008
#define TIMER_ENABLE			0x0008
@@ -179,6 +181,15 @@ static u64 notrace msm_sched_clock_read(void)
	return msm_clocksource.read(&msm_clocksource);
	return msm_clocksource.read(&msm_clocksource);
}
}


static unsigned long msm_read_current_timer(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static struct delay_timer msm_delay_timer = {
	.read_current_timer = msm_read_current_timer,
};

static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
				  bool percpu)
				  bool percpu)
{
{
@@ -217,6 +228,8 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
	if (res)
	if (res)
		pr_err("clocksource_register failed\n");
		pr_err("clocksource_register failed\n");
	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
	msm_delay_timer.freq = dgt_hz;
	register_current_timer_delay(&msm_delay_timer);
}
}


#ifdef CONFIG_ARCH_QCOM
#ifdef CONFIG_ARCH_QCOM